wadd.cgs 4.8 KB

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  1. # Intel(r) Wireless MMX(tm) technology testcase for WADD
  2. # mach: xscale
  3. # as: -mcpu=xscale+iwmmxt
  4. .include "testutils.inc"
  5. start
  6. .global wadd
  7. wadd:
  8. # Enable access to CoProcessors 0 & 1 before
  9. # we attempt these instructions.
  10. mvi_h_gr r1, 3
  11. mcr p15, 0, r1, cr15, cr1, 0
  12. # Test UnSaturated Byte Addition
  13. mvi_h_gr r0, 0x12345678
  14. mvi_h_gr r1, 0x9abcde00
  15. mvi_h_gr r2, 0x11111111
  16. mvi_h_gr r3, 0x11111111
  17. mvi_h_gr r4, 0
  18. mvi_h_gr r5, 0
  19. tmcrr wr0, r0, r1
  20. tmcrr wr1, r2, r3
  21. tmcrr wr2, r4, r5
  22. waddb wr2, wr0, wr1
  23. tmrrc r0, r1, wr0
  24. tmrrc r2, r3, wr1
  25. tmrrc r4, r5, wr2
  26. test_h_gr r0, 0x12345678
  27. test_h_gr r1, 0x9abcde00
  28. test_h_gr r2, 0x11111111
  29. test_h_gr r3, 0x11111111
  30. test_h_gr r4, 0x23456789
  31. test_h_gr r5, 0xabcdef11
  32. # Test Unsigned Saturated Byte Addition
  33. mvi_h_gr r0, 0x12345678
  34. mvi_h_gr r1, 0x9abcde00
  35. mvi_h_gr r2, 0x11111111
  36. mvi_h_gr r3, 0x11111111
  37. mvi_h_gr r4, 0
  38. mvi_h_gr r5, 0
  39. tmcrr wr0, r0, r1
  40. tmcrr wr1, r2, r3
  41. tmcrr wr2, r4, r5
  42. waddbus wr2, wr0, wr1
  43. tmrrc r0, r1, wr0
  44. tmrrc r2, r3, wr1
  45. tmrrc r4, r5, wr2
  46. test_h_gr r0, 0x12345678
  47. test_h_gr r1, 0x9abcde00
  48. test_h_gr r2, 0x11111111
  49. test_h_gr r3, 0x11111111
  50. test_h_gr r4, 0x23456789
  51. test_h_gr r5, 0xabcdef11
  52. # Test Signed Saturated Byte Addition
  53. mvi_h_gr r0, 0x12345678
  54. mvi_h_gr r1, 0x9abcde00
  55. mvi_h_gr r2, 0x11111111
  56. mvi_h_gr r3, 0x11111111
  57. mvi_h_gr r4, 0
  58. mvi_h_gr r5, 0
  59. tmcrr wr0, r0, r1
  60. tmcrr wr1, r2, r3
  61. tmcrr wr2, r4, r5
  62. waddbss wr2, wr0, wr1
  63. tmrrc r0, r1, wr0
  64. tmrrc r2, r3, wr1
  65. tmrrc r4, r5, wr2
  66. test_h_gr r0, 0x12345678
  67. test_h_gr r1, 0x9abcde00
  68. test_h_gr r2, 0x11111111
  69. test_h_gr r3, 0x11111111
  70. test_h_gr r4, 0x2345677f
  71. test_h_gr r5, 0xabcdef11
  72. # Test UnSaturated Halfword Addition
  73. mvi_h_gr r0, 0x12345678
  74. mvi_h_gr r1, 0x9abcde00
  75. mvi_h_gr r2, 0x11111111
  76. mvi_h_gr r3, 0x11111111
  77. mvi_h_gr r4, 0
  78. mvi_h_gr r5, 0
  79. tmcrr wr0, r0, r1
  80. tmcrr wr1, r2, r3
  81. tmcrr wr2, r4, r5
  82. waddh wr2, wr0, wr1
  83. tmrrc r0, r1, wr0
  84. tmrrc r2, r3, wr1
  85. tmrrc r4, r5, wr2
  86. test_h_gr r0, 0x12345678
  87. test_h_gr r1, 0x9abcde00
  88. test_h_gr r2, 0x11111111
  89. test_h_gr r3, 0x11111111
  90. test_h_gr r4, 0x23456789
  91. test_h_gr r5, 0xabcdef11
  92. # Test Unsigned Saturated Halfword Addition
  93. mvi_h_gr r0, 0x12345678
  94. mvi_h_gr r1, 0x9abcde00
  95. mvi_h_gr r2, 0x11111111
  96. mvi_h_gr r3, 0x11111111
  97. mvi_h_gr r4, 0
  98. mvi_h_gr r5, 0
  99. tmcrr wr0, r0, r1
  100. tmcrr wr1, r2, r3
  101. tmcrr wr2, r4, r5
  102. waddhus wr2, wr0, wr1
  103. tmrrc r0, r1, wr0
  104. tmrrc r2, r3, wr1
  105. tmrrc r4, r5, wr2
  106. test_h_gr r0, 0x12345678
  107. test_h_gr r1, 0x9abcde00
  108. test_h_gr r2, 0x11111111
  109. test_h_gr r3, 0x11111111
  110. test_h_gr r4, 0x23456789
  111. test_h_gr r5, 0xabcdef11
  112. # Test Signed Saturated Halfword Addition
  113. mvi_h_gr r0, 0x12345678
  114. mvi_h_gr r1, 0x9abcde00
  115. mvi_h_gr r2, 0x11111111
  116. mvi_h_gr r3, 0x11111111
  117. mvi_h_gr r4, 0
  118. mvi_h_gr r5, 0
  119. tmcrr wr0, r0, r1
  120. tmcrr wr1, r2, r3
  121. tmcrr wr2, r4, r5
  122. waddhss wr2, wr0, wr1
  123. tmrrc r0, r1, wr0
  124. tmrrc r2, r3, wr1
  125. tmrrc r4, r5, wr2
  126. test_h_gr r0, 0x12345678
  127. test_h_gr r1, 0x9abcde00
  128. test_h_gr r2, 0x11111111
  129. test_h_gr r3, 0x11111111
  130. test_h_gr r4, 0x23456789
  131. test_h_gr r5, 0xabcdef11
  132. # Test UnSaturated Word Addition
  133. mvi_h_gr r0, 0x12345678
  134. mvi_h_gr r1, 0x9abcde00
  135. mvi_h_gr r2, 0x11111111
  136. mvi_h_gr r3, 0x11111111
  137. mvi_h_gr r4, 0
  138. mvi_h_gr r5, 0
  139. tmcrr wr0, r0, r1
  140. tmcrr wr1, r2, r3
  141. tmcrr wr2, r4, r5
  142. waddw wr2, wr0, wr1
  143. tmrrc r0, r1, wr0
  144. tmrrc r2, r3, wr1
  145. tmrrc r4, r5, wr2
  146. test_h_gr r0, 0x12345678
  147. test_h_gr r1, 0x9abcde00
  148. test_h_gr r2, 0x11111111
  149. test_h_gr r3, 0x11111111
  150. test_h_gr r4, 0x23456789
  151. test_h_gr r5, 0xabcdef11
  152. # Test Unsigned Saturated Word Addition
  153. mvi_h_gr r0, 0x12345678
  154. mvi_h_gr r1, 0x9abcde00
  155. mvi_h_gr r2, 0x11111111
  156. mvi_h_gr r3, 0x11111111
  157. mvi_h_gr r4, 0
  158. mvi_h_gr r5, 0
  159. tmcrr wr0, r0, r1
  160. tmcrr wr1, r2, r3
  161. tmcrr wr2, r4, r5
  162. waddwus wr2, wr0, wr1
  163. tmrrc r0, r1, wr0
  164. tmrrc r2, r3, wr1
  165. tmrrc r4, r5, wr2
  166. test_h_gr r0, 0x12345678
  167. test_h_gr r1, 0x9abcde00
  168. test_h_gr r2, 0x11111111
  169. test_h_gr r3, 0x11111111
  170. test_h_gr r4, 0x23456789
  171. test_h_gr r5, 0xabcdef11
  172. # Test Signed Saturated Word Addition
  173. mvi_h_gr r0, 0x12345678
  174. mvi_h_gr r1, 0x9abcde00
  175. mvi_h_gr r2, 0x11111111
  176. mvi_h_gr r3, 0x11111111
  177. mvi_h_gr r4, 0
  178. mvi_h_gr r5, 0
  179. tmcrr wr0, r0, r1
  180. tmcrr wr1, r2, r3
  181. tmcrr wr2, r4, r5
  182. waddwss wr2, wr0, wr1
  183. tmrrc r0, r1, wr0
  184. tmrrc r2, r3, wr1
  185. tmrrc r4, r5, wr2
  186. test_h_gr r0, 0x12345678
  187. test_h_gr r1, 0x9abcde00
  188. test_h_gr r2, 0x11111111
  189. test_h_gr r3, 0x11111111
  190. test_h_gr r4, 0x23456789
  191. test_h_gr r5, 0xabcdef11
  192. pass