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- # Intel(r) Wireless MMX(tm) technology testcase for WSLL
- # mach: xscale
- # as: -mcpu=xscale+iwmmxt
- .include "testutils.inc"
- start
- .global wsll
- wsll:
- # Enable access to CoProcessors 0 & 1 before
- # we attempt these instructions.
- mvi_h_gr r1, 3
- mcr p15, 0, r1, cr15, cr1, 0
- # Test Halfword Logical Shift Left
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdef0
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsllh wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdef0
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x23406780
- test_h_gr r5, 0xabc0ef00
-
- # Test Halfword Aritc Shift Left by CG register
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdef0
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0
- mvi_h_gr r4, 0
- tmcrr wr0, r0, r1
- tmcr wcgr1, r2
- tmcrr wr1, r3, r4
- wsllhg wr1, wr0, wcgr1
-
- tmrrc r0, r1, wr0
- tmrc r2, wcgr1
- tmrrc r3, r4, wr1
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdef0
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x23406780
- test_h_gr r4, 0xabc0ef00
-
- # Test Word Logical Shift Left
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdef0
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsllw wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdef0
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x23456780
- test_h_gr r5, 0xabcdef00
-
- # Test Word Logical Shift Left by CG register
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdef0
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0
- mvi_h_gr r4, 0
- tmcrr wr0, r0, r1
- tmcr wcgr2, r2
- tmcrr wr1, r3, r4
- wsllwg wr1, wr0, wcgr2
-
- tmrrc r0, r1, wr0
- tmrc r2, wcgr2
- tmrrc r3, r4, wr1
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdef0
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x23456780
- test_h_gr r4, 0xabcdef00
-
- # Test Double Word Logical Shift Left
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdefc
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wslld wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdefc
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x23456780
- test_h_gr r5, 0xabcdefc1
-
- # Test Double Word Logical Shift Left by CG register
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdefc
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0
- mvi_h_gr r4, 0
- tmcrr wr0, r0, r1
- tmcr wcgr3, r2
- tmcrr wr1, r3, r4
- wslldg wr1, wr0, wcgr3
-
- tmrrc r0, r1, wr0
- tmrc r2, wcgr3
- tmrrc r3, r4, wr1
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdefc
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x23456780
- test_h_gr r4, 0xabcdefc1
-
- pass
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