| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167 |
- # Intel(r) Wireless MMX(tm) technology testcase for WSRL
- # mach: xscale
- # as: -mcpu=xscale+iwmmxt
- .include "testutils.inc"
- start
- .global wsrl
- wsrl:
- # Enable access to CoProcessors 0 & 1 before
- # we attempt these instructions.
- mvi_h_gr r1, 3
- mcr p15, 0, r1, cr15, cr1, 0
- # Test Halfword Logical Shift Right
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdef0
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsrlh wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdef0
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01230567
- test_h_gr r5, 0x09ab0def
-
- # Test Halfword Logical Shift Right by CG register
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdef0
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0
- mvi_h_gr r4, 0
- tmcrr wr0, r0, r1
- tmcr wcgr1, r2
- tmcrr wr1, r3, r4
- wsrlhg wr1, wr0, wcgr1
-
- tmrrc r0, r1, wr0
- tmrc r2, wcgr1
- tmrrc r3, r4, wr1
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdef0
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x01230567
- test_h_gr r4, 0x09ab0def
-
- # Test Word Logical Shift Right
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdef0
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsrlw wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdef0
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x09abcdef
-
- # Test Word Logical Shift Right by CG register
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdef0
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0
- mvi_h_gr r4, 0
- tmcrr wr0, r0, r1
- tmcr wcgr2, r2
- tmcrr wr1, r3, r4
- wsrlwg wr1, wr0, wcgr2
-
- tmrrc r0, r1, wr0
- tmrc r2, wcgr2
- tmrrc r3, r4, wr1
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdef0
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x01234567
- test_h_gr r4, 0x09abcdef
-
- # Test Double Word Logical Shift Right
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdefc
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsrld wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdefc
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0xc1234567
- test_h_gr r5, 0x09abcdef
-
- # Test Double Word Logical Shift Right by CG register
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcdefc
- mvi_h_gr r2, 0x11111104
- mvi_h_gr r3, 0
- mvi_h_gr r4, 0
- tmcrr wr0, r0, r1
- tmcr wcgr3, r2
- tmcrr wr1, r3, r4
- wsrldg wr1, wr0, wcgr3
-
- tmrrc r0, r1, wr0
- tmrc r2, wcgr3
- tmrrc r3, r4, wr1
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcdefc
- test_h_gr r2, 0x11111104
- test_h_gr r3, 0xc1234567
- test_h_gr r4, 0x09abcdef
-
- pass
|
