| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251 |
- # Intel(r) Wireless MMX(tm) technology testcase for WSUB
- # mach: xscale
- # as: -mcpu=xscale+iwmmxt
- .include "testutils.inc"
- start
- .global wsub
- wsub:
- # Enable access to CoProcessors 0 & 1 before
- # we attempt these instructions.
- mvi_h_gr r1, 3
- mcr p15, 0, r1, cr15, cr1, 0
- # Test Unsaturated Byte subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubb wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abcdef
-
- # Test Unsigned saturated Byte subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubbus wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abcd00
-
- # Test Signed saturated Byte subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubbss wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abcdef
-
- # Test Unsaturated Halfword subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubh wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abccef
-
- # Test Unsigned saturated Halfword subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubhus wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abccef
-
- # Test Signed saturated Halfword subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubhss wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abccef
-
- # Test Unsaturated Word subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubw wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abccef
-
- # Test Unsigned saturated Word subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubwus wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abccef
-
- # Test Signed saturated Word subtraction
-
- mvi_h_gr r0, 0x12345678
- mvi_h_gr r1, 0x9abcde00
- mvi_h_gr r2, 0x11111111
- mvi_h_gr r3, 0x11111111
- mvi_h_gr r4, 0
- mvi_h_gr r5, 0
- tmcrr wr0, r0, r1
- tmcrr wr1, r2, r3
- tmcrr wr2, r4, r5
- wsubwss wr2, wr0, wr1
-
- tmrrc r0, r1, wr0
- tmrrc r2, r3, wr1
- tmrrc r4, r5, wr2
-
- test_h_gr r0, 0x12345678
- test_h_gr r1, 0x9abcde00
- test_h_gr r2, 0x11111111
- test_h_gr r3, 0x11111111
- test_h_gr r4, 0x01234567
- test_h_gr r5, 0x89abccef
-
- pass
|
