binutils-gdb/sim/testsuite/frv/fcbulr.cgs

# frv testcase for fcbulr $FCCi,$ccond,$hint
# mach: all

	.include "testutils.inc"

	start

	.global fcbulr
fcbulr:
	; ccond is true
	set_spr_immed	128,lcr
	set_spr_addr	bad,lr
	set_fcc		0x0 0
	fcbulr		fcc0,0,0

	set_spr_addr	ok2,lr
	set_fcc		0x1 1
	fcbulr		fcc1,0,1
	fail
ok2:
	set_spr_addr	bad,lr
	set_fcc		0x2 2
	fcbulr		fcc2,0,2

	set_spr_addr	ok4,lr
	set_fcc		0x3 3
	fcbulr		fcc3,0,3
	fail
ok4:
	set_spr_addr	bad,lr
	set_fcc		0x4 0
	fcbulr		fcc0,0,0

	set_spr_addr	ok6,lr
	set_fcc		0x5 1
	fcbulr		fcc1,0,1
	fail
ok6:
	set_spr_addr	bad,lr
	set_fcc		0x6 2
	fcbulr		fcc2,0,2

	set_spr_addr	ok8,lr
	set_fcc		0x7 3
	fcbulr		fcc3,0,3
	fail
ok8:
	set_spr_addr	bad,lr
	set_fcc		0x8 0
	fcbulr		fcc0,0,0

	set_spr_addr	oka,lr
	set_fcc		0x9 1
	fcbulr		fcc1,0,1
	fail
oka:
	set_spr_addr	bad,lr
	set_fcc		0xa 2
	fcbulr		fcc2,0,2

	set_spr_addr	okc,lr
	set_fcc		0xb 3
	fcbulr		fcc3,0,3
	fail
okc:
	set_spr_addr	bad,lr
	set_fcc		0xc 0
	fcbulr		fcc0,0,0

	set_spr_addr	oke,lr
	set_fcc		0xd 1
	fcbulr		fcc1,0,1
	fail
oke:
	set_spr_addr	bad,lr
	set_fcc		0xe 2
	fcbulr		fcc2,0,2

	set_spr_addr	okg,lr
	set_fcc		0xf 3
	fcbulr		fcc3,0,3
	fail
okg:

	; ccond is true
	set_spr_immed	1,lcr
	set_spr_addr	bad,lr
	set_fcc		0x0 0
	fcbulr		fcc0,1,0

	set_spr_immed	1,lcr
	set_spr_addr	oki,lr
	set_fcc		0x1 1
	fcbulr		fcc1,1,1
	fail
oki:
	set_spr_immed	1,lcr
	set_spr_addr	bad,lr
	set_fcc		0x2 2
	fcbulr		fcc2,1,2

	set_spr_immed	1,lcr
	set_spr_addr	okk,lr
	set_fcc		0x3 3
	fcbulr		fcc3,1,3
	fail
okk:
	set_spr_immed	1,lcr
	set_spr_addr	bad,lr
	set_fcc		0x4 0
	fcbulr		fcc0,1,0

	set_spr_immed	1,lcr
	set_spr_addr	okm,lr
	set_fcc		0x5 1
	fcbulr		fcc1,1,1
	fail
okm:
	set_spr_immed	1,lcr
	set_spr_addr	bad,lr
	set_fcc		0x6 2
	fcbulr		fcc2,1,2

	set_spr_immed	1,lcr
	set_spr_addr	oko,lr
	set_fcc		0x7 3
	fcbulr		fcc3,1,3
	fail
oko:
	set_spr_immed	1,lcr
	set_spr_addr	bad,lr
	set_fcc		0x8 0
	fcbulr		fcc0,1,0

	set_spr_immed	1,lcr
	set_spr_addr	okq,lr
	set_fcc		0x9 1
	fcbulr		fcc1,1,1
	fail
okq:
	set_spr_immed	1,lcr
	set_spr_addr	bad,lr
	set_fcc		0xa 2
	fcbulr		fcc2,1,2

	set_spr_immed	1,lcr
	set_spr_addr	oks,lr
	set_fcc		0xb 3
	fcbulr		fcc3,1,3
	fail
oks:
	set_spr_immed	1,lcr
	set_spr_addr	bad,lr
	set_fcc		0xc 0
	fcbulr		fcc0,1,0

	set_spr_immed	1,lcr
	set_spr_addr	oku,lr
	set_fcc		0xd 1
	fcbulr		fcc1,1,1
	fail
oku:
	set_spr_immed	1,lcr
	set_spr_addr	bad,lr
	set_fcc		0xe 2
	fcbulr		fcc2,1,2

	set_spr_immed	1,lcr
	set_spr_addr	okw,lr
	set_fcc		0xf 3
	fcbulr		fcc3,1,3
	fail
okw:
	; ccond is false
	set_spr_immed	128,lcr

	set_fcc		0x0 0
	fcbulr	fcc0,1,0
	set_fcc		0x1 1
	fcbulr	fcc1,1,1
	set_fcc		0x2 2
	fcbulr	fcc2,1,2
	set_fcc		0x3 3
	fcbulr	fcc3,1,3
	set_fcc		0x4 0
	fcbulr	fcc0,1,0
	set_fcc		0x5 1
	fcbulr	fcc1,1,1
	set_fcc		0x6 2
	fcbulr	fcc2,1,2
	set_fcc		0x7 3
	fcbulr	fcc3,1,3
	set_fcc		0x8 0
	fcbulr	fcc0,1,0
	set_fcc		0x9 1
	fcbulr	fcc1,1,1
	set_fcc		0xa 2
	fcbulr	fcc2,1,2
	set_fcc		0xb 3
	fcbulr	fcc3,1,3
	set_fcc		0xc 0
	fcbulr	fcc0,1,0
	set_fcc		0xd 1
	fcbulr	fcc1,1,1
	set_fcc		0xe 2
	fcbulr	fcc2,1,2
	set_fcc		0xf 3
	fcbulr	fcc3,1,3

	; ccond is false
	set_spr_immed	1,lcr
	set_fcc		0x0 0
	fcbulr	fcc0,0,0
	set_spr_immed	1,lcr
	set_fcc		0x1 1
	fcbulr	fcc1,0,1
	set_spr_immed	1,lcr
	set_fcc		0x2 2
	fcbulr	fcc2,0,2
	set_spr_immed	1,lcr
	set_fcc		0x3 3
	fcbulr	fcc3,0,3
	set_spr_immed	1,lcr
	set_fcc		0x4 0
	fcbulr	fcc0,0,0
	set_spr_immed	1,lcr
	set_fcc		0x5 1
	fcbulr	fcc1,0,1
	set_spr_immed	1,lcr
	set_fcc		0x6 2
	fcbulr	fcc2,0,2
	set_spr_immed	1,lcr
	set_fcc		0x7 3
	fcbulr	fcc3,0,3
	set_spr_immed	1,lcr
	set_fcc		0x8 0
	fcbulr	fcc0,0,0
	set_spr_immed	1,lcr
	set_fcc		0x9 1
	fcbulr	fcc1,0,1
	set_spr_immed	1,lcr
	set_fcc		0xa 2
	fcbulr	fcc2,0,2
	set_spr_immed	1,lcr
	set_fcc		0xb 3
	fcbulr	fcc3,0,3
	set_spr_immed	1,lcr
	set_fcc		0xc 0
	fcbulr	fcc0,0,0
	set_spr_immed	1,lcr
	set_fcc		0xd 1
	fcbulr	fcc1,0,1
	set_spr_immed	1,lcr
	set_fcc		0xe 2
	fcbulr	fcc2,0,2
	set_spr_immed	1,lcr
	set_fcc		0xf 3
	fcbulr	fcc3,0,3

	pass
bad:
	fail