ftiul.cgs 2.1 KB

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  1. # frv testcase for ftiul $FCCi_2,$GRi,$s12
  2. # mach: all
  3. .include "testutils.inc"
  4. start
  5. .global ftiul
  6. ftiul:
  7. and_spr_immed -4081,tbr ; clear tbr.tt
  8. set_gr_spr tbr,gr7
  9. inc_gr_immed 2112,gr7 ; address of exception handler
  10. set_bctrlr_0_0 gr7 ; bctrlr 0,0
  11. set_spr_immed 128,lcr
  12. set_gr_immed 0,gr7
  13. set_spr_addr bad,lr
  14. set_fcc 0x0 0
  15. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  16. set_psr_et 1
  17. set_spr_addr ok1,lr
  18. set_fcc 0x1 0
  19. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  20. fail
  21. ok1:
  22. set_spr_addr bad,lr
  23. set_fcc 0x2 0
  24. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  25. set_psr_et 1
  26. set_spr_addr ok3,lr
  27. set_fcc 0x3 0
  28. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  29. fail
  30. ok3:
  31. set_psr_et 1
  32. set_spr_addr ok4,lr
  33. set_fcc 0x4 0
  34. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  35. fail
  36. ok4:
  37. set_psr_et 1
  38. set_spr_addr ok5,lr
  39. set_fcc 0x5 0
  40. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  41. fail
  42. ok5:
  43. set_psr_et 1
  44. set_spr_addr ok6,lr
  45. set_fcc 0x6 0
  46. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  47. fail
  48. ok6:
  49. set_psr_et 1
  50. set_spr_addr ok7,lr
  51. set_fcc 0x7 0
  52. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  53. fail
  54. ok7:
  55. set_spr_addr bad,lr
  56. set_fcc 0x8 0
  57. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  58. set_psr_et 1
  59. set_spr_addr ok9,lr
  60. set_fcc 0x9 0
  61. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  62. fail
  63. ok9:
  64. set_spr_addr bad,lr
  65. set_fcc 0xa 0
  66. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  67. set_psr_et 1
  68. set_spr_addr okb,lr
  69. set_fcc 0xb 0
  70. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  71. fail
  72. okb:
  73. set_psr_et 1
  74. set_spr_addr okc,lr
  75. set_fcc 0xc 0
  76. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  77. fail
  78. okc:
  79. set_psr_et 1
  80. set_spr_addr okd,lr
  81. set_fcc 0xd 0
  82. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  83. fail
  84. okd:
  85. set_psr_et 1
  86. set_spr_addr oke,lr
  87. set_fcc 0xe 0
  88. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  89. fail
  90. oke:
  91. set_psr_et 1
  92. set_spr_addr okf,lr
  93. set_fcc 0xf 0
  94. ftiul fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16
  95. fail
  96. okf:
  97. pass
  98. bad:
  99. fail