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- # frv testcase for nfmuls $FRi,$FRj,$FRk
- # mach: fr500 fr550 frv
- .include "testutils.inc"
- float_constants
- start
- load_float_constants
- .global nfmuls
- nfmuls:
- nfmuls fr16,fr4,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr8,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr12,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr16,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr20,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr24,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr28,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr32,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr36,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr40,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr44,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr16,fr48,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr4,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr8,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr12,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr16,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr20,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr24,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr28,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr32,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr36,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr40,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr44,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr20,fr48,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr0,fr1
- test_fr_fr fr1,fr0
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr4,fr1
- test_fr_fr fr1,fr4
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr8,fr1
- test_fr_fr fr1,fr8
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr12,fr1
- test_fr_fr fr1,fr12
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr16,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr20,fr1
- test_fr_fr fr1,fr16
- test_fr_fr fr1,fr20
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr24,fr1
- test_fr_fr fr1,fr24
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr28,fr1
- test_fr_fr fr1,fr28
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr32,fr1
- test_fr_fr fr1,fr32
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr36,fr1
- test_fr_fr fr1,fr36
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr40,fr1
- test_fr_fr fr1,fr40
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr44,fr1
- test_fr_fr fr1,fr44
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr48,fr1
- test_fr_fr fr1,fr48
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr52,fr1
- test_fr_fr fr1,fr52
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr28,fr8,fr1
- test_fr_fr fr1,fr8
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr8,fr28,fr1
- test_fr_fr fr1,fr8
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr32,fr36,fr1
- test_fr_fr fr1,fr40
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- ; try to cause exceptions
- nfmuls fr48,fr32,fr1
- ; test_fr_fr fr1,fr44
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr52,fr28,fr1
- ; test_fr_fr fr1,fr44
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr56,fr28,fr1
- ; test_fr_fr fr1,fr44
- test_spr_immed 0,fner1
- test_spr_immed 0,fner0
- nfmuls fr60,fr28,fr1
- ; test_fr_fr fr1,fr44
- test_spr_immed 2,fner1
- test_spr_immed 0,fner0
- pass
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