123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580 |
- # Hitachi H8 testcase 'exts.w, extu.w'
- # mach(): h8300h h8300s h8sx
- # as(h8300): --defsym sim_cpu=0
- # as(h8300h): --defsym sim_cpu=1
- # as(h8300s): --defsym sim_cpu=2
- # as(h8sx): --defsym sim_cpu=3
- # ld(h8300h): -m h8300helf
- # ld(h8300s): -m h8300self
- # ld(h8sx): -m h8300sxelf
- .include "testutils.inc"
- start
- .data
- .align 2
- pos: .word 0xff01
- neg: .word 0x0080
- .text
- exts_w_reg16_p:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w rn16
- mov.b #1, r0l
- exts.w r0
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 0xa5a50001 er0 ; result of sign extend
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- exts_w_reg16_n:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w rn16
- mov.b #0xff, r0l
- exts.w r0
- ;; Test ccr H=0 N=1 Z=0 V=0 C=0
- test_neg_set
- test_zero_clear
- test_ovf_clear
- test_carry_clear
- test_h_gr32 0xa5a5ffff er0 ; result of sign extend
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- extu_w_reg16_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w rn16
- mov.b #0xff, r0l
- extu.w r0
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 0xa5a500ff er0 ; result of zero extend
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- .if (sim_cpu == h8sx)
- exts_w_ind_p:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @ern
- mov.l #pos, er1
- exts.w @er1
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 pos er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0001, @pos
- beq .Lswindp
- fail
- .Lswindp:
- mov.w #0xff01, @pos ; Restore initial value
- exts_w_ind_n:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @ern
- mov.l #neg, er1
- exts.w @er1
- ;; Test ccr H=0 N=1 Z=0 V=0 C=0
- test_neg_set
- test_zero_clear
- test_ovf_clear
- test_carry_clear
- test_h_gr32 neg er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0xff80, @neg
- beq .Lswindn
- fail
- .Lswindn:
- ;; Note: leave the value as 0xff80, so that extu has work to do.
-
- extu_w_ind_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @ern
- mov.l #neg, er1
- extu.w @er1
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 neg er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwindn
- fail
- .Luwindn:
- ;; Note: leave the value as 0x0080, like it started out.
- exts_w_postinc_p:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @ern+
- mov.l #pos, er1
- exts.w @er1+
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 pos+2 er1 ; er1 still contains target address plus 2
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0001, @pos
- beq .Lswpostincp
- fail
- .Lswpostincp:
- mov.w #0xff01, @pos ; Restore initial value
- exts_w_postinc_n:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @ern+
- mov.l #neg, er1
- exts.w @er1+
- ;; Test ccr H=0 N=1 Z=0 V=0 C=0
- test_neg_set
- test_zero_clear
- test_ovf_clear
- test_carry_clear
- test_h_gr32 neg+2 er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0xff80, @neg
- beq .Lswpostincn
- fail
- .Lswpostincn:
- ;; Note: leave the value as 0xff80, so that extu has work to do.
-
- extu_w_postinc_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @ern+
- mov.l #neg, er1
- extu.w @er1+
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 neg+2 er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwpostincn
- fail
- .Luwpostincn:
- ;; Note: leave the value as 0x0080, like it started out.
- exts_w_postdec_p:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @ern-
- mov.l #pos, er1
- exts.w @er1-
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 pos-2 er1 ; er1 still contains target address plus 2
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0001, @pos
- beq .Lswpostdecp
- fail
- .Lswpostdecp:
- mov.w #0xff01, @pos ; Restore initial value
- exts_w_postdec_n:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @ern-
- mov.l #neg, er1
- exts.w @er1-
- ;; Test ccr H=0 N=1 Z=0 V=0 C=0
- test_neg_set
- test_zero_clear
- test_ovf_clear
- test_carry_clear
- test_h_gr32 neg-2 er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0xff80, @neg
- beq .Lswpostdecn
- fail
- .Lswpostdecn:
- ;; Note: leave the value as 0xff80, so that extu has work to do.
-
- extu_w_postdec_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @ern-
- mov.l #neg, er1
- extu.w @er1-
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 neg-2 er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwpostdecn
- fail
- .Luwpostdecn:
- ;; Note: leave the value as 0x0080, like it started out.
- exts_w_preinc_p:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @+ern
- mov.l #pos-2, er1
- exts.w @+er1
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 pos er1 ; er1 still contains target address plus 2
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0001, @pos
- beq .Lswpreincp
- fail
- .Lswpreincp:
- mov.w #0xff01, @pos ; Restore initial value
- exts_w_preinc_n:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @+ern
- mov.l #neg-2, er1
- exts.w @+er1
- ;; Test ccr H=0 N=1 Z=0 V=0 C=0
- test_neg_set
- test_zero_clear
- test_ovf_clear
- test_carry_clear
- test_h_gr32 neg er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0xff80, @neg
- beq .Lswpreincn
- fail
- .Lswpreincn:
- ;; Note: leave the value as 0xff80, so that extu has work to do.
-
- extu_w_preinc_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @+ern
- mov.l #neg-2, er1
- extu.w @+er1
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 neg er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwpreincn
- fail
- .Luwpreincn:
- ;; Note: leave the value as 0x0080, like it started out.
- exts_w_predec_p:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @-ern
- mov.l #pos+2, er1
- exts.w @-er1
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 pos er1 ; er1 still contains target address plus 2
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0001, @pos
- beq .Lswpredecp
- fail
- .Lswpredecp:
- mov.w #0xff01, @pos ; Restore initial value
- exts_w_predec_n:
- set_grs_a5a5
- set_ccr_zero
- ;; exts.w @-ern
- mov.l #neg+2, er1
- exts.w @-er1
- ;; Test ccr H=0 N=1 Z=0 V=0 C=0
- test_neg_set
- test_zero_clear
- test_ovf_clear
- test_carry_clear
- test_h_gr32 neg er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0xff80, @neg
- beq .Lswpredecn
- fail
- .Lswpredecn:
- ;; Note: leave the value as 0xff80, so that extu has work to do.
-
- extu_w_predec_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @-ern
- mov.l #neg+2, er1
- extu.w @-er1
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 neg er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwpredecn
- fail
- .Luwpredecn:
- ;; Note: leave the value as 0x0080, like it started out.
- extu_w_disp2_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @(dd:2, ern)
- mov.l #neg-2, er1
- extu.w @(2:2, er1)
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 neg-2 er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwdisp2n
- fail
- .Luwdisp2n:
- ;; Note: leave the value as 0x0080, like it started out.
- extu_w_disp16_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @(dd:16, ern)
- mov.l #neg-44, er1
- extu.w @(44:16, er1)
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 neg-44 er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwdisp16n
- fail
- .Luwdisp16n:
- ;; Note: leave the value as 0x0080, like it started out.
- extu_w_disp32_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @(dd:32, ern)
- mov.l #neg+444, er1
- extu.w @(-444:32, er1)
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_h_gr32 neg+444 er1 ; er1 still contains target address
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwdisp32n
- fail
- .Luwdisp32n:
- ;; Note: leave the value as 0x0080, like it started out.
- extu_w_abs16_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @aa:16
- extu.w @neg:16
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 1
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwabs16n
- fail
- .Luwabs16n:
- ;; Note: leave the value as 0x0080, like it started out.
- extu_w_abs32_n:
- set_grs_a5a5
- set_ccr_zero
- ;; extu.w @aa:32
- extu.w @neg:32
- ;; Test ccr H=0 N=0 Z=0 V=0 C=0
- test_cc_clear
- test_gr_a5a5 0 ; Make sure other general regs not disturbed
- test_gr_a5a5 1
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- cmp.w #0x0080, @neg
- beq .Luwabs32n
- fail
- .Luwabs32n:
- ;; Note: leave the value as 0x0080, like it started out.
- .endif
- pass
- exit 0
|