123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375 |
- # Hitachi H8 testcase 'ldc'
- # mach(): all
- # as(h8300): --defsym sim_cpu=0
- # as(h8300h): --defsym sim_cpu=1
- # as(h8300s): --defsym sim_cpu=2
- # as(h8sx): --defsym sim_cpu=3
- # ld(h8300h): -m h8300helf
- # ld(h8300s): -m h8300self
- # ld(h8sx): -m h8300sxelf
- .include "testutils.inc"
- .data
- byte_pre:
- .byte 0
- byte_src:
- .byte 0xff
- byte_post:
- .byte 0
-
- start
- ldc_imm8_ccr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0xff, ccr ; set all ccr flags high, immediate operand
- bcs .L1 ; carry flag set?
- fail
- .L1: bvs .L2 ; overflow flag set?
- fail
- .L2: beq .L3 ; zero flag set?
- fail
- .L3: bmi .L4 ; neg flag set?
- fail
- .L4:
- ldc #0, ccr ; set all ccr flags low, immediate operand
- bcc .L5 ; carry flag clear?
- fail
- .L5: bvc .L6 ; overflow flag clear?
- fail
- .L6: bne .L7 ; zero flag clear?
- fail
- .L7: bpl .L8 ; neg flag clear?
- fail
- .L8:
- test_cc_clear
- test_grs_a5a5
-
- ldc_reg8_ccr:
- set_grs_a5a5
- set_ccr_zero
- mov #0xff, r0h
- ldc r0h, ccr ; set all ccr flags high, reg operand
- bcs .L11 ; carry flag set?
- fail
- .L11: bvs .L12 ; overflow flag set?
- fail
- .L12: beq .L13 ; zero flag set?
- fail
- .L13: bmi .L14 ; neg flag set?
- fail
- .L14:
- mov #0, r0h
- ldc r0h, ccr ; set all ccr flags low, reg operand
- bcc .L15 ; carry flag clear?
- fail
- .L15: bvc .L16 ; overflow flag clear?
- fail
- .L16: bne .L17 ; zero flag clear?
- fail
- .L17: bpl .L18 ; neg flag clear?
- fail
- .L18:
- test_cc_clear
- test_h_gr16 0x00a5 r0 ; Register 0 modified by test procedure.
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- .if (sim_cpu == h8300s || sim_cpu == h8sx) ; Earlier versions, no exr
- ldc_imm8_exr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0, exr
- ldc #0x87, exr ; set exr to 0x87
- stc exr, r0l ; retrieve and check exr value
- cmp.b #0x87, r0l
- beq .L19
- fail
- .L19:
- test_h_gr16 0xa587 r0 ; Register 0 modified by test procedure.
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
-
- ldc_reg8_exr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0, exr
- mov #0x87, r0h
- ldc r0h, exr ; set exr to 0x87
- stc exr, r0l ; retrieve and check exr value
- cmp.b #0x87, r0l
- beq .L21
- fail
- .L21:
- test_h_gr16 0x8787 r0 ; Register 0 modified by test procedure.
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_abs16_ccr:
- set_grs_a5a5
- set_ccr_zero
- ldc @byte_src:16, ccr ; abs16 src
- stc ccr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_abs16_exr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0, exr
- ldc @byte_src:16, exr ; abs16 src
- stc exr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_abs32_ccr:
- set_grs_a5a5
- set_ccr_zero
- ldc @byte_src:32, ccr ; abs32 src
- stc ccr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_abs32_exr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0, exr
- ldc @byte_src:32, exr ; abs32 src
- stc exr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
- test_gr_a5a5 1 ; Make sure other general regs not disturbed
- test_gr_a5a5 2
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_disp16_ccr:
- set_grs_a5a5
- set_ccr_zero
- mov #byte_pre, er1
- ldc @(1:16, er1), ccr ; disp16 src
- stc ccr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
- test_h_gr32 byte_pre, er1 ; er1 still contains address
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_disp16_exr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0, exr
- mov #byte_post, er1
- ldc @(-1:16, er1), exr ; disp16 src
- stc exr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
- test_h_gr32 byte_post, er1 ; er1 still contains address
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_disp32_ccr:
- set_grs_a5a5
- set_ccr_zero
- mov #byte_pre, er1
- ldc @(1:32, er1), ccr ; disp32 src
- stc ccr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
- test_h_gr32 byte_pre, er1 ; er1 still contains address
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_disp32_exr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0, exr
- mov #byte_post, er1
- ldc @(-1:32, er1), exr ; disp16 src
- stc exr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
- test_h_gr32 byte_post, er1 ; er1 still contains address
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_postinc_ccr:
- set_grs_a5a5
- set_ccr_zero
- mov #byte_src, er1
- ldc @er1+, ccr ; postinc src
- stc ccr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
- test_h_gr32 byte_src+2, er1 ; er1 still contains address
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
-
- ldc_postinc_exr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0, exr
- mov #byte_src, er1
- ldc @er1+, exr ; postinc src
- stc exr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
- test_h_gr32 byte_src+2, er1 ; er1 still contains address
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
-
- ldc_ind_ccr:
- set_grs_a5a5
- set_ccr_zero
- mov #byte_src, er1
- ldc @er1, ccr ; postinc src
- stc ccr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a5ff er0 ; ff in r0l, a5 elsewhere.
- test_h_gr32 byte_src, er1 ; er1 still contains address
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
-
- ldc_ind_exr:
- set_grs_a5a5
- set_ccr_zero
- ldc #0, exr
- mov #byte_src, er1
- ldc @er1, exr ; postinc src
- stc exr, r0l ; copy into general reg
- test_h_gr32 0xa5a5a587 er0 ; 87 in r0l, a5 elsewhere.
- test_h_gr32 byte_src, er1 ; er1 still contains address
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
-
- .endif
-
- .if (sim_cpu == h8sx) ; New vbr and sbr registers for h8sx
- ldc_reg_sbr:
- set_grs_a5a5
- set_ccr_zero
- mov #0xaaaaaaaa, er0
- ldc er0, sbr ; set sbr to 0xaaaaaaaa
- stc sbr, er1 ; retreive and check sbr value
- test_h_gr32 0xaaaaaaaa er1
- test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- ldc_reg_vbr:
- set_grs_a5a5
- set_ccr_zero
- mov #0xaaaaaaaa, er0
- ldc er0, vbr ; set sbr to 0xaaaaaaaa
- stc vbr, er1 ; retreive and check sbr value
- test_h_gr32 0xaaaaaaaa er1
- test_h_gr32 0xaaaaaaaa er0 ; Register 0 modified by test procedure.
- test_gr_a5a5 2 ; Make sure other general regs not disturbed
- test_gr_a5a5 3
- test_gr_a5a5 4
- test_gr_a5a5 5
- test_gr_a5a5 6
- test_gr_a5a5 7
- .endif
- pass
- exit 0
|