cpu-mips.c 6.5 KB

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  1. /* bfd back-end for mips support
  2. Copyright (C) 1990-2022 Free Software Foundation, Inc.
  3. Written by Steve Chamberlain of Cygnus Support.
  4. This file is part of BFD, the Binary File Descriptor library.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 3 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program; if not, write to the Free Software
  15. Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  16. MA 02110-1301, USA. */
  17. #include "sysdep.h"
  18. #include "bfd.h"
  19. #include "libbfd.h"
  20. static const bfd_arch_info_type *mips_compatible
  21. (const bfd_arch_info_type *, const bfd_arch_info_type *);
  22. /* The default routine tests bits_per_word, which is wrong on mips as
  23. mips word size doesn't correlate with reloc size. */
  24. static const bfd_arch_info_type *
  25. mips_compatible (const bfd_arch_info_type *a, const bfd_arch_info_type *b)
  26. {
  27. if (a->arch != b->arch)
  28. return NULL;
  29. /* Machine compatibility is checked in
  30. _bfd_mips_elf_merge_private_bfd_data. */
  31. return a;
  32. }
  33. #define N(BITS_WORD, BITS_ADDR, NUMBER, PRINT, DEFAULT, NEXT) \
  34. { \
  35. BITS_WORD, /* Bits in a word. */ \
  36. BITS_ADDR, /* Bits in an address. */ \
  37. 8, /* Bits in a byte. */ \
  38. bfd_arch_mips, \
  39. NUMBER, \
  40. "mips", \
  41. PRINT, \
  42. 3, \
  43. DEFAULT, \
  44. mips_compatible, \
  45. bfd_default_scan, \
  46. bfd_arch_default_fill, \
  47. NEXT, \
  48. 0 /* Maximum offset of a reloc from the start of an insn. */ \
  49. }
  50. enum
  51. {
  52. I_mips3000,
  53. I_mips3900,
  54. I_mips4000,
  55. I_mips4010,
  56. I_mips4100,
  57. I_mips4111,
  58. I_mips4120,
  59. I_mips4300,
  60. I_mips4400,
  61. I_mips4600,
  62. I_mips4650,
  63. I_mips5000,
  64. I_mips5400,
  65. I_mips5500,
  66. I_mips5900,
  67. I_mips6000,
  68. I_mips7000,
  69. I_mips8000,
  70. I_mips9000,
  71. I_mips10000,
  72. I_mips12000,
  73. I_mips14000,
  74. I_mips16000,
  75. I_mips16,
  76. I_mips5,
  77. I_mipsisa32,
  78. I_mipsisa32r2,
  79. I_mipsisa32r3,
  80. I_mipsisa32r5,
  81. I_mipsisa32r6,
  82. I_mipsisa64,
  83. I_mipsisa64r2,
  84. I_mipsisa64r3,
  85. I_mipsisa64r5,
  86. I_mipsisa64r6,
  87. I_sb1,
  88. I_loongson_2e,
  89. I_loongson_2f,
  90. I_gs464,
  91. I_gs464e,
  92. I_gs264e,
  93. I_mipsocteon,
  94. I_mipsocteonp,
  95. I_mipsocteon2,
  96. I_mipsocteon3,
  97. I_xlr,
  98. I_interaptiv_mr2,
  99. I_micromips
  100. };
  101. #define NN(index) (&arch_info_struct[(index) + 1])
  102. static const bfd_arch_info_type arch_info_struct[] =
  103. {
  104. N (32, 32, bfd_mach_mips3000, "mips:3000", false, NN(I_mips3000)),
  105. N (32, 32, bfd_mach_mips3900, "mips:3900", false, NN(I_mips3900)),
  106. N (64, 64, bfd_mach_mips4000, "mips:4000", false, NN(I_mips4000)),
  107. N (32, 32, bfd_mach_mips4010, "mips:4010", false, NN(I_mips4010)),
  108. N (64, 64, bfd_mach_mips4100, "mips:4100", false, NN(I_mips4100)),
  109. N (64, 64, bfd_mach_mips4111, "mips:4111", false, NN(I_mips4111)),
  110. N (64, 64, bfd_mach_mips4120, "mips:4120", false, NN(I_mips4120)),
  111. N (64, 64, bfd_mach_mips4300, "mips:4300", false, NN(I_mips4300)),
  112. N (64, 64, bfd_mach_mips4400, "mips:4400", false, NN(I_mips4400)),
  113. N (64, 64, bfd_mach_mips4600, "mips:4600", false, NN(I_mips4600)),
  114. N (64, 64, bfd_mach_mips4650, "mips:4650", false, NN(I_mips4650)),
  115. N (64, 64, bfd_mach_mips5000, "mips:5000", false, NN(I_mips5000)),
  116. N (64, 64, bfd_mach_mips5400, "mips:5400", false, NN(I_mips5400)),
  117. N (64, 64, bfd_mach_mips5500, "mips:5500", false, NN(I_mips5500)),
  118. N (64, 32, bfd_mach_mips5900, "mips:5900", false, NN(I_mips5900)),
  119. N (32, 32, bfd_mach_mips6000, "mips:6000", false, NN(I_mips6000)),
  120. N (64, 64, bfd_mach_mips7000, "mips:7000", false, NN(I_mips7000)),
  121. N (64, 64, bfd_mach_mips8000, "mips:8000", false, NN(I_mips8000)),
  122. N (64, 64, bfd_mach_mips9000, "mips:9000", false, NN(I_mips9000)),
  123. N (64, 64, bfd_mach_mips10000,"mips:10000", false, NN(I_mips10000)),
  124. N (64, 64, bfd_mach_mips12000,"mips:12000", false, NN(I_mips12000)),
  125. N (64, 64, bfd_mach_mips14000,"mips:14000", false, NN(I_mips14000)),
  126. N (64, 64, bfd_mach_mips16000,"mips:16000", false, NN(I_mips16000)),
  127. N (64, 64, bfd_mach_mips16, "mips:16", false, NN(I_mips16)),
  128. N (64, 64, bfd_mach_mips5, "mips:mips5", false, NN(I_mips5)),
  129. N (32, 32, bfd_mach_mipsisa32, "mips:isa32", false, NN(I_mipsisa32)),
  130. N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", false, NN(I_mipsisa32r2)),
  131. N (32, 32, bfd_mach_mipsisa32r3,"mips:isa32r3", false, NN(I_mipsisa32r3)),
  132. N (32, 32, bfd_mach_mipsisa32r5,"mips:isa32r5", false, NN(I_mipsisa32r5)),
  133. N (32, 32, bfd_mach_mipsisa32r6,"mips:isa32r6", false, NN(I_mipsisa32r6)),
  134. N (64, 64, bfd_mach_mipsisa64, "mips:isa64", false, NN(I_mipsisa64)),
  135. N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", false, NN(I_mipsisa64r2)),
  136. N (64, 64, bfd_mach_mipsisa64r3,"mips:isa64r3", false, NN(I_mipsisa64r3)),
  137. N (64, 64, bfd_mach_mipsisa64r5,"mips:isa64r5", false, NN(I_mipsisa64r5)),
  138. N (64, 64, bfd_mach_mipsisa64r6,"mips:isa64r6", false, NN(I_mipsisa64r6)),
  139. N (64, 64, bfd_mach_mips_sb1, "mips:sb1", false, NN(I_sb1)),
  140. N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", false, NN(I_loongson_2e)),
  141. N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", false, NN(I_loongson_2f)),
  142. N (64, 64, bfd_mach_mips_gs464, "mips:gs464", false, NN(I_gs464)),
  143. N (64, 64, bfd_mach_mips_gs464e, "mips:gs464e", false, NN(I_gs464e)),
  144. N (64, 64, bfd_mach_mips_gs264e, "mips:gs264e", false, NN(I_gs264e)),
  145. N (64, 64, bfd_mach_mips_octeon,"mips:octeon", false, NN(I_mipsocteon)),
  146. N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", false, NN(I_mipsocteonp)),
  147. N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", false, NN(I_mipsocteon2)),
  148. N (64, 64, bfd_mach_mips_octeon3, "mips:octeon3", false, NN(I_mipsocteon3)),
  149. N (64, 64, bfd_mach_mips_xlr, "mips:xlr", false, NN(I_xlr)),
  150. N (32, 32, bfd_mach_mips_interaptiv_mr2, "mips:interaptiv-mr2", false,
  151. NN(I_interaptiv_mr2)),
  152. N (64, 64, bfd_mach_mips_micromips, "mips:micromips", false, NULL)
  153. };
  154. /* The default architecture is mips:3000, but with a machine number of
  155. zero. This lets the linker distinguish between a default setting
  156. of mips, and an explicit setting of mips:3000. */
  157. const bfd_arch_info_type bfd_mips_arch =
  158. N (32, 32, 0, "mips", true, &arch_info_struct[0]);