12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559756075617562756375647565756675677568756975707571757275737574757575767577757875797580758175827583758475857586758775887589759075917592759375947595759675977598759976007601760276037604760576067607760876097610761176127613761476157616761776187619762076217622762376247625762676277628762976307631763276337634763576367637763876397640764176427643764476457646764776487649765076517652765376547655765676577658765976607661766276637664766576667667766876697670767176727673767476757676767776787679768076817682768376847685768676877688768976907691769276937694769576967697769876997700770177027703770477057706770777087709771077117712771377147715771677177718771977207721772277237724772577267727772877297730773177327733773477357736773777387739774077417742774377447745774677477748774977507751775277537754775577567757775877597760776177627763776477657766776777687769777077717772777377747775777677777778777977807781778277837784778577867787778877897790779177927793779477957796779777987799780078017802780378047805780678077808780978107811781278137814781578167817781878197820782178227823782478257826782778287829783078317832783378347835783678377838783978407841784278437844784578467847784878497850785178527853785478557856785778587859786078617862786378647865786678677868786978707871787278737874787578767877787878797880788178827883788478857886788778887889789078917892789378947895789678977898789979007901790279037904790579067907790879097910791179127913791479157916791779187919792079217922792379247925792679277928792979307931793279337934793579367937793879397940794179427943794479457946794779487949795079517952795379547955795679577958795979607961796279637964796579667967796879697970797179727973797479757976797779787979798079817982798379847985798679877988798979907991799279937994799579967997799879998000800180028003800480058006800780088009801080118012801380148015801680178018801980208021802280238024802580268027802880298030803180328033803480358036803780388039804080418042804380448045804680478048804980508051805280538054805580568057805880598060806180628063806480658066806780688069807080718072807380748075807680778078807980808081808280838084808580868087808880898090809180928093809480958096809780988099810081018102810381048105810681078108810981108111811281138114811581168117811881198120812181228123812481258126812781288129813081318132813381348135813681378138813981408141814281438144814581468147814881498150815181528153815481558156815781588159816081618162816381648165816681678168816981708171817281738174817581768177817881798180818181828183818481858186818781888189819081918192819381948195819681978198819982008201820282038204820582068207820882098210821182128213821482158216821782188219822082218222822382248225822682278228822982308231823282338234823582368237823882398240824182428243824482458246824782488249825082518252825382548255825682578258825982608261826282638264826582668267826882698270827182728273827482758276827782788279828082818282828382848285828682878288828982908291829282938294829582968297829882998300830183028303830483058306830783088309831083118312831383148315831683178318831983208321832283238324832583268327832883298330833183328333833483358336833783388339834083418342834383448345834683478348834983508351835283538354835583568357835883598360836183628363836483658366836783688369837083718372837383748375837683778378837983808381838283838384838583868387838883898390839183928393839483958396839783988399840084018402840384048405840684078408840984108411841284138414841584168417841884198420842184228423842484258426842784288429843084318432843384348435843684378438843984408441844284438444844584468447844884498450845184528453845484558456845784588459846084618462846384648465846684678468846984708471847284738474847584768477847884798480848184828483848484858486848784888489849084918492849384948495849684978498849985008501850285038504850585068507850885098510851185128513851485158516851785188519852085218522852385248525852685278528852985308531853285338534853585368537853885398540854185428543854485458546854785488549855085518552855385548555855685578558855985608561856285638564856585668567856885698570857185728573857485758576857785788579858085818582858385848585858685878588858985908591859285938594859585968597859885998600860186028603860486058606860786088609861086118612861386148615861686178618861986208621862286238624862586268627862886298630863186328633863486358636863786388639864086418642864386448645864686478648864986508651865286538654865586568657865886598660866186628663866486658666866786688669867086718672867386748675867686778678867986808681868286838684868586868687868886898690869186928693869486958696869786988699870087018702870387048705870687078708870987108711871287138714871587168717871887198720872187228723872487258726872787288729873087318732873387348735873687378738873987408741874287438744874587468747874887498750875187528753875487558756875787588759876087618762876387648765876687678768876987708771877287738774877587768777877887798780878187828783878487858786878787888789879087918792879387948795879687978798879988008801880288038804880588068807880888098810881188128813881488158816881788188819882088218822882388248825882688278828882988308831883288338834883588368837883888398840884188428843884488458846884788488849885088518852885388548855885688578858885988608861886288638864886588668867886888698870887188728873887488758876887788788879888088818882888388848885888688878888888988908891889288938894889588968897889888998900890189028903890489058906890789088909891089118912891389148915891689178918891989208921892289238924892589268927892889298930893189328933893489358936893789388939894089418942894389448945894689478948894989508951895289538954895589568957895889598960896189628963896489658966896789688969897089718972897389748975897689778978897989808981898289838984898589868987898889898990899189928993899489958996899789988999900090019002900390049005900690079008900990109011901290139014901590169017901890199020902190229023902490259026902790289029903090319032903390349035903690379038903990409041904290439044904590469047904890499050905190529053905490559056905790589059906090619062906390649065906690679068906990709071907290739074907590769077907890799080908190829083908490859086908790889089909090919092909390949095909690979098909991009101910291039104910591069107910891099110911191129113911491159116911791189119912091219122912391249125912691279128912991309131913291339134913591369137913891399140914191429143914491459146914791489149915091519152915391549155915691579158915991609161916291639164916591669167916891699170917191729173917491759176917791789179918091819182918391849185918691879188918991909191919291939194919591969197919891999200920192029203920492059206920792089209921092119212921392149215921692179218921992209221922292239224922592269227922892299230923192329233923492359236923792389239924092419242924392449245924692479248924992509251925292539254925592569257925892599260926192629263926492659266926792689269927092719272927392749275927692779278927992809281928292839284928592869287928892899290929192929293929492959296929792989299930093019302930393049305930693079308930993109311931293139314931593169317931893199320932193229323932493259326932793289329933093319332933393349335933693379338933993409341934293439344934593469347934893499350935193529353935493559356935793589359936093619362936393649365936693679368936993709371937293739374937593769377937893799380938193829383938493859386938793889389939093919392939393949395939693979398939994009401940294039404940594069407940894099410941194129413941494159416941794189419942094219422942394249425942694279428942994309431943294339434943594369437943894399440944194429443944494459446944794489449945094519452945394549455945694579458945994609461946294639464946594669467946894699470947194729473947494759476947794789479948094819482948394849485948694879488948994909491949294939494949594969497949894999500950195029503950495059506950795089509951095119512951395149515951695179518951995209521952295239524952595269527952895299530953195329533953495359536953795389539954095419542954395449545954695479548954995509551955295539554955595569557955895599560956195629563956495659566956795689569957095719572957395749575957695779578957995809581958295839584958595869587958895899590959195929593959495959596959795989599960096019602960396049605960696079608960996109611961296139614961596169617961896199620962196229623962496259626962796289629963096319632963396349635963696379638963996409641964296439644964596469647964896499650965196529653965496559656965796589659966096619662966396649665966696679668966996709671967296739674967596769677967896799680968196829683968496859686968796889689969096919692969396949695969696979698969997009701970297039704970597069707970897099710971197129713971497159716971797189719972097219722972397249725972697279728972997309731973297339734973597369737973897399740974197429743974497459746974797489749975097519752975397549755975697579758975997609761976297639764976597669767976897699770977197729773977497759776977797789779978097819782978397849785978697879788978997909791979297939794979597969797979897999800980198029803980498059806980798089809981098119812981398149815981698179818981998209821982298239824982598269827982898299830983198329833983498359836983798389839984098419842984398449845984698479848984998509851985298539854985598569857985898599860986198629863986498659866986798689869987098719872987398749875987698779878987998809881988298839884988598869887988898899890989198929893989498959896989798989899990099019902990399049905990699079908990999109911991299139914991599169917991899199920992199229923992499259926992799289929993099319932993399349935993699379938993999409941994299439944994599469947994899499950995199529953995499559956995799589959996099619962996399649965996699679968996999709971997299739974997599769977997899799980998199829983998499859986998799889989999099919992999399949995999699979998999910000100011000210003100041000510006100071000810009100101001110012100131001410015100161001710018100191002010021100221002310024100251002610027100281002910030100311003210033100341003510036100371003810039100401004110042100431004410045100461004710048100491005010051100521005310054100551005610057100581005910060100611006210063100641006510066100671006810069100701007110072100731007410075100761007710078100791008010081100821008310084100851008610087100881008910090100911009210093100941009510096100971009810099101001010110102101031010410105101061010710108101091011010111101121011310114101151011610117101181011910120101211012210123101241012510126101271012810129101301013110132101331013410135101361013710138101391014010141101421014310144101451014610147101481014910150101511015210153101541015510156101571015810159101601016110162101631016410165101661016710168101691017010171101721017310174101751017610177101781017910180101811018210183101841018510186101871018810189101901019110192101931019410195101961019710198101991020010201102021020310204102051020610207102081020910210102111021210213102141021510216102171021810219102201022110222102231022410225102261022710228102291023010231102321023310234102351023610237102381023910240102411024210243102441024510246102471024810249102501025110252102531025410255102561025710258102591026010261102621026310264102651026610267102681026910270102711027210273102741027510276102771027810279102801028110282102831028410285102861028710288102891029010291102921029310294102951029610297102981029910300103011030210303103041030510306103071030810309103101031110312103131031410315103161031710318103191032010321103221032310324103251032610327103281032910330103311033210333103341033510336103371033810339103401034110342103431034410345103461034710348103491035010351103521035310354103551035610357103581035910360103611036210363103641036510366103671036810369103701037110372103731037410375103761037710378103791038010381103821038310384103851038610387103881038910390103911039210393103941039510396103971039810399104001040110402104031040410405104061040710408104091041010411104121041310414104151041610417104181041910420104211042210423104241042510426104271042810429104301043110432104331043410435104361043710438104391044010441104421044310444104451044610447104481044910450104511045210453104541045510456104571045810459104601046110462104631046410465104661046710468104691047010471104721047310474104751047610477104781047910480104811048210483104841048510486104871048810489104901049110492104931049410495104961049710498104991050010501105021050310504105051050610507105081050910510105111051210513105141051510516105171051810519105201052110522105231052410525105261052710528105291053010531105321053310534105351053610537105381053910540105411054210543105441054510546105471054810549105501055110552105531055410555105561055710558105591056010561105621056310564105651056610567105681056910570105711057210573105741057510576105771057810579105801058110582105831058410585105861058710588105891059010591105921059310594105951059610597105981059910600106011060210603106041060510606106071060810609106101061110612106131061410615106161061710618106191062010621106221062310624106251062610627106281062910630106311063210633106341063510636106371063810639106401064110642106431064410645106461064710648106491065010651106521065310654106551065610657106581065910660106611066210663106641066510666106671066810669106701067110672106731067410675106761067710678106791068010681106821068310684106851068610687106881068910690106911069210693106941069510696106971069810699107001070110702107031070410705107061070710708107091071010711107121071310714107151071610717107181071910720107211072210723107241072510726107271072810729107301073110732107331073410735107361073710738107391074010741107421074310744107451074610747107481074910750107511075210753107541075510756107571075810759107601076110762107631076410765107661076710768107691077010771107721077310774107751077610777107781077910780107811078210783107841078510786107871078810789107901079110792107931079410795107961079710798107991080010801108021080310804108051080610807108081080910810108111081210813108141081510816108171081810819108201082110822108231082410825108261082710828108291083010831108321083310834108351083610837108381083910840108411084210843108441084510846108471084810849108501085110852108531085410855108561085710858108591086010861108621086310864108651086610867108681086910870108711087210873108741087510876108771087810879108801088110882108831088410885108861088710888108891089010891108921089310894108951089610897108981089910900109011090210903109041090510906109071090810909109101091110912109131091410915109161091710918109191092010921109221092310924109251092610927109281092910930109311093210933109341093510936109371093810939109401094110942109431094410945109461094710948109491095010951109521095310954109551095610957109581095910960109611096210963109641096510966109671096810969109701097110972109731097410975109761097710978109791098010981109821098310984109851098610987109881098910990109911099210993109941099510996109971099810999110001100111002110031100411005110061100711008110091101011011110121101311014110151101611017110181101911020110211102211023110241102511026110271102811029110301103111032110331103411035110361103711038110391104011041110421104311044110451104611047110481104911050110511105211053110541105511056110571105811059110601106111062110631106411065110661106711068110691107011071110721107311074110751107611077110781107911080110811108211083110841108511086110871108811089110901109111092110931109411095110961109711098110991110011101111021110311104111051110611107111081110911110111111111211113111141111511116111171111811119111201112111122111231112411125111261112711128111291113011131111321113311134111351113611137111381113911140111411114211143111441114511146111471114811149111501115111152111531115411155111561115711158111591116011161111621116311164111651116611167111681116911170111711117211173111741117511176111771117811179111801118111182111831118411185111861118711188111891119011191111921119311194111951119611197111981119911200112011120211203112041120511206112071120811209112101121111212112131121411215112161121711218112191122011221112221122311224112251122611227112281122911230112311123211233112341123511236112371123811239112401124111242112431124411245112461124711248112491125011251112521125311254112551125611257112581125911260112611126211263112641126511266112671126811269112701127111272112731127411275112761127711278112791128011281112821128311284112851128611287112881128911290112911129211293112941129511296112971129811299113001130111302113031130411305113061130711308113091131011311113121131311314113151131611317113181131911320113211132211323113241132511326113271132811329113301133111332113331133411335113361133711338113391134011341113421134311344113451134611347113481134911350113511135211353113541135511356113571135811359113601136111362113631136411365113661136711368113691137011371113721137311374113751137611377113781137911380113811138211383113841138511386113871138811389113901139111392113931139411395113961139711398113991140011401114021140311404114051140611407114081140911410114111141211413114141141511416114171141811419114201142111422114231142411425114261142711428114291143011431114321143311434114351143611437114381143911440114411144211443114441144511446114471144811449114501145111452114531145411455114561145711458114591146011461114621146311464114651146611467114681146911470114711147211473114741147511476114771147811479114801148111482114831148411485114861148711488114891149011491114921149311494114951149611497114981149911500115011150211503115041150511506115071150811509115101151111512115131151411515115161151711518115191152011521115221152311524115251152611527115281152911530115311153211533115341153511536115371153811539115401154111542115431154411545115461154711548115491155011551115521155311554115551155611557115581155911560115611156211563115641156511566115671156811569115701157111572115731157411575115761157711578115791158011581115821158311584115851158611587115881158911590115911159211593115941159511596115971159811599116001160111602116031160411605116061160711608116091161011611116121161311614116151161611617116181161911620116211162211623116241162511626116271162811629116301163111632116331163411635116361163711638116391164011641116421164311644116451164611647116481164911650116511165211653116541165511656116571165811659116601166111662116631166411665116661166711668116691167011671116721167311674116751167611677116781167911680116811168211683116841168511686116871168811689116901169111692116931169411695116961169711698116991170011701117021170311704117051170611707117081170911710117111171211713117141171511716117171171811719117201172111722117231172411725117261172711728117291173011731117321173311734117351173611737117381173911740117411174211743117441174511746117471174811749117501175111752117531175411755117561175711758117591176011761117621176311764117651176611767117681176911770117711177211773117741177511776117771177811779117801178111782117831178411785117861178711788117891179011791117921179311794117951179611797117981179911800118011180211803118041180511806118071180811809118101181111812118131181411815118161181711818118191182011821118221182311824118251182611827118281182911830118311183211833118341183511836118371183811839118401184111842118431184411845118461184711848118491185011851118521185311854118551185611857118581185911860118611186211863118641186511866118671186811869118701187111872118731187411875118761187711878118791188011881118821188311884118851188611887118881188911890118911189211893118941189511896118971189811899119001190111902119031190411905119061190711908119091191011911119121191311914119151191611917119181191911920119211192211923119241192511926119271192811929119301193111932119331193411935119361193711938119391194011941119421194311944119451194611947119481194911950119511195211953119541195511956119571195811959119601196111962119631196411965119661196711968119691197011971119721197311974119751197611977119781197911980119811198211983119841198511986119871198811989119901199111992119931199411995119961199711998119991200012001120021200312004120051200612007120081200912010120111201212013120141201512016120171201812019120201202112022120231202412025120261202712028120291203012031120321203312034120351203612037120381203912040120411204212043120441204512046120471204812049120501205112052120531205412055120561205712058120591206012061120621206312064120651206612067120681206912070120711207212073120741207512076120771207812079120801208112082120831208412085120861208712088120891209012091120921209312094120951209612097120981209912100121011210212103121041210512106121071210812109121101211112112121131211412115121161211712118121191212012121121221212312124121251212612127121281212912130121311213212133121341213512136121371213812139121401214112142121431214412145121461214712148121491215012151121521215312154121551215612157121581215912160121611216212163121641216512166121671216812169121701217112172121731217412175121761217712178121791218012181121821218312184121851218612187121881218912190121911219212193121941219512196121971219812199122001220112202122031220412205122061220712208122091221012211122121221312214122151221612217122181221912220122211222212223122241222512226122271222812229122301223112232122331223412235122361223712238122391224012241122421224312244122451224612247122481224912250122511225212253122541225512256122571225812259122601226112262122631226412265122661226712268122691227012271122721227312274122751227612277122781227912280122811228212283122841228512286122871228812289122901229112292122931229412295122961229712298122991230012301123021230312304123051230612307123081230912310123111231212313123141231512316123171231812319123201232112322123231232412325123261232712328123291233012331123321233312334123351233612337123381233912340123411234212343123441234512346123471234812349123501235112352123531235412355123561235712358123591236012361123621236312364123651236612367123681236912370123711237212373123741237512376123771237812379123801238112382123831238412385123861238712388123891239012391123921239312394123951239612397123981239912400124011240212403124041240512406124071240812409124101241112412124131241412415124161241712418124191242012421124221242312424124251242612427124281242912430124311243212433124341243512436124371243812439124401244112442124431244412445124461244712448124491245012451124521245312454124551245612457124581245912460124611246212463124641246512466124671246812469124701247112472124731247412475124761247712478124791248012481124821248312484124851248612487124881248912490124911249212493124941249512496124971249812499125001250112502125031250412505125061250712508125091251012511125121251312514125151251612517125181251912520125211252212523125241252512526125271252812529125301253112532125331253412535125361253712538125391254012541125421254312544125451254612547125481254912550125511255212553125541255512556125571255812559125601256112562125631256412565125661256712568125691257012571125721257312574125751257612577125781257912580125811258212583125841258512586125871258812589125901259112592125931259412595125961259712598125991260012601126021260312604126051260612607126081260912610126111261212613126141261512616126171261812619126201262112622126231262412625126261262712628126291263012631126321263312634126351263612637126381263912640126411264212643126441264512646126471264812649126501265112652126531265412655126561265712658126591266012661126621266312664126651266612667126681266912670126711267212673126741267512676126771267812679126801268112682126831268412685126861268712688126891269012691126921269312694126951269612697126981269912700127011270212703127041270512706127071270812709127101271112712127131271412715127161271712718127191272012721127221272312724127251272612727127281272912730127311273212733127341273512736127371273812739127401274112742127431274412745127461274712748127491275012751127521275312754127551275612757127581275912760127611276212763127641276512766127671276812769127701277112772127731277412775127761277712778127791278012781127821278312784127851278612787127881278912790127911279212793127941279512796127971279812799128001280112802128031280412805128061280712808128091281012811128121281312814128151281612817128181281912820128211282212823128241282512826128271282812829128301283112832128331283412835128361283712838128391284012841128421284312844128451284612847128481284912850128511285212853128541285512856128571285812859128601286112862128631286412865128661286712868128691287012871128721287312874128751287612877128781287912880128811288212883128841288512886128871288812889128901289112892128931289412895128961289712898128991290012901129021290312904129051290612907129081290912910129111291212913129141291512916129171291812919129201292112922129231292412925129261292712928129291293012931129321293312934129351293612937129381293912940129411294212943129441294512946129471294812949129501295112952129531295412955129561295712958129591296012961129621296312964129651296612967129681296912970129711297212973129741297512976129771297812979129801298112982129831298412985129861298712988129891299012991129921299312994129951299612997129981299913000130011300213003130041300513006130071300813009130101301113012130131301413015130161301713018130191302013021130221302313024130251302613027130281302913030130311303213033130341303513036130371303813039130401304113042130431304413045130461304713048130491305013051130521305313054130551305613057130581305913060130611306213063130641306513066130671306813069130701307113072130731307413075130761307713078130791308013081130821308313084130851308613087130881308913090130911309213093130941309513096130971309813099131001310113102131031310413105131061310713108131091311013111131121311313114131151311613117131181311913120131211312213123131241312513126131271312813129131301313113132131331313413135131361313713138131391314013141131421314313144131451314613147131481314913150131511315213153131541315513156131571315813159131601316113162131631316413165131661316713168131691317013171131721317313174131751317613177131781317913180131811318213183131841318513186131871318813189131901319113192131931319413195131961319713198131991320013201132021320313204132051320613207132081320913210132111321213213132141321513216132171321813219132201322113222132231322413225132261322713228132291323013231132321323313234132351323613237132381323913240132411324213243132441324513246132471324813249132501325113252132531325413255132561325713258132591326013261132621326313264132651326613267132681326913270132711327213273132741327513276132771327813279132801328113282132831328413285132861328713288132891329013291132921329313294132951329613297132981329913300133011330213303133041330513306133071330813309133101331113312133131331413315133161331713318133191332013321133221332313324133251332613327133281332913330133311333213333133341333513336133371333813339133401334113342133431334413345133461334713348133491335013351133521335313354133551335613357133581335913360133611336213363133641336513366133671336813369133701337113372133731337413375133761337713378133791338013381133821338313384133851338613387133881338913390133911339213393133941339513396133971339813399134001340113402134031340413405134061340713408134091341013411134121341313414134151341613417134181341913420134211342213423134241342513426134271342813429134301343113432134331343413435134361343713438134391344013441134421344313444134451344613447134481344913450134511345213453134541345513456134571345813459134601346113462134631346413465134661346713468134691347013471134721347313474134751347613477134781347913480134811348213483134841348513486134871348813489134901349113492134931349413495134961349713498134991350013501135021350313504135051350613507135081350913510135111351213513135141351513516135171351813519135201352113522135231352413525135261352713528135291353013531135321353313534135351353613537135381353913540135411354213543135441354513546135471354813549135501355113552135531355413555135561355713558135591356013561135621356313564135651356613567135681356913570135711357213573135741357513576135771357813579135801358113582135831358413585135861358713588135891359013591135921359313594135951359613597135981359913600136011360213603136041360513606136071360813609136101361113612136131361413615136161361713618136191362013621136221362313624136251362613627136281362913630136311363213633136341363513636136371363813639136401364113642136431364413645136461364713648136491365013651136521365313654136551365613657136581365913660136611366213663136641366513666136671366813669136701367113672136731367413675136761367713678136791368013681136821368313684136851368613687136881368913690136911369213693136941369513696136971369813699137001370113702137031370413705137061370713708137091371013711137121371313714137151371613717137181371913720137211372213723137241372513726137271372813729137301373113732137331373413735137361373713738137391374013741137421374313744137451374613747137481374913750137511375213753137541375513756137571375813759137601376113762137631376413765137661376713768137691377013771137721377313774137751377613777137781377913780137811378213783137841378513786137871378813789137901379113792137931379413795137961379713798137991380013801138021380313804138051380613807138081380913810138111381213813138141381513816138171381813819138201382113822138231382413825138261382713828138291383013831138321383313834138351383613837138381383913840138411384213843138441384513846138471384813849138501385113852138531385413855138561385713858138591386013861138621386313864138651386613867138681386913870138711387213873138741387513876138771387813879138801388113882138831388413885138861388713888138891389013891138921389313894138951389613897138981389913900139011390213903139041390513906139071390813909139101391113912139131391413915139161391713918139191392013921139221392313924139251392613927139281392913930139311393213933139341393513936139371393813939139401394113942139431394413945139461394713948139491395013951139521395313954139551395613957139581395913960139611396213963139641396513966139671396813969139701397113972139731397413975139761397713978139791398013981139821398313984139851398613987139881398913990139911399213993139941399513996139971399813999140001400114002140031400414005140061400714008140091401014011140121401314014140151401614017140181401914020140211402214023140241402514026140271402814029140301403114032140331403414035140361403714038140391404014041140421404314044140451404614047140481404914050140511405214053140541405514056140571405814059140601406114062140631406414065140661406714068140691407014071140721407314074140751407614077140781407914080140811408214083140841408514086140871408814089140901409114092140931409414095140961409714098140991410014101141021410314104141051410614107141081410914110141111411214113141141411514116141171411814119141201412114122141231412414125141261412714128141291413014131141321413314134141351413614137141381413914140141411414214143141441414514146141471414814149141501415114152141531415414155141561415714158141591416014161141621416314164141651416614167141681416914170141711417214173141741417514176141771417814179141801418114182141831418414185141861418714188141891419014191141921419314194141951419614197141981419914200142011420214203142041420514206142071420814209142101421114212142131421414215142161421714218142191422014221142221422314224142251422614227142281422914230142311423214233142341423514236142371423814239142401424114242142431424414245142461424714248142491425014251142521425314254142551425614257142581425914260142611426214263142641426514266142671426814269142701427114272142731427414275142761427714278142791428014281142821428314284142851428614287142881428914290142911429214293142941429514296142971429814299143001430114302143031430414305143061430714308143091431014311143121431314314143151431614317143181431914320143211432214323143241432514326143271432814329143301433114332143331433414335143361433714338143391434014341143421434314344143451434614347143481434914350143511435214353143541435514356143571435814359143601436114362143631436414365143661436714368143691437014371143721437314374143751437614377143781437914380143811438214383143841438514386143871438814389143901439114392143931439414395143961439714398143991440014401144021440314404144051440614407144081440914410144111441214413144141441514416144171441814419144201442114422144231442414425144261442714428144291443014431144321443314434144351443614437144381443914440144411444214443144441444514446144471444814449144501445114452144531445414455144561445714458144591446014461144621446314464144651446614467144681446914470144711447214473144741447514476144771447814479144801448114482144831448414485144861448714488144891449014491144921449314494144951449614497144981449914500145011450214503145041450514506145071450814509145101451114512145131451414515145161451714518145191452014521145221452314524145251452614527145281452914530145311453214533145341453514536145371453814539145401454114542145431454414545145461454714548145491455014551145521455314554145551455614557145581455914560145611456214563145641456514566145671456814569145701457114572145731457414575145761457714578145791458014581145821458314584145851458614587145881458914590145911459214593145941459514596145971459814599146001460114602146031460414605146061460714608146091461014611146121461314614146151461614617146181461914620146211462214623146241462514626146271462814629146301463114632146331463414635146361463714638146391464014641146421464314644146451464614647146481464914650146511465214653146541465514656146571465814659146601466114662146631466414665146661466714668146691467014671146721467314674146751467614677146781467914680146811468214683146841468514686146871468814689146901469114692146931469414695146961469714698146991470014701147021470314704147051470614707147081470914710147111471214713147141471514716147171471814719147201472114722147231472414725147261472714728147291473014731147321473314734147351473614737147381473914740147411474214743147441474514746147471474814749147501475114752147531475414755147561475714758147591476014761147621476314764147651476614767147681476914770147711477214773147741477514776147771477814779147801478114782147831478414785147861478714788147891479014791147921479314794147951479614797147981479914800148011480214803148041480514806148071480814809148101481114812148131481414815148161481714818148191482014821148221482314824148251482614827148281482914830148311483214833148341483514836148371483814839148401484114842148431484414845148461484714848148491485014851148521485314854148551485614857148581485914860148611486214863148641486514866148671486814869148701487114872148731487414875148761487714878148791488014881148821488314884148851488614887148881488914890148911489214893148941489514896148971489814899149001490114902149031490414905149061490714908149091491014911149121491314914149151491614917149181491914920149211492214923149241492514926149271492814929149301493114932149331493414935149361493714938149391494014941149421494314944149451494614947149481494914950149511495214953149541495514956149571495814959149601496114962149631496414965149661496714968149691497014971149721497314974149751497614977149781497914980149811498214983149841498514986149871498814989149901499114992149931499414995149961499714998149991500015001150021500315004150051500615007150081500915010150111501215013150141501515016150171501815019150201502115022150231502415025150261502715028150291503015031150321503315034150351503615037150381503915040150411504215043150441504515046150471504815049150501505115052150531505415055150561505715058150591506015061150621506315064150651506615067150681506915070150711507215073150741507515076150771507815079150801508115082150831508415085150861508715088150891509015091150921509315094150951509615097150981509915100151011510215103151041510515106151071510815109151101511115112151131511415115151161511715118151191512015121151221512315124151251512615127151281512915130151311513215133151341513515136151371513815139151401514115142151431514415145151461514715148151491515015151151521515315154151551515615157151581515915160151611516215163151641516515166151671516815169151701517115172151731517415175151761517715178151791518015181151821518315184151851518615187151881518915190151911519215193151941519515196151971519815199152001520115202152031520415205152061520715208152091521015211152121521315214152151521615217152181521915220152211522215223152241522515226152271522815229152301523115232152331523415235152361523715238152391524015241152421524315244152451524615247152481524915250152511525215253152541525515256152571525815259152601526115262152631526415265152661526715268152691527015271152721527315274152751527615277152781527915280152811528215283152841528515286152871528815289152901529115292152931529415295152961529715298152991530015301153021530315304153051530615307153081530915310153111531215313153141531515316153171531815319153201532115322153231532415325153261532715328153291533015331153321533315334153351533615337153381533915340153411534215343153441534515346153471534815349153501535115352153531535415355153561535715358153591536015361153621536315364153651536615367153681536915370153711537215373153741537515376153771537815379153801538115382153831538415385153861538715388153891539015391153921539315394153951539615397153981539915400154011540215403154041540515406154071540815409154101541115412154131541415415154161541715418154191542015421154221542315424154251542615427154281542915430154311543215433154341543515436154371543815439154401544115442154431544415445154461544715448154491545015451154521545315454154551545615457154581545915460154611546215463154641546515466154671546815469154701547115472154731547415475154761547715478154791548015481154821548315484154851548615487154881548915490154911549215493154941549515496154971549815499155001550115502155031550415505155061550715508155091551015511155121551315514155151551615517155181551915520155211552215523155241552515526155271552815529155301553115532155331553415535155361553715538155391554015541155421554315544155451554615547155481554915550155511555215553155541555515556155571555815559155601556115562155631556415565155661556715568155691557015571155721557315574155751557615577155781557915580155811558215583155841558515586155871558815589155901559115592155931559415595155961559715598155991560015601156021560315604156051560615607156081560915610156111561215613156141561515616156171561815619156201562115622156231562415625156261562715628156291563015631156321563315634156351563615637156381563915640156411564215643156441564515646156471564815649156501565115652156531565415655156561565715658156591566015661156621566315664156651566615667156681566915670156711567215673156741567515676156771567815679156801568115682156831568415685156861568715688156891569015691156921569315694156951569615697156981569915700157011570215703157041570515706157071570815709157101571115712157131571415715157161571715718157191572015721157221572315724157251572615727157281572915730157311573215733157341573515736157371573815739157401574115742157431574415745157461574715748157491575015751157521575315754157551575615757157581575915760157611576215763157641576515766157671576815769157701577115772157731577415775157761577715778157791578015781157821578315784157851578615787157881578915790157911579215793157941579515796157971579815799158001580115802158031580415805158061580715808158091581015811158121581315814158151581615817158181581915820158211582215823158241582515826158271582815829158301583115832158331583415835158361583715838158391584015841158421584315844158451584615847158481584915850158511585215853158541585515856158571585815859158601586115862158631586415865158661586715868158691587015871158721587315874158751587615877158781587915880158811588215883158841588515886158871588815889158901589115892158931589415895158961589715898158991590015901159021590315904159051590615907159081590915910159111591215913159141591515916159171591815919159201592115922159231592415925159261592715928159291593015931159321593315934159351593615937159381593915940159411594215943159441594515946159471594815949159501595115952159531595415955159561595715958159591596015961159621596315964159651596615967159681596915970159711597215973159741597515976159771597815979159801598115982159831598415985159861598715988159891599015991159921599315994159951599615997159981599916000160011600216003160041600516006160071600816009160101601116012160131601416015160161601716018160191602016021160221602316024160251602616027160281602916030160311603216033160341603516036160371603816039160401604116042160431604416045160461604716048160491605016051160521605316054160551605616057160581605916060160611606216063160641606516066160671606816069160701607116072160731607416075160761607716078160791608016081160821608316084160851608616087160881608916090160911609216093160941609516096160971609816099161001610116102161031610416105161061610716108161091611016111161121611316114161151611616117161181611916120161211612216123161241612516126161271612816129161301613116132161331613416135161361613716138161391614016141161421614316144161451614616147161481614916150161511615216153161541615516156161571615816159161601616116162161631616416165161661616716168161691617016171161721617316174161751617616177161781617916180161811618216183161841618516186161871618816189161901619116192161931619416195161961619716198161991620016201162021620316204162051620616207162081620916210162111621216213162141621516216162171621816219162201622116222162231622416225162261622716228162291623016231162321623316234162351623616237162381623916240162411624216243162441624516246162471624816249162501625116252162531625416255162561625716258162591626016261162621626316264162651626616267162681626916270162711627216273162741627516276162771627816279162801628116282162831628416285162861628716288162891629016291162921629316294162951629616297162981629916300163011630216303163041630516306163071630816309163101631116312163131631416315163161631716318163191632016321163221632316324163251632616327163281632916330163311633216333163341633516336163371633816339163401634116342163431634416345163461634716348163491635016351163521635316354163551635616357163581635916360163611636216363163641636516366163671636816369163701637116372163731637416375163761637716378163791638016381163821638316384163851638616387163881638916390163911639216393163941639516396163971639816399164001640116402164031640416405164061640716408164091641016411164121641316414164151641616417164181641916420164211642216423164241642516426164271642816429164301643116432164331643416435164361643716438164391644016441164421644316444164451644616447164481644916450164511645216453164541645516456164571645816459164601646116462164631646416465164661646716468164691647016471164721647316474164751647616477164781647916480164811648216483164841648516486164871648816489164901649116492164931649416495164961649716498164991650016501165021650316504165051650616507165081650916510165111651216513165141651516516165171651816519165201652116522165231652416525165261652716528165291653016531165321653316534165351653616537165381653916540165411654216543165441654516546165471654816549165501655116552165531655416555165561655716558165591656016561165621656316564165651656616567165681656916570165711657216573165741657516576165771657816579165801658116582165831658416585165861658716588165891659016591165921659316594165951659616597165981659916600166011660216603166041660516606166071660816609166101661116612166131661416615166161661716618166191662016621166221662316624166251662616627166281662916630166311663216633166341663516636166371663816639166401664116642166431664416645166461664716648166491665016651166521665316654166551665616657166581665916660166611666216663166641666516666166671666816669166701667116672166731667416675166761667716678166791668016681166821668316684166851668616687166881668916690166911669216693166941669516696166971669816699167001670116702167031670416705167061670716708167091671016711167121671316714167151671616717167181671916720167211672216723167241672516726167271672816729167301673116732167331673416735167361673716738167391674016741167421674316744167451674616747167481674916750167511675216753167541675516756167571675816759167601676116762167631676416765167661676716768167691677016771167721677316774167751677616777167781677916780167811678216783167841678516786167871678816789167901679116792167931679416795167961679716798167991680016801168021680316804168051680616807168081680916810168111681216813168141681516816168171681816819168201682116822168231682416825168261682716828168291683016831168321683316834168351683616837168381683916840168411684216843168441684516846168471684816849168501685116852168531685416855168561685716858168591686016861168621686316864168651686616867168681686916870168711687216873168741687516876168771687816879168801688116882168831688416885168861688716888168891689016891168921689316894168951689616897168981689916900169011690216903169041690516906169071690816909169101691116912169131691416915169161691716918169191692016921169221692316924169251692616927169281692916930169311693216933169341693516936169371693816939169401694116942169431694416945169461694716948169491695016951169521695316954169551695616957169581695916960169611696216963169641696516966169671696816969169701697116972169731697416975169761697716978169791698016981169821698316984169851698616987169881698916990169911699216993169941699516996169971699816999170001700117002170031700417005170061700717008170091701017011170121701317014170151701617017170181701917020170211702217023170241702517026170271702817029170301703117032170331703417035170361703717038170391704017041170421704317044170451704617047170481704917050170511705217053170541705517056170571705817059170601706117062170631706417065170661706717068170691707017071170721707317074170751707617077170781707917080170811708217083170841708517086170871708817089170901709117092170931709417095170961709717098170991710017101171021710317104171051710617107171081710917110171111711217113171141711517116171171711817119171201712117122171231712417125171261712717128171291713017131171321713317134171351713617137171381713917140171411714217143171441714517146171471714817149171501715117152171531715417155171561715717158171591716017161171621716317164171651716617167171681716917170171711717217173171741717517176171771717817179171801718117182171831718417185171861718717188171891719017191171921719317194171951719617197171981719917200172011720217203172041720517206172071720817209172101721117212172131721417215172161721717218172191722017221172221722317224172251722617227172281722917230172311723217233172341723517236172371723817239172401724117242172431724417245172461724717248172491725017251172521725317254172551725617257172581725917260172611726217263172641726517266172671726817269172701727117272172731727417275172761727717278172791728017281172821728317284172851728617287172881728917290172911729217293172941729517296172971729817299173001730117302173031730417305173061730717308173091731017311173121731317314173151731617317173181731917320173211732217323173241732517326173271732817329173301733117332173331733417335173361733717338173391734017341173421734317344173451734617347173481734917350173511735217353173541735517356173571735817359173601736117362173631736417365173661736717368173691737017371173721737317374173751737617377173781737917380173811738217383173841738517386173871738817389173901739117392173931739417395173961739717398173991740017401174021740317404174051740617407174081740917410174111741217413174141741517416174171741817419174201742117422174231742417425174261742717428174291743017431174321743317434174351743617437174381743917440174411744217443174441744517446174471744817449174501745117452174531745417455174561745717458174591746017461174621746317464174651746617467174681746917470174711747217473174741747517476174771747817479174801748117482174831748417485174861748717488174891749017491174921749317494174951749617497174981749917500175011750217503175041750517506175071750817509175101751117512175131751417515175161751717518175191752017521175221752317524175251752617527175281752917530175311753217533175341753517536175371753817539175401754117542175431754417545175461754717548175491755017551175521755317554175551755617557175581755917560175611756217563175641756517566175671756817569175701757117572175731757417575175761757717578175791758017581175821758317584175851758617587175881758917590175911759217593175941759517596175971759817599176001760117602176031760417605176061760717608176091761017611176121761317614176151761617617176181761917620176211762217623176241762517626176271762817629176301763117632176331763417635176361763717638176391764017641176421764317644176451764617647176481764917650176511765217653176541765517656176571765817659176601766117662176631766417665176661766717668176691767017671176721767317674176751767617677176781767917680176811768217683176841768517686176871768817689176901769117692176931769417695176961769717698176991770017701177021770317704177051770617707177081770917710177111771217713177141771517716177171771817719177201772117722177231772417725177261772717728177291773017731177321773317734177351773617737177381773917740177411774217743177441774517746177471774817749177501775117752177531775417755177561775717758177591776017761177621776317764177651776617767177681776917770177711777217773177741777517776177771777817779177801778117782177831778417785177861778717788177891779017791177921779317794177951779617797177981779917800178011780217803178041780517806178071780817809178101781117812178131781417815178161781717818178191782017821178221782317824178251782617827178281782917830178311783217833178341783517836178371783817839178401784117842178431784417845178461784717848178491785017851178521785317854178551785617857178581785917860178611786217863178641786517866178671786817869178701787117872178731787417875178761787717878178791788017881178821788317884178851788617887178881788917890178911789217893178941789517896178971789817899179001790117902179031790417905179061790717908179091791017911179121791317914179151791617917179181791917920179211792217923179241792517926179271792817929179301793117932179331793417935179361793717938179391794017941179421794317944179451794617947179481794917950179511795217953179541795517956179571795817959179601796117962179631796417965179661796717968179691797017971179721797317974179751797617977179781797917980179811798217983179841798517986179871798817989179901799117992179931799417995179961799717998179991800018001180021800318004180051800618007180081800918010180111801218013180141801518016180171801818019180201802118022180231802418025180261802718028180291803018031180321803318034180351803618037180381803918040180411804218043180441804518046180471804818049180501805118052180531805418055180561805718058180591806018061180621806318064180651806618067180681806918070180711807218073180741807518076180771807818079180801808118082180831808418085180861808718088180891809018091180921809318094180951809618097180981809918100181011810218103181041810518106181071810818109181101811118112181131811418115181161811718118181191812018121181221812318124181251812618127181281812918130181311813218133181341813518136181371813818139181401814118142181431814418145181461814718148181491815018151181521815318154181551815618157181581815918160181611816218163181641816518166181671816818169181701817118172181731817418175181761817718178181791818018181181821818318184181851818618187181881818918190181911819218193181941819518196181971819818199182001820118202182031820418205182061820718208182091821018211182121821318214182151821618217182181821918220182211822218223182241822518226182271822818229182301823118232182331823418235182361823718238182391824018241182421824318244182451824618247182481824918250182511825218253182541825518256182571825818259182601826118262182631826418265182661826718268182691827018271182721827318274182751827618277182781827918280182811828218283182841828518286182871828818289182901829118292182931829418295182961829718298182991830018301183021830318304183051830618307183081830918310183111831218313183141831518316183171831818319183201832118322183231832418325183261832718328183291833018331183321833318334183351833618337183381833918340183411834218343183441834518346183471834818349183501835118352183531835418355183561835718358183591836018361183621836318364183651836618367183681836918370183711837218373183741837518376183771837818379183801838118382183831838418385183861838718388183891839018391183921839318394183951839618397183981839918400184011840218403184041840518406184071840818409184101841118412184131841418415184161841718418184191842018421184221842318424184251842618427184281842918430184311843218433184341843518436184371843818439184401844118442184431844418445184461844718448184491845018451184521845318454184551845618457184581845918460184611846218463184641846518466184671846818469184701847118472184731847418475184761847718478184791848018481184821848318484184851848618487184881848918490184911849218493184941849518496184971849818499185001850118502185031850418505185061850718508185091851018511185121851318514185151851618517185181851918520185211852218523185241852518526185271852818529185301853118532185331853418535185361853718538185391854018541185421854318544185451854618547185481854918550185511855218553185541855518556185571855818559185601856118562185631856418565185661856718568185691857018571185721857318574185751857618577185781857918580185811858218583185841858518586185871858818589185901859118592185931859418595185961859718598185991860018601186021860318604186051860618607186081860918610186111861218613186141861518616186171861818619186201862118622186231862418625186261862718628186291863018631186321863318634186351863618637186381863918640186411864218643186441864518646186471864818649186501865118652186531865418655186561865718658186591866018661186621866318664186651866618667186681866918670186711867218673186741867518676186771867818679186801868118682186831868418685186861868718688186891869018691186921869318694186951869618697186981869918700187011870218703187041870518706187071870818709187101871118712187131871418715187161871718718187191872018721187221872318724187251872618727187281872918730187311873218733187341873518736187371873818739187401874118742187431874418745187461874718748187491875018751187521875318754187551875618757187581875918760187611876218763187641876518766187671876818769187701877118772187731877418775187761877718778187791878018781187821878318784187851878618787187881878918790187911879218793187941879518796187971879818799188001880118802188031880418805188061880718808188091881018811188121881318814188151881618817188181881918820188211882218823188241882518826188271882818829188301883118832188331883418835188361883718838188391884018841188421884318844188451884618847188481884918850188511885218853188541885518856188571885818859188601886118862188631886418865188661886718868188691887018871188721887318874188751887618877188781887918880188811888218883188841888518886188871888818889188901889118892188931889418895188961889718898188991890018901189021890318904189051890618907189081890918910189111891218913189141891518916189171891818919189201892118922189231892418925189261892718928189291893018931189321893318934189351893618937189381893918940189411894218943189441894518946189471894818949189501895118952189531895418955189561895718958189591896018961189621896318964189651896618967189681896918970189711897218973189741897518976189771897818979189801898118982189831898418985189861898718988189891899018991189921899318994189951899618997189981899919000190011900219003190041900519006190071900819009190101901119012190131901419015190161901719018190191902019021190221902319024190251902619027190281902919030190311903219033190341903519036190371903819039190401904119042190431904419045190461904719048190491905019051190521905319054190551905619057190581905919060190611906219063190641906519066190671906819069190701907119072190731907419075190761907719078190791908019081190821908319084190851908619087190881908919090190911909219093190941909519096190971909819099191001910119102191031910419105191061910719108191091911019111191121911319114191151911619117191181911919120191211912219123191241912519126191271912819129191301913119132191331913419135191361913719138191391914019141191421914319144191451914619147191481914919150191511915219153191541915519156191571915819159191601916119162191631916419165191661916719168191691917019171191721917319174191751917619177191781917919180191811918219183191841918519186191871918819189191901919119192191931919419195191961919719198191991920019201192021920319204192051920619207192081920919210192111921219213192141921519216192171921819219192201922119222192231922419225192261922719228192291923019231192321923319234192351923619237192381923919240192411924219243192441924519246192471924819249192501925119252192531925419255192561925719258192591926019261192621926319264192651926619267192681926919270192711927219273192741927519276192771927819279192801928119282192831928419285192861928719288192891929019291192921929319294192951929619297192981929919300193011930219303193041930519306193071930819309193101931119312193131931419315193161931719318193191932019321193221932319324193251932619327193281932919330193311933219333193341933519336193371933819339193401934119342193431934419345193461934719348193491935019351193521935319354193551935619357193581935919360193611936219363193641936519366193671936819369193701937119372193731937419375193761937719378193791938019381193821938319384193851938619387193881938919390193911939219393193941939519396193971939819399194001940119402194031940419405194061940719408194091941019411194121941319414194151941619417194181941919420194211942219423194241942519426194271942819429194301943119432194331943419435194361943719438194391944019441194421944319444194451944619447194481944919450194511945219453194541945519456194571945819459194601946119462194631946419465194661946719468194691947019471194721947319474194751947619477194781947919480194811948219483194841948519486194871948819489194901949119492194931949419495194961949719498194991950019501195021950319504195051950619507195081950919510195111951219513195141951519516195171951819519195201952119522195231952419525195261952719528195291953019531195321953319534195351953619537195381953919540195411954219543195441954519546195471954819549195501955119552195531955419555195561955719558195591956019561195621956319564195651956619567195681956919570195711957219573195741957519576195771957819579195801958119582195831958419585195861958719588195891959019591195921959319594195951959619597195981959919600196011960219603196041960519606196071960819609196101961119612196131961419615196161961719618196191962019621196221962319624196251962619627196281962919630196311963219633196341963519636196371963819639196401964119642196431964419645196461964719648196491965019651196521965319654196551965619657196581965919660196611966219663196641966519666196671966819669196701967119672196731967419675196761967719678196791968019681196821968319684196851968619687196881968919690196911969219693196941969519696196971969819699197001970119702197031970419705197061970719708197091971019711197121971319714197151971619717197181971919720197211972219723197241972519726197271972819729197301973119732197331973419735197361973719738197391974019741197421974319744197451974619747197481974919750197511975219753197541975519756197571975819759197601976119762197631976419765197661976719768197691977019771197721977319774197751977619777197781977919780197811978219783197841978519786197871978819789197901979119792197931979419795197961979719798197991980019801198021980319804198051980619807198081980919810198111981219813198141981519816198171981819819198201982119822198231982419825198261982719828198291983019831198321983319834198351983619837198381983919840198411984219843198441984519846198471984819849198501985119852198531985419855198561985719858198591986019861198621986319864198651986619867198681986919870198711987219873198741987519876198771987819879198801988119882198831988419885198861988719888198891989019891198921989319894198951989619897198981989919900199011990219903199041990519906199071990819909199101991119912199131991419915199161991719918199191992019921199221992319924199251992619927199281992919930199311993219933199341993519936199371993819939199401994119942199431994419945199461994719948199491995019951199521995319954199551995619957199581995919960199611996219963199641996519966199671996819969199701997119972199731997419975199761997719978199791998019981199821998319984199851998619987199881998919990199911999219993199941999519996199971999819999200002000120002200032000420005200062000720008200092001020011200122001320014200152001620017200182001920020200212002220023200242002520026200272002820029200302003120032200332003420035200362003720038200392004020041200422004320044200452004620047200482004920050200512005220053200542005520056200572005820059200602006120062200632006420065200662006720068200692007020071200722007320074200752007620077200782007920080200812008220083200842008520086200872008820089200902009120092200932009420095200962009720098200992010020101201022010320104201052010620107201082010920110201112011220113201142011520116201172011820119201202012120122201232012420125201262012720128201292013020131201322013320134201352013620137201382013920140201412014220143201442014520146201472014820149201502015120152201532015420155201562015720158201592016020161201622016320164201652016620167201682016920170201712017220173201742017520176201772017820179201802018120182201832018420185201862018720188201892019020191201922019320194201952019620197201982019920200202012020220203202042020520206202072020820209202102021120212202132021420215202162021720218202192022020221202222022320224202252022620227202282022920230202312023220233202342023520236202372023820239202402024120242202432024420245202462024720248202492025020251202522025320254202552025620257202582025920260202612026220263202642026520266202672026820269202702027120272202732027420275202762027720278202792028020281202822028320284202852028620287202882028920290202912029220293202942029520296202972029820299203002030120302203032030420305203062030720308203092031020311203122031320314203152031620317203182031920320203212032220323203242032520326203272032820329203302033120332203332033420335203362033720338203392034020341203422034320344203452034620347203482034920350203512035220353203542035520356203572035820359203602036120362203632036420365203662036720368203692037020371203722037320374203752037620377203782037920380203812038220383203842038520386203872038820389203902039120392203932039420395203962039720398203992040020401204022040320404204052040620407204082040920410204112041220413204142041520416204172041820419204202042120422204232042420425204262042720428204292043020431204322043320434204352043620437204382043920440204412044220443204442044520446204472044820449204502045120452204532045420455204562045720458204592046020461204622046320464204652046620467204682046920470204712047220473204742047520476204772047820479204802048120482204832048420485204862048720488204892049020491204922049320494204952049620497204982049920500205012050220503205042050520506205072050820509205102051120512205132051420515205162051720518205192052020521205222052320524205252052620527205282052920530205312053220533205342053520536205372053820539205402054120542205432054420545205462054720548205492055020551205522055320554205552055620557205582055920560205612056220563205642056520566205672056820569205702057120572205732057420575205762057720578205792058020581205822058320584205852058620587205882058920590205912059220593205942059520596205972059820599206002060120602206032060420605206062060720608206092061020611206122061320614206152061620617206182061920620206212062220623206242062520626206272062820629206302063120632206332063420635206362063720638206392064020641206422064320644206452064620647206482064920650206512065220653206542065520656206572065820659206602066120662206632066420665206662066720668206692067020671206722067320674206752067620677206782067920680206812068220683206842068520686206872068820689206902069120692206932069420695206962069720698206992070020701207022070320704207052070620707207082070920710207112071220713207142071520716207172071820719207202072120722207232072420725207262072720728207292073020731207322073320734207352073620737207382073920740207412074220743207442074520746207472074820749207502075120752207532075420755207562075720758207592076020761207622076320764207652076620767207682076920770207712077220773207742077520776207772077820779207802078120782207832078420785207862078720788207892079020791207922079320794207952079620797207982079920800208012080220803208042080520806208072080820809208102081120812208132081420815208162081720818208192082020821208222082320824208252082620827208282082920830208312083220833208342083520836208372083820839208402084120842208432084420845208462084720848208492085020851208522085320854208552085620857208582085920860208612086220863208642086520866208672086820869208702087120872208732087420875208762087720878208792088020881208822088320884208852088620887208882088920890208912089220893208942089520896 |
- /* Xtensa configuration-specific ISA information.
- Copyright (C) 2003-2022 Free Software Foundation, Inc.
- This file is part of BFD, the Binary File Descriptor library.
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of the
- License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
- 02110-1301, USA. */
- #include "ansidecl.h"
- #include <xtensa-isa.h>
- #include "xtensa-isa-internal.h"
- /* Sysregs. */
- static xtensa_sysreg_internal sysregs[] = {
- { "LBEG", 0, 0 },
- { "LEND", 1, 0 },
- { "LCOUNT", 2, 0 },
- { "BR", 4, 0 },
- { "ACCLO", 16, 0 },
- { "ACCHI", 17, 0 },
- { "M0", 32, 0 },
- { "M1", 33, 0 },
- { "M2", 34, 0 },
- { "M3", 35, 0 },
- { "PTEVADDR", 83, 0 },
- { "MMID", 89, 0 },
- { "DDR", 104, 0 },
- { "176", 176, 0 },
- { "208", 208, 0 },
- { "INTERRUPT", 226, 0 },
- { "INTCLEAR", 227, 0 },
- { "CCOUNT", 234, 0 },
- { "PRID", 235, 0 },
- { "ICOUNT", 236, 0 },
- { "CCOMPARE0", 240, 0 },
- { "CCOMPARE1", 241, 0 },
- { "CCOMPARE2", 242, 0 },
- { "VECBASE", 231, 0 },
- { "EPC1", 177, 0 },
- { "EPC2", 178, 0 },
- { "EPC3", 179, 0 },
- { "EPC4", 180, 0 },
- { "EPC5", 181, 0 },
- { "EPC6", 182, 0 },
- { "EPC7", 183, 0 },
- { "EXCSAVE1", 209, 0 },
- { "EXCSAVE2", 210, 0 },
- { "EXCSAVE3", 211, 0 },
- { "EXCSAVE4", 212, 0 },
- { "EXCSAVE5", 213, 0 },
- { "EXCSAVE6", 214, 0 },
- { "EXCSAVE7", 215, 0 },
- { "EPS2", 194, 0 },
- { "EPS3", 195, 0 },
- { "EPS4", 196, 0 },
- { "EPS5", 197, 0 },
- { "EPS6", 198, 0 },
- { "EPS7", 199, 0 },
- { "EXCCAUSE", 232, 0 },
- { "DEPC", 192, 0 },
- { "EXCVADDR", 238, 0 },
- { "WINDOWBASE", 72, 0 },
- { "WINDOWSTART", 73, 0 },
- { "SAR", 3, 0 },
- { "LITBASE", 5, 0 },
- { "PS", 230, 0 },
- { "MISC0", 244, 0 },
- { "MISC1", 245, 0 },
- { "MISC2", 246, 0 },
- { "MISC3", 247, 0 },
- { "INTENABLE", 228, 0 },
- { "DBREAKA0", 144, 0 },
- { "DBREAKC0", 160, 0 },
- { "DBREAKA1", 145, 0 },
- { "DBREAKC1", 161, 0 },
- { "IBREAKA0", 128, 0 },
- { "IBREAKA1", 129, 0 },
- { "IBREAKENABLE", 96, 0 },
- { "ICOUNTLEVEL", 237, 0 },
- { "DEBUGCAUSE", 233, 0 },
- { "RASID", 90, 0 },
- { "ITLBCFG", 91, 0 },
- { "DTLBCFG", 92, 0 },
- { "CPENABLE", 224, 0 },
- { "SCOMPARE1", 12, 0 },
- { "THREADPTR", 231, 1 },
- { "FCR", 232, 1 },
- { "FSR", 233, 1 }
- };
- #define NUM_SYSREGS 74
- #define MAX_SPECIAL_REG 247
- #define MAX_USER_REG 233
- /* Processor states. */
- static xtensa_state_internal states[] = {
- { "LCOUNT", 32, 0 },
- { "PC", 32, 0 },
- { "ICOUNT", 32, 0 },
- { "DDR", 32, 0 },
- { "INTERRUPT", 32, 0 },
- { "CCOUNT", 32, 0 },
- { "XTSYNC", 1, 0 },
- { "VECBASE", 22, 0 },
- { "EPC1", 32, 0 },
- { "EPC2", 32, 0 },
- { "EPC3", 32, 0 },
- { "EPC4", 32, 0 },
- { "EPC5", 32, 0 },
- { "EPC6", 32, 0 },
- { "EPC7", 32, 0 },
- { "EXCSAVE1", 32, 0 },
- { "EXCSAVE2", 32, 0 },
- { "EXCSAVE3", 32, 0 },
- { "EXCSAVE4", 32, 0 },
- { "EXCSAVE5", 32, 0 },
- { "EXCSAVE6", 32, 0 },
- { "EXCSAVE7", 32, 0 },
- { "EPS2", 15, 0 },
- { "EPS3", 15, 0 },
- { "EPS4", 15, 0 },
- { "EPS5", 15, 0 },
- { "EPS6", 15, 0 },
- { "EPS7", 15, 0 },
- { "EXCCAUSE", 6, 0 },
- { "PSINTLEVEL", 4, 0 },
- { "PSUM", 1, 0 },
- { "PSWOE", 1, 0 },
- { "PSRING", 2, 0 },
- { "PSEXCM", 1, 0 },
- { "DEPC", 32, 0 },
- { "EXCVADDR", 32, 0 },
- { "WindowBase", 4, 0 },
- { "WindowStart", 16, 0 },
- { "PSCALLINC", 2, 0 },
- { "PSOWB", 4, 0 },
- { "LBEG", 32, 0 },
- { "LEND", 32, 0 },
- { "SAR", 6, 0 },
- { "THREADPTR", 32, 0 },
- { "LITBADDR", 20, 0 },
- { "LITBEN", 1, 0 },
- { "MISC0", 32, 0 },
- { "MISC1", 32, 0 },
- { "MISC2", 32, 0 },
- { "MISC3", 32, 0 },
- { "ACC", 40, 0 },
- { "InOCDMode", 1, 0 },
- { "INTENABLE", 32, 0 },
- { "DBREAKA0", 32, 0 },
- { "DBREAKC0", 8, 0 },
- { "DBREAKA1", 32, 0 },
- { "DBREAKC1", 8, 0 },
- { "IBREAKA0", 32, 0 },
- { "IBREAKA1", 32, 0 },
- { "IBREAKENABLE", 2, 0 },
- { "ICOUNTLEVEL", 4, 0 },
- { "DEBUGCAUSE", 6, 0 },
- { "DBNUM", 4, 0 },
- { "CCOMPARE0", 32, 0 },
- { "CCOMPARE1", 32, 0 },
- { "CCOMPARE2", 32, 0 },
- { "ASID3", 8, 0 },
- { "ASID2", 8, 0 },
- { "ASID1", 8, 0 },
- { "INSTPGSZID4", 2, 0 },
- { "DATAPGSZID4", 2, 0 },
- { "PTBASE", 10, 0 },
- { "CPENABLE", 1, 0 },
- { "SCOMPARE1", 32, 0 },
- { "RoundMode", 2, 0 },
- { "InvalidEnable", 1, 0 },
- { "DivZeroEnable", 1, 0 },
- { "OverflowEnable", 1, 0 },
- { "UnderflowEnable", 1, 0 },
- { "InexactEnable", 1, 0 },
- { "InvalidFlag", 1, 0 },
- { "DivZeroFlag", 1, 0 },
- { "OverflowFlag", 1, 0 },
- { "UnderflowFlag", 1, 0 },
- { "InexactFlag", 1, 0 },
- { "FPreserved20", 20, 0 },
- { "FPreserved20a", 20, 0 },
- { "FPreserved5", 5, 0 },
- { "FPreserved7", 7, 0 }
- };
- #define NUM_STATES 89
- /* Macros for xtensa_state numbers (for use in iclasses because the
- state numbers are not available when the iclass table is generated). */
- #define STATE_LCOUNT 0
- #define STATE_PC 1
- #define STATE_ICOUNT 2
- #define STATE_DDR 3
- #define STATE_INTERRUPT 4
- #define STATE_CCOUNT 5
- #define STATE_XTSYNC 6
- #define STATE_VECBASE 7
- #define STATE_EPC1 8
- #define STATE_EPC2 9
- #define STATE_EPC3 10
- #define STATE_EPC4 11
- #define STATE_EPC5 12
- #define STATE_EPC6 13
- #define STATE_EPC7 14
- #define STATE_EXCSAVE1 15
- #define STATE_EXCSAVE2 16
- #define STATE_EXCSAVE3 17
- #define STATE_EXCSAVE4 18
- #define STATE_EXCSAVE5 19
- #define STATE_EXCSAVE6 20
- #define STATE_EXCSAVE7 21
- #define STATE_EPS2 22
- #define STATE_EPS3 23
- #define STATE_EPS4 24
- #define STATE_EPS5 25
- #define STATE_EPS6 26
- #define STATE_EPS7 27
- #define STATE_EXCCAUSE 28
- #define STATE_PSINTLEVEL 29
- #define STATE_PSUM 30
- #define STATE_PSWOE 31
- #define STATE_PSRING 32
- #define STATE_PSEXCM 33
- #define STATE_DEPC 34
- #define STATE_EXCVADDR 35
- #define STATE_WindowBase 36
- #define STATE_WindowStart 37
- #define STATE_PSCALLINC 38
- #define STATE_PSOWB 39
- #define STATE_LBEG 40
- #define STATE_LEND 41
- #define STATE_SAR 42
- #define STATE_THREADPTR 43
- #define STATE_LITBADDR 44
- #define STATE_LITBEN 45
- #define STATE_MISC0 46
- #define STATE_MISC1 47
- #define STATE_MISC2 48
- #define STATE_MISC3 49
- #define STATE_ACC 50
- #define STATE_InOCDMode 51
- #define STATE_INTENABLE 52
- #define STATE_DBREAKA0 53
- #define STATE_DBREAKC0 54
- #define STATE_DBREAKA1 55
- #define STATE_DBREAKC1 56
- #define STATE_IBREAKA0 57
- #define STATE_IBREAKA1 58
- #define STATE_IBREAKENABLE 59
- #define STATE_ICOUNTLEVEL 60
- #define STATE_DEBUGCAUSE 61
- #define STATE_DBNUM 62
- #define STATE_CCOMPARE0 63
- #define STATE_CCOMPARE1 64
- #define STATE_CCOMPARE2 65
- #define STATE_ASID3 66
- #define STATE_ASID2 67
- #define STATE_ASID1 68
- #define STATE_INSTPGSZID4 69
- #define STATE_DATAPGSZID4 70
- #define STATE_PTBASE 71
- #define STATE_CPENABLE 72
- #define STATE_SCOMPARE1 73
- #define STATE_RoundMode 74
- #define STATE_InvalidEnable 75
- #define STATE_DivZeroEnable 76
- #define STATE_OverflowEnable 77
- #define STATE_UnderflowEnable 78
- #define STATE_InexactEnable 79
- #define STATE_InvalidFlag 80
- #define STATE_DivZeroFlag 81
- #define STATE_OverflowFlag 82
- #define STATE_UnderflowFlag 83
- #define STATE_InexactFlag 84
- #define STATE_FPreserved20 85
- #define STATE_FPreserved20a 86
- #define STATE_FPreserved5 87
- #define STATE_FPreserved7 88
- /* Field definitions. */
- static unsigned
- Field_t_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xf;
- return tie_t;
- }
- static void
- Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- }
- static unsigned
- Field_t_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- }
- static unsigned
- Field_t_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xf;
- return tie_t;
- }
- static void
- Field_t_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- }
- static unsigned
- Field_t_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0xf;
- return tie_t;
- }
- static void
- Field_t_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- }
- static unsigned
- Field_t_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0xf;
- return tie_t;
- }
- static void
- Field_t_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- }
- static unsigned
- Field_t_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0xf;
- return tie_t;
- }
- static void
- Field_t_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- }
- static unsigned
- Field_t_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0xf;
- return tie_t;
- }
- static void
- Field_t_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- }
- static unsigned
- Field_bbi4_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- return tie_t;
- }
- static void
- Field_bbi4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_bbi_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_bbi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_bbi_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 26) & 1;
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_bbi_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- }
- static unsigned
- Field_imm12_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xfff;
- return tie_t;
- }
- static void
- Field_imm12_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xfff;
- insn[0] = (insn[0] & ~0xfff000) | (tie_t << 12);
- }
- static unsigned
- Field_imm8_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 0xff;
- return tie_t;
- }
- static void
- Field_imm8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xff;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
- }
- static unsigned
- Field_imm8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xff;
- return tie_t;
- }
- static void
- Field_imm8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xff;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
- }
- static unsigned
- Field_imm8_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_imm8_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_s_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- return tie_t;
- }
- static void
- Field_s_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_s_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- return tie_t;
- }
- static void
- Field_s_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_s_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- return tie_t;
- }
- static void
- Field_s_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_s_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xf;
- return tie_t;
- }
- static void
- Field_s_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- }
- static unsigned
- Field_s_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- return tie_t;
- }
- static void
- Field_s_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_s_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- return tie_t;
- }
- static void
- Field_s_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_s_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xf;
- return tie_t;
- }
- static void
- Field_s_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- }
- static unsigned
- Field_imm12b_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- tie_t = (tie_t << 8) | ((insn[0] >> 16) & 0xff);
- return tie_t;
- }
- static void
- Field_imm12b_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xff;
- insn[0] = (insn[0] & ~0xff0000) | (tie_t << 16);
- tie_t = (val >> 8) & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_imm12b_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xf;
- tie_t = (tie_t << 8) | ((insn[0] >> 12) & 0xff);
- return tie_t;
- }
- static void
- Field_imm12b_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xff;
- insn[0] = (insn[0] & ~0xff000) | (tie_t << 12);
- tie_t = (val >> 8) & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- }
- static unsigned
- Field_imm12b_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xfff;
- return tie_t;
- }
- static void
- Field_imm12b_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xfff;
- insn[0] = (insn[0] & ~0xfff0) | (tie_t << 4);
- }
- static unsigned
- Field_imm16_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xffff;
- return tie_t;
- }
- static void
- Field_imm16_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xffff;
- insn[0] = (insn[0] & ~0xffff00) | (tie_t << 8);
- }
- static unsigned
- Field_imm16_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xffff;
- return tie_t;
- }
- static void
- Field_imm16_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xffff;
- insn[0] = (insn[0] & ~0xffff0) | (tie_t << 4);
- }
- static unsigned
- Field_m_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 3;
- return tie_t;
- }
- static void
- Field_m_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- }
- static unsigned
- Field_m_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 2) & 3;
- return tie_t;
- }
- static void
- Field_m_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc) | (tie_t << 2);
- }
- static unsigned
- Field_n_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 3;
- return tie_t;
- }
- static void
- Field_n_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- }
- static unsigned
- Field_n_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 3;
- return tie_t;
- }
- static void
- Field_n_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x3) | (tie_t << 0);
- }
- static unsigned
- Field_offset_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 0x3ffff;
- return tie_t;
- }
- static void
- Field_offset_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x3ffff;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
- }
- static unsigned
- Field_offset_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0x3ffff;
- return tie_t;
- }
- static void
- Field_offset_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x3ffff;
- insn[0] = (insn[0] & ~0x3ffff) | (tie_t << 0);
- }
- static unsigned
- Field_op0_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0xf;
- return tie_t;
- }
- static void
- Field_op0_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- }
- static unsigned
- Field_op0_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0xf;
- return tie_t;
- }
- static void
- Field_op0_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- }
- static unsigned
- Field_op0_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0xf;
- return tie_t;
- }
- static void
- Field_op0_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- }
- static unsigned
- Field_op1_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 0xf;
- return tie_t;
- }
- static void
- Field_op1_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- }
- static unsigned
- Field_op1_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_op1_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_op2_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 20) & 0xf;
- return tie_t;
- }
- static void
- Field_op2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
- }
- static unsigned
- Field_op2_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 0xf;
- return tie_t;
- }
- static void
- Field_op2_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- }
- static unsigned
- Field_op2_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- return tie_t;
- }
- static void
- Field_op2_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_r_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_r_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_r_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_r_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_r_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_r_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_r_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- return tie_t;
- }
- static void
- Field_r_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_r_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xf;
- return tie_t;
- }
- static void
- Field_r_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- }
- static unsigned
- Field_r_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 0xf;
- return tie_t;
- }
- static void
- Field_r_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- }
- static unsigned
- Field_r_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0xf;
- return tie_t;
- }
- static void
- Field_r_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- }
- static unsigned
- Field_sa4_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 20) & 1;
- return tie_t;
- }
- static void
- Field_sa4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
- }
- static unsigned
- Field_sae4_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 1;
- return tie_t;
- }
- static void
- Field_sae4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
- }
- static unsigned
- Field_sae4_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] << 12) & 1;
- return tie_t;
- }
- static void
- Field_sae4_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_sae_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 1;
- tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
- return tie_t;
- }
- static void
- Field_sae_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
- }
- static unsigned
- Field_sae_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_sae_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_sae_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x1f;
- return tie_t;
- }
- static void
- Field_sae_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x1f;
- insn[0] = (insn[0] & ~0x1f000) | (tie_t << 12);
- }
- static unsigned
- Field_sal_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 20) & 1;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_sal_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
- }
- static unsigned
- Field_sal_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 1;
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_sal_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
- }
- static unsigned
- Field_sal_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_sal_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_sargt_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 20) & 1;
- tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
- return tie_t;
- }
- static void
- Field_sargt_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x100000) | (tie_t << 20);
- }
- static unsigned
- Field_sargt_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 1;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_sargt_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x10000) | (tie_t << 16);
- }
- static unsigned
- Field_sargt_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0x1f;
- return tie_t;
- }
- static void
- Field_sargt_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x1f;
- insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
- }
- static unsigned
- Field_sargt_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0x1f;
- return tie_t;
- }
- static void
- Field_sargt_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x1f;
- insn[0] = (insn[0] & ~0x1f00) | (tie_t << 8);
- }
- static unsigned
- Field_sas4_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 1;
- return tie_t;
- }
- static void
- Field_sas4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
- }
- static unsigned
- Field_sas_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 1;
- tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
- return tie_t;
- }
- static void
- Field_sas_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
- }
- static unsigned
- Field_sas_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 1;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_sas_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x1) | (tie_t << 0);
- }
- static unsigned
- Field_sr_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
- return tie_t;
- }
- static void
- Field_sr_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val >> 4) & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_sr_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
- return tie_t;
- }
- static void
- Field_sr_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val >> 4) & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_sr_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
- return tie_t;
- }
- static void
- Field_sr_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val >> 4) & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_st_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_st_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_st_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_st_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_st_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- tie_t = (tie_t << 4) | ((insn[0] >> 4) & 0xf);
- return tie_t;
- }
- static void
- Field_st_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf0) | (tie_t << 4);
- tie_t = (val >> 4) & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_thi3_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 5) & 7;
- return tie_t;
- }
- static void
- Field_thi3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
- }
- static unsigned
- Field_thi3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 1) & 7;
- return tie_t;
- }
- static void
- Field_thi3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe) | (tie_t << 1);
- }
- static unsigned
- Field_imm4_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_imm4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_imm4_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_imm4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_imm4_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_imm4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_mn_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 3;
- tie_t = (tie_t << 2) | ((insn[0] >> 4) & 3);
- return tie_t;
- }
- static void
- Field_mn_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- tie_t = (val >> 2) & 3;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- }
- static unsigned
- Field_i_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- return tie_t;
- }
- static void
- Field_i_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_i_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- return tie_t;
- }
- static void
- Field_i_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_imm6lo_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_imm6lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_imm6lo_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_imm6lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_imm6hi_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 3;
- return tie_t;
- }
- static void
- Field_imm6hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- }
- static unsigned
- Field_imm6hi_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 3;
- return tie_t;
- }
- static void
- Field_imm6hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- }
- static unsigned
- Field_imm7lo_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_imm7lo_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_imm7lo_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_imm7lo_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_imm7hi_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 7;
- return tie_t;
- }
- static void
- Field_imm7hi_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- }
- static unsigned
- Field_imm7hi_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 7;
- return tie_t;
- }
- static void
- Field_imm7hi_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- }
- static unsigned
- Field_z_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 1;
- return tie_t;
- }
- static void
- Field_z_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- }
- static unsigned
- Field_z_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 1;
- return tie_t;
- }
- static void
- Field_z_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- }
- static unsigned
- Field_imm6_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 3;
- tie_t = (tie_t << 4) | ((insn[0] >> 12) & 0xf);
- return tie_t;
- }
- static void
- Field_imm6_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val >> 4) & 3;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- }
- static unsigned
- Field_imm6_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 3;
- tie_t = (tie_t << 4) | ((insn[0] >> 12) & 0xf);
- return tie_t;
- }
- static void
- Field_imm6_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val >> 4) & 3;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- }
- static unsigned
- Field_imm7_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 7;
- tie_t = (tie_t << 4) | ((insn[0] >> 12) & 0xf);
- return tie_t;
- }
- static void
- Field_imm7_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val >> 4) & 7;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- }
- static unsigned
- Field_imm7_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 7;
- tie_t = (tie_t << 4) | ((insn[0] >> 12) & 0xf);
- return tie_t;
- }
- static void
- Field_imm7_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- tie_t = (val >> 4) & 7;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- }
- static unsigned
- Field_imm7_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[0] & 0x7f;
- return tie_t;
- }
- static void
- Field_imm7_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t;
- tie_t = val & 0x7f;
- insn[0] = (insn[0] & ~0x7f) | (tie_t << 0);
- }
- static unsigned
- Field_r3_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 15) & 1;
- return tie_t;
- }
- static void
- Field_r3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
- }
- static unsigned
- Field_rbit2_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 14) & 1;
- return tie_t;
- }
- static void
- Field_rbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
- }
- static unsigned
- Field_rhi_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 14) & 3;
- return tie_t;
- }
- static void
- Field_rhi_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- }
- static unsigned
- Field_t3_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- return tie_t;
- }
- static void
- Field_t3_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_tbit2_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 1;
- return tie_t;
- }
- static void
- Field_tbit2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- }
- static unsigned
- Field_tlo_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 4) & 3;
- return tie_t;
- }
- static void
- Field_tlo_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x30) | (tie_t << 4);
- }
- static unsigned
- Field_w_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 3;
- return tie_t;
- }
- static void
- Field_w_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x3000) | (tie_t << 12);
- }
- static unsigned
- Field_y_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 1;
- return tie_t;
- }
- static void
- Field_y_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- }
- static unsigned
- Field_x_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 14) & 1;
- return tie_t;
- }
- static void
- Field_x_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000) | (tie_t << 14);
- }
- static unsigned
- Field_t2_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 5) & 7;
- return tie_t;
- }
- static void
- Field_t2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
- }
- static unsigned
- Field_t2_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 5) & 7;
- return tie_t;
- }
- static void
- Field_t2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
- }
- static unsigned
- Field_t2_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 5) & 7;
- return tie_t;
- }
- static void
- Field_t2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe0) | (tie_t << 5);
- }
- static unsigned
- Field_s2_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 9) & 7;
- return tie_t;
- }
- static void
- Field_s2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- }
- static unsigned
- Field_s2_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 9) & 7;
- return tie_t;
- }
- static void
- Field_s2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- }
- static unsigned
- Field_s2_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 9) & 7;
- return tie_t;
- }
- static void
- Field_s2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe00) | (tie_t << 9);
- }
- static unsigned
- Field_r2_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 13) & 7;
- return tie_t;
- }
- static void
- Field_r2_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
- }
- static unsigned
- Field_r2_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 13) & 7;
- return tie_t;
- }
- static void
- Field_r2_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
- }
- static unsigned
- Field_r2_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 13) & 7;
- return tie_t;
- }
- static void
- Field_r2_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
- }
- static unsigned
- Field_t4_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 3;
- return tie_t;
- }
- static void
- Field_t4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- }
- static unsigned
- Field_t4_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 3;
- return tie_t;
- }
- static void
- Field_t4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- }
- static unsigned
- Field_t4_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 3;
- return tie_t;
- }
- static void
- Field_t4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc0) | (tie_t << 6);
- }
- static unsigned
- Field_s4_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 10) & 3;
- return tie_t;
- }
- static void
- Field_s4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
- }
- static unsigned
- Field_s4_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 10) & 3;
- return tie_t;
- }
- static void
- Field_s4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
- }
- static unsigned
- Field_s4_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 10) & 3;
- return tie_t;
- }
- static void
- Field_s4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
- }
- static unsigned
- Field_r4_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 14) & 3;
- return tie_t;
- }
- static void
- Field_r4_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- }
- static unsigned
- Field_r4_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 14) & 3;
- return tie_t;
- }
- static void
- Field_r4_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- }
- static unsigned
- Field_r4_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 14) & 3;
- return tie_t;
- }
- static void
- Field_r4_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc000) | (tie_t << 14);
- }
- static unsigned
- Field_t8_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- return tie_t;
- }
- static void
- Field_t8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_t8_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- return tie_t;
- }
- static void
- Field_t8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_t8_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- return tie_t;
- }
- static void
- Field_t8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_s8_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 11) & 1;
- return tie_t;
- }
- static void
- Field_s8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
- }
- static unsigned
- Field_s8_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 11) & 1;
- return tie_t;
- }
- static void
- Field_s8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
- }
- static unsigned
- Field_s8_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 11) & 1;
- return tie_t;
- }
- static void
- Field_s8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
- }
- static unsigned
- Field_r8_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 15) & 1;
- return tie_t;
- }
- static void
- Field_r8_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
- }
- static unsigned
- Field_r8_Slot_inst16a_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 15) & 1;
- return tie_t;
- }
- static void
- Field_r8_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
- }
- static unsigned
- Field_r8_Slot_inst16b_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 15) & 1;
- return tie_t;
- }
- static void
- Field_r8_Slot_inst16b_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x8000) | (tie_t << 15);
- }
- static unsigned
- Field_xt_wbr15_imm_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 9) & 0x7fff;
- return tie_t;
- }
- static void
- Field_xt_wbr15_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x7fff;
- insn[0] = (insn[0] & ~0xfffe00) | (tie_t << 9);
- }
- static unsigned
- Field_xt_wbr18_imm_Slot_inst_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 6) & 0x3ffff;
- return tie_t;
- }
- static void
- Field_xt_wbr18_imm_Slot_inst_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x3ffff;
- insn[0] = (insn[0] & ~0xffffc0) | (tie_t << 6);
- }
- static unsigned
- Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0x3ffff;
- return tie_t;
- }
- static void
- Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x3ffff;
- insn[0] = (insn[0] & ~0x3ffff00) | (tie_t << 8);
- }
- static unsigned
- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 20) & 0xf;
- return tie_t;
- }
- static void
- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
- }
- static unsigned
- Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 13) & 7;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
- }
- static unsigned
- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 13) & 7;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
- }
- static unsigned
- Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 17) & 7;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
- }
- static unsigned
- Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 17) & 7;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe0000) | (tie_t << 17);
- }
- static unsigned
- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 0xf;
- tie_t = (tie_t << 4) | ((insn[0] >> 8) & 0xf);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- tie_t = (val >> 4) & 0xf;
- insn[0] = (insn[0] & ~0xf0000) | (tie_t << 16);
- }
- static unsigned
- Field_op0_s4_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 18) & 3;
- return tie_t;
- }
- static void
- Field_op0_s4_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc0000) | (tie_t << 18);
- }
- static unsigned
- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0xf;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 17) & 1;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x20000) | (tie_t << 17);
- }
- static unsigned
- Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 16) & 3;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x30000) | (tie_t << 16);
- }
- static unsigned
- Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 13) & 0x1f;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x1f;
- insn[0] = (insn[0] & ~0x3e000) | (tie_t << 13);
- }
- static unsigned
- Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x3f;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x3f;
- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x3f;
- tie_t = (tie_t << 3) | ((insn[0] >> 4) & 7);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- tie_t = (val >> 3) & 0x3f;
- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x3f;
- tie_t = (tie_t << 3) | ((insn[0] >> 4) & 7);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0x70) | (tie_t << 4);
- tie_t = (val >> 3) & 0x3f;
- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x3f;
- tie_t = (tie_t << 2) | ((insn[0] >> 5) & 3);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
- tie_t = (val >> 2) & 0x3f;
- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x3f;
- tie_t = (tie_t << 1) | ((insn[0] >> 6) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x40) | (tie_t << 6);
- tie_t = (val >> 1) & 0x3f;
- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x3f;
- tie_t = (tie_t << 2) | ((insn[0] >> 8) & 3);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
- tie_t = (val >> 2) & 0x3f;
- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x3f;
- tie_t = (tie_t << 2) | ((insn[0] >> 8) & 3);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
- tie_t = (val >> 2) & 0x3f;
- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 0x3f;
- tie_t = (tie_t << 1) | ((insn[0] >> 9) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x200) | (tie_t << 9);
- tie_t = (val >> 1) & 0x3f;
- insn[0] = (insn[0] & ~0x3f000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 15) & 7;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0x38000) | (tie_t << 15);
- }
- static unsigned
- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 10) & 3;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
- }
- static unsigned
- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 0x1f;
- tie_t = (tie_t << 6) | (insn[0] & 0x3f);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x3f;
- insn[0] = (insn[0] & ~0x3f) | (tie_t << 0);
- tie_t = (val >> 6) & 0x1f;
- insn[0] = (insn[0] & ~0xf80) | (tie_t << 7);
- }
- static unsigned
- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 10) & 3;
- tie_t = (tie_t << 1) | ((insn[0] >> 8) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val >> 1) & 3;
- insn[0] = (insn[0] & ~0xc00) | (tie_t << 10);
- }
- static unsigned
- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 7) & 1;
- tie_t = (tie_t << 5) | (insn[0] & 0x1f);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x1f;
- insn[0] = (insn[0] & ~0x1f) | (tie_t << 0);
- tie_t = (val >> 5) & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- }
- static unsigned
- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 7;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0x7000) | (tie_t << 12);
- }
- static unsigned
- Field_op0_s5_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 13) & 7;
- return tie_t;
- }
- static void
- Field_op0_s5_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0xe000) | (tie_t << 13);
- }
- static unsigned
- Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 1) | ((insn[0] >> 7) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val >> 1) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 1) | ((insn[0] >> 7) & 1);
- tie_t = (tie_t << 1) | ((insn[0] >> 4) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
- tie_t = (val >> 1) & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val >> 2) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 1) | ((insn[0] >> 7) & 1);
- tie_t = (tie_t << 1) | ((insn[0] >> 4) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x10) | (tie_t << 4);
- tie_t = (val >> 1) & 1;
- insn[0] = (insn[0] & ~0x80) | (tie_t << 7);
- tie_t = (val >> 2) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 3) | ((insn[0] >> 8) & 7);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
- tie_t = (val >> 3) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 3) | ((insn[0] >> 8) & 7);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[0] = (insn[0] & ~0x700) | (tie_t << 8);
- tie_t = (val >> 3) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 2) | ((insn[0] >> 9) & 3);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x600) | (tie_t << 9);
- tie_t = (val >> 2) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 12) & 1;
- tie_t = (tie_t << 1) | ((insn[0] >> 10) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x400) | (tie_t << 10);
- tie_t = (val >> 1) & 1;
- insn[0] = (insn[0] & ~0x1000) | (tie_t << 12);
- }
- static unsigned
- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 5) & 3;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
- }
- static unsigned
- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 11) & 1;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
- }
- static unsigned
- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 8) & 0xf;
- tie_t = (tie_t << 2) | ((insn[0] >> 5) & 3);
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 3;
- insn[0] = (insn[0] & ~0x60) | (tie_t << 5);
- tie_t = (val >> 6) & 0xf;
- insn[0] = (insn[0] & ~0xf00) | (tie_t << 8);
- }
- static unsigned
- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 11) & 1;
- tie_t = (tie_t << 1) | ((insn[0] >> 8) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x100) | (tie_t << 8);
- tie_t = (val >> 1) & 1;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
- }
- static unsigned
- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 11) & 1;
- tie_t = (tie_t << 2) | ((insn[0] >> 8) & 3);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 3;
- insn[0] = (insn[0] & ~0x300) | (tie_t << 8);
- tie_t = (val >> 2) & 1;
- insn[0] = (insn[0] & ~0x800) | (tie_t << 11);
- }
- static unsigned
- Field_op0_s6_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 27) & 0x1f;
- return tie_t;
- }
- static void
- Field_op0_s6_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0x1f;
- insn[0] = (insn[0] & ~0xf8000000) | (tie_t << 27);
- }
- static unsigned
- Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 5) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 5) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 5) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- tie_t = (tie_t << 4) | (insn[0] & 0xf);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf) | (tie_t << 0);
- tie_t = (val >> 4) & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 5) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 1) | ((insn[0] >> 26) & 1);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 1;
- insn[0] = (insn[0] & ~0x4000000) | (tie_t << 26);
- tie_t = (val >> 1) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = insn[1] & 7;
- tie_t = (tie_t << 27) | (insn[0] & 0x7ffffff);
- return tie_t;
- }
- static void
- Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t;
- tie_t = val & 0x7ffffff;
- insn[0] = (insn[0] & ~0x7ffffff) | (tie_t << 0);
- tie_t = (val >> 27) & 7;
- insn[1] = (insn[1] & ~0x7) | (tie_t << 0);
- }
- static unsigned
- Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (const xtensa_insnbuf insn)
- {
- unsigned tie_t = (insn[0] >> 20) & 0xf;
- return tie_t;
- }
- static void
- Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set (xtensa_insnbuf insn, uint32 val)
- {
- uint32 tie_t = val & 0xf;
- insn[0] = (insn[0] & ~0xf00000) | (tie_t << 20);
- }
- static void
- Implicit_Field_set (xtensa_insnbuf insn ATTRIBUTE_UNUSED,
- uint32 val ATTRIBUTE_UNUSED)
- {
- /* Do nothing. */
- }
- static unsigned
- Implicit_Field_ar0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static unsigned
- Implicit_Field_ar4_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 4;
- }
- static unsigned
- Implicit_Field_ar8_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 8;
- }
- static unsigned
- Implicit_Field_ar12_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 12;
- }
- static unsigned
- Implicit_Field_mr0_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static unsigned
- Implicit_Field_mr1_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 1;
- }
- static unsigned
- Implicit_Field_mr2_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 2;
- }
- static unsigned
- Implicit_Field_mr3_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 3;
- }
- static unsigned
- Implicit_Field_bt16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static unsigned
- Implicit_Field_bs16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static unsigned
- Implicit_Field_br16_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static unsigned
- Implicit_Field_brall_get (const xtensa_insnbuf insn ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- /* Functional units. */
- static xtensa_funcUnit_internal funcUnits[] = {
- };
- /* Register files. */
- static xtensa_regfile_internal regfiles[] = {
- { "AR", "a", 0, 32, 64 },
- { "MR", "m", 1, 32, 4 },
- { "BR", "b", 2, 1, 16 },
- { "FR", "f", 3, 32, 16 },
- { "BR2", "b", 2, 2, 8 },
- { "BR4", "b", 2, 4, 4 },
- { "BR8", "b", 2, 8, 2 },
- { "BR16", "b", 2, 16, 1 }
- };
- /* Interfaces. */
- static xtensa_interface_internal interfaces[] = {
- };
- /* Constant tables. */
- /* constant table ai4c */
- static const unsigned CONST_TBL_ai4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0x9,
- 0xa,
- 0xb,
- 0xc,
- 0xd,
- 0xe,
- 0xf,
- 0
- };
- /* constant table b4c */
- static const unsigned CONST_TBL_b4c_0[] = {
- 0xffffffff,
- 0x1,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
- };
- /* constant table b4cu */
- static const unsigned CONST_TBL_b4cu_0[] = {
- 0x8000,
- 0x10000,
- 0x2,
- 0x3,
- 0x4,
- 0x5,
- 0x6,
- 0x7,
- 0x8,
- 0xa,
- 0xc,
- 0x10,
- 0x20,
- 0x40,
- 0x80,
- 0x100,
- 0
- };
- /* Instruction operands. */
- static int
- Operand_soffsetx4_decode (uint32 *valp)
- {
- unsigned soffsetx4_0, offset_0;
- offset_0 = *valp & 0x3ffff;
- soffsetx4_0 = 0x4 + (((offset_0 ^ 0x20000) - 0x20000) << 2);
- *valp = soffsetx4_0;
- return 0;
- }
- static int
- Operand_soffsetx4_encode (uint32 *valp)
- {
- unsigned offset_0, soffsetx4_0;
- soffsetx4_0 = *valp;
- offset_0 = ((soffsetx4_0 - 0x4) >> 2) & 0x3ffff;
- *valp = offset_0;
- return 0;
- }
- static int
- Operand_soffsetx4_ator (uint32 *valp, uint32 pc)
- {
- *valp -= (pc & ~0x3);
- return 0;
- }
- static int
- Operand_soffsetx4_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += (pc & ~0x3);
- return 0;
- }
- static int
- Operand_uimm12x8_decode (uint32 *valp)
- {
- unsigned uimm12x8_0, imm12_0;
- imm12_0 = *valp & 0xfff;
- uimm12x8_0 = imm12_0 << 3;
- *valp = uimm12x8_0;
- return 0;
- }
- static int
- Operand_uimm12x8_encode (uint32 *valp)
- {
- unsigned imm12_0, uimm12x8_0;
- uimm12x8_0 = *valp;
- imm12_0 = ((uimm12x8_0 >> 3) & 0xfff);
- *valp = imm12_0;
- return 0;
- }
- static int
- Operand_simm4_decode (uint32 *valp)
- {
- unsigned simm4_0, mn_0;
- mn_0 = *valp & 0xf;
- simm4_0 = (mn_0 ^ 0x8) - 0x8;
- *valp = simm4_0;
- return 0;
- }
- static int
- Operand_simm4_encode (uint32 *valp)
- {
- unsigned mn_0, simm4_0;
- simm4_0 = *valp;
- mn_0 = (simm4_0 & 0xf);
- *valp = mn_0;
- return 0;
- }
- static int
- Operand_arr_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_arr_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static int
- Operand_ars_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_ars_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static int
- Operand_art_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_art_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static int
- Operand_ar0_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_ar0_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3f) != 0;
- return error;
- }
- static int
- Operand_ar4_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_ar4_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3f) != 0;
- return error;
- }
- static int
- Operand_ar8_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_ar8_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3f) != 0;
- return error;
- }
- static int
- Operand_ar12_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_ar12_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3f) != 0;
- return error;
- }
- static int
- Operand_ars_entry_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_ars_entry_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3f) != 0;
- return error;
- }
- static int
- Operand_immrx4_decode (uint32 *valp)
- {
- unsigned immrx4_0, r_0;
- r_0 = *valp & 0xf;
- immrx4_0 = (0xfffffff0 | r_0) << 2;
- *valp = immrx4_0;
- return 0;
- }
- static int
- Operand_immrx4_encode (uint32 *valp)
- {
- unsigned r_0, immrx4_0;
- immrx4_0 = *valp;
- r_0 = ((immrx4_0 >> 2) & 0xf);
- *valp = r_0;
- return 0;
- }
- static int
- Operand_lsi4x4_decode (uint32 *valp)
- {
- unsigned lsi4x4_0, r_0;
- r_0 = *valp & 0xf;
- lsi4x4_0 = r_0 << 2;
- *valp = lsi4x4_0;
- return 0;
- }
- static int
- Operand_lsi4x4_encode (uint32 *valp)
- {
- unsigned r_0, lsi4x4_0;
- lsi4x4_0 = *valp;
- r_0 = ((lsi4x4_0 >> 2) & 0xf);
- *valp = r_0;
- return 0;
- }
- static int
- Operand_simm7_decode (uint32 *valp)
- {
- unsigned simm7_0, imm7_0;
- imm7_0 = *valp & 0x7f;
- simm7_0 = ((((-((((imm7_0 >> 6) & 1)) & (((imm7_0 >> 5) & 1)))) & 0x1ffffff)) << 7) | imm7_0;
- *valp = simm7_0;
- return 0;
- }
- static int
- Operand_simm7_encode (uint32 *valp)
- {
- unsigned imm7_0, simm7_0;
- simm7_0 = *valp;
- imm7_0 = (simm7_0 & 0x7f);
- *valp = imm7_0;
- return 0;
- }
- static int
- Operand_uimm6_decode (uint32 *valp)
- {
- unsigned uimm6_0, imm6_0;
- imm6_0 = *valp & 0x3f;
- uimm6_0 = 0x4 + (((0) << 6) | imm6_0);
- *valp = uimm6_0;
- return 0;
- }
- static int
- Operand_uimm6_encode (uint32 *valp)
- {
- unsigned imm6_0, uimm6_0;
- uimm6_0 = *valp;
- imm6_0 = (uimm6_0 - 0x4) & 0x3f;
- *valp = imm6_0;
- return 0;
- }
- static int
- Operand_uimm6_ator (uint32 *valp, uint32 pc)
- {
- *valp -= pc;
- return 0;
- }
- static int
- Operand_uimm6_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += pc;
- return 0;
- }
- static int
- Operand_ai4const_decode (uint32 *valp)
- {
- unsigned ai4const_0, t_0;
- t_0 = *valp & 0xf;
- ai4const_0 = CONST_TBL_ai4c_0[t_0 & 0xf];
- *valp = ai4const_0;
- return 0;
- }
- static int
- Operand_ai4const_encode (uint32 *valp)
- {
- unsigned t_0, ai4const_0;
- ai4const_0 = *valp;
- switch (ai4const_0)
- {
- case 0xffffffff: t_0 = 0; break;
- case 0x1: t_0 = 0x1; break;
- case 0x2: t_0 = 0x2; break;
- case 0x3: t_0 = 0x3; break;
- case 0x4: t_0 = 0x4; break;
- case 0x5: t_0 = 0x5; break;
- case 0x6: t_0 = 0x6; break;
- case 0x7: t_0 = 0x7; break;
- case 0x8: t_0 = 0x8; break;
- case 0x9: t_0 = 0x9; break;
- case 0xa: t_0 = 0xa; break;
- case 0xb: t_0 = 0xb; break;
- case 0xc: t_0 = 0xc; break;
- case 0xd: t_0 = 0xd; break;
- case 0xe: t_0 = 0xe; break;
- default: t_0 = 0xf; break;
- }
- *valp = t_0;
- return 0;
- }
- static int
- Operand_b4const_decode (uint32 *valp)
- {
- unsigned b4const_0, r_0;
- r_0 = *valp & 0xf;
- b4const_0 = CONST_TBL_b4c_0[r_0 & 0xf];
- *valp = b4const_0;
- return 0;
- }
- static int
- Operand_b4const_encode (uint32 *valp)
- {
- unsigned r_0, b4const_0;
- b4const_0 = *valp;
- switch (b4const_0)
- {
- case 0xffffffff: r_0 = 0; break;
- case 0x1: r_0 = 0x1; break;
- case 0x2: r_0 = 0x2; break;
- case 0x3: r_0 = 0x3; break;
- case 0x4: r_0 = 0x4; break;
- case 0x5: r_0 = 0x5; break;
- case 0x6: r_0 = 0x6; break;
- case 0x7: r_0 = 0x7; break;
- case 0x8: r_0 = 0x8; break;
- case 0xa: r_0 = 0x9; break;
- case 0xc: r_0 = 0xa; break;
- case 0x10: r_0 = 0xb; break;
- case 0x20: r_0 = 0xc; break;
- case 0x40: r_0 = 0xd; break;
- case 0x80: r_0 = 0xe; break;
- default: r_0 = 0xf; break;
- }
- *valp = r_0;
- return 0;
- }
- static int
- Operand_b4constu_decode (uint32 *valp)
- {
- unsigned b4constu_0, r_0;
- r_0 = *valp & 0xf;
- b4constu_0 = CONST_TBL_b4cu_0[r_0 & 0xf];
- *valp = b4constu_0;
- return 0;
- }
- static int
- Operand_b4constu_encode (uint32 *valp)
- {
- unsigned r_0, b4constu_0;
- b4constu_0 = *valp;
- switch (b4constu_0)
- {
- case 0x8000: r_0 = 0; break;
- case 0x10000: r_0 = 0x1; break;
- case 0x2: r_0 = 0x2; break;
- case 0x3: r_0 = 0x3; break;
- case 0x4: r_0 = 0x4; break;
- case 0x5: r_0 = 0x5; break;
- case 0x6: r_0 = 0x6; break;
- case 0x7: r_0 = 0x7; break;
- case 0x8: r_0 = 0x8; break;
- case 0xa: r_0 = 0x9; break;
- case 0xc: r_0 = 0xa; break;
- case 0x10: r_0 = 0xb; break;
- case 0x20: r_0 = 0xc; break;
- case 0x40: r_0 = 0xd; break;
- case 0x80: r_0 = 0xe; break;
- default: r_0 = 0xf; break;
- }
- *valp = r_0;
- return 0;
- }
- static int
- Operand_uimm8_decode (uint32 *valp)
- {
- unsigned uimm8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8_0 = imm8_0;
- *valp = uimm8_0;
- return 0;
- }
- static int
- Operand_uimm8_encode (uint32 *valp)
- {
- unsigned imm8_0, uimm8_0;
- uimm8_0 = *valp;
- imm8_0 = (uimm8_0 & 0xff);
- *valp = imm8_0;
- return 0;
- }
- static int
- Operand_uimm8x2_decode (uint32 *valp)
- {
- unsigned uimm8x2_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8x2_0 = imm8_0 << 1;
- *valp = uimm8x2_0;
- return 0;
- }
- static int
- Operand_uimm8x2_encode (uint32 *valp)
- {
- unsigned imm8_0, uimm8x2_0;
- uimm8x2_0 = *valp;
- imm8_0 = ((uimm8x2_0 >> 1) & 0xff);
- *valp = imm8_0;
- return 0;
- }
- static int
- Operand_uimm8x4_decode (uint32 *valp)
- {
- unsigned uimm8x4_0, imm8_0;
- imm8_0 = *valp & 0xff;
- uimm8x4_0 = imm8_0 << 2;
- *valp = uimm8x4_0;
- return 0;
- }
- static int
- Operand_uimm8x4_encode (uint32 *valp)
- {
- unsigned imm8_0, uimm8x4_0;
- uimm8x4_0 = *valp;
- imm8_0 = ((uimm8x4_0 >> 2) & 0xff);
- *valp = imm8_0;
- return 0;
- }
- static int
- Operand_uimm4x16_decode (uint32 *valp)
- {
- unsigned uimm4x16_0, op2_0;
- op2_0 = *valp & 0xf;
- uimm4x16_0 = op2_0 << 4;
- *valp = uimm4x16_0;
- return 0;
- }
- static int
- Operand_uimm4x16_encode (uint32 *valp)
- {
- unsigned op2_0, uimm4x16_0;
- uimm4x16_0 = *valp;
- op2_0 = ((uimm4x16_0 >> 4) & 0xf);
- *valp = op2_0;
- return 0;
- }
- static int
- Operand_simm8_decode (uint32 *valp)
- {
- unsigned simm8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- simm8_0 = (imm8_0 ^ 0x80) - 0x80;
- *valp = simm8_0;
- return 0;
- }
- static int
- Operand_simm8_encode (uint32 *valp)
- {
- unsigned imm8_0, simm8_0;
- simm8_0 = *valp;
- imm8_0 = (simm8_0 & 0xff);
- *valp = imm8_0;
- return 0;
- }
- static int
- Operand_simm8x256_decode (uint32 *valp)
- {
- unsigned simm8x256_0, imm8_0;
- imm8_0 = *valp & 0xff;
- simm8x256_0 = ((imm8_0 ^ 0x80) - 0x80) << 8;
- *valp = simm8x256_0;
- return 0;
- }
- static int
- Operand_simm8x256_encode (uint32 *valp)
- {
- unsigned imm8_0, simm8x256_0;
- simm8x256_0 = *valp;
- imm8_0 = ((simm8x256_0 >> 8) & 0xff);
- *valp = imm8_0;
- return 0;
- }
- static int
- Operand_simm12b_decode (uint32 *valp)
- {
- unsigned simm12b_0, imm12b_0;
- imm12b_0 = *valp & 0xfff;
- simm12b_0 = (imm12b_0 ^ 0x800) - 0x800;
- *valp = simm12b_0;
- return 0;
- }
- static int
- Operand_simm12b_encode (uint32 *valp)
- {
- unsigned imm12b_0, simm12b_0;
- simm12b_0 = *valp;
- imm12b_0 = (simm12b_0 & 0xfff);
- *valp = imm12b_0;
- return 0;
- }
- static int
- Operand_msalp32_decode (uint32 *valp)
- {
- unsigned msalp32_0, sal_0;
- sal_0 = *valp & 0x1f;
- msalp32_0 = 0x20 - sal_0;
- *valp = msalp32_0;
- return 0;
- }
- static int
- Operand_msalp32_encode (uint32 *valp)
- {
- unsigned sal_0, msalp32_0;
- msalp32_0 = *valp;
- sal_0 = (0x20 - msalp32_0) & 0x1f;
- *valp = sal_0;
- return 0;
- }
- static int
- Operand_op2p1_decode (uint32 *valp)
- {
- unsigned op2p1_0, op2_0;
- op2_0 = *valp & 0xf;
- op2p1_0 = op2_0 + 0x1;
- *valp = op2p1_0;
- return 0;
- }
- static int
- Operand_op2p1_encode (uint32 *valp)
- {
- unsigned op2_0, op2p1_0;
- op2p1_0 = *valp;
- op2_0 = (op2p1_0 - 0x1) & 0xf;
- *valp = op2_0;
- return 0;
- }
- static int
- Operand_label8_decode (uint32 *valp)
- {
- unsigned label8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- label8_0 = 0x4 + ((imm8_0 ^ 0x80) - 0x80);
- *valp = label8_0;
- return 0;
- }
- static int
- Operand_label8_encode (uint32 *valp)
- {
- unsigned imm8_0, label8_0;
- label8_0 = *valp;
- imm8_0 = (label8_0 - 0x4) & 0xff;
- *valp = imm8_0;
- return 0;
- }
- static int
- Operand_label8_ator (uint32 *valp, uint32 pc)
- {
- *valp -= pc;
- return 0;
- }
- static int
- Operand_label8_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += pc;
- return 0;
- }
- static int
- Operand_ulabel8_decode (uint32 *valp)
- {
- unsigned ulabel8_0, imm8_0;
- imm8_0 = *valp & 0xff;
- ulabel8_0 = 0x4 + (((0) << 8) | imm8_0);
- *valp = ulabel8_0;
- return 0;
- }
- static int
- Operand_ulabel8_encode (uint32 *valp)
- {
- unsigned imm8_0, ulabel8_0;
- ulabel8_0 = *valp;
- imm8_0 = (ulabel8_0 - 0x4) & 0xff;
- *valp = imm8_0;
- return 0;
- }
- static int
- Operand_ulabel8_ator (uint32 *valp, uint32 pc)
- {
- *valp -= pc;
- return 0;
- }
- static int
- Operand_ulabel8_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += pc;
- return 0;
- }
- static int
- Operand_label12_decode (uint32 *valp)
- {
- unsigned label12_0, imm12_0;
- imm12_0 = *valp & 0xfff;
- label12_0 = 0x4 + ((imm12_0 ^ 0x800) - 0x800);
- *valp = label12_0;
- return 0;
- }
- static int
- Operand_label12_encode (uint32 *valp)
- {
- unsigned imm12_0, label12_0;
- label12_0 = *valp;
- imm12_0 = (label12_0 - 0x4) & 0xfff;
- *valp = imm12_0;
- return 0;
- }
- static int
- Operand_label12_ator (uint32 *valp, uint32 pc)
- {
- *valp -= pc;
- return 0;
- }
- static int
- Operand_label12_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += pc;
- return 0;
- }
- static int
- Operand_soffset_decode (uint32 *valp)
- {
- unsigned soffset_0, offset_0;
- offset_0 = *valp & 0x3ffff;
- soffset_0 = 0x4 + ((offset_0 ^ 0x20000) - 0x20000);
- *valp = soffset_0;
- return 0;
- }
- static int
- Operand_soffset_encode (uint32 *valp)
- {
- unsigned offset_0, soffset_0;
- soffset_0 = *valp;
- offset_0 = (soffset_0 - 0x4) & 0x3ffff;
- *valp = offset_0;
- return 0;
- }
- static int
- Operand_soffset_ator (uint32 *valp, uint32 pc)
- {
- *valp -= pc;
- return 0;
- }
- static int
- Operand_soffset_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += pc;
- return 0;
- }
- static int
- Operand_uimm16x4_decode (uint32 *valp)
- {
- unsigned uimm16x4_0, imm16_0;
- imm16_0 = *valp & 0xffff;
- uimm16x4_0 = (0xffff0000 | imm16_0) << 2;
- *valp = uimm16x4_0;
- return 0;
- }
- static int
- Operand_uimm16x4_encode (uint32 *valp)
- {
- unsigned imm16_0, uimm16x4_0;
- uimm16x4_0 = *valp;
- imm16_0 = (uimm16x4_0 >> 2) & 0xffff;
- *valp = imm16_0;
- return 0;
- }
- static int
- Operand_uimm16x4_ator (uint32 *valp, uint32 pc)
- {
- *valp -= ((pc + 3) & ~0x3);
- return 0;
- }
- static int
- Operand_uimm16x4_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += ((pc + 3) & ~0x3);
- return 0;
- }
- static int
- Operand_mx_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_mx_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3) != 0;
- return error;
- }
- static int
- Operand_my_decode (uint32 *valp)
- {
- *valp += 2;
- return 0;
- }
- static int
- Operand_my_encode (uint32 *valp)
- {
- int error;
- error = ((*valp & ~0x3) != 0) || ((*valp & 0x2) == 0);
- *valp = *valp & 1;
- return error;
- }
- static int
- Operand_mw_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_mw_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3) != 0;
- return error;
- }
- static int
- Operand_mr0_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_mr0_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3) != 0;
- return error;
- }
- static int
- Operand_mr1_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_mr1_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3) != 0;
- return error;
- }
- static int
- Operand_mr2_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_mr2_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3) != 0;
- return error;
- }
- static int
- Operand_mr3_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_mr3_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0x3) != 0;
- return error;
- }
- static int
- Operand_immt_decode (uint32 *valp)
- {
- unsigned immt_0, t_0;
- t_0 = *valp & 0xf;
- immt_0 = t_0;
- *valp = immt_0;
- return 0;
- }
- static int
- Operand_immt_encode (uint32 *valp)
- {
- unsigned t_0, immt_0;
- immt_0 = *valp;
- t_0 = immt_0 & 0xf;
- *valp = t_0;
- return 0;
- }
- static int
- Operand_imms_decode (uint32 *valp)
- {
- unsigned imms_0, s_0;
- s_0 = *valp & 0xf;
- imms_0 = s_0;
- *valp = imms_0;
- return 0;
- }
- static int
- Operand_imms_encode (uint32 *valp)
- {
- unsigned s_0, imms_0;
- imms_0 = *valp;
- s_0 = imms_0 & 0xf;
- *valp = s_0;
- return 0;
- }
- static int
- Operand_bt_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_bt_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static int
- Operand_bs_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_bs_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static int
- Operand_br_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_br_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static int
- Operand_bt2_decode (uint32 *valp)
- {
- *valp = *valp << 1;
- return 0;
- }
- static int
- Operand_bt2_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x7 << 1)) != 0;
- *valp = *valp >> 1;
- return error;
- }
- static int
- Operand_bs2_decode (uint32 *valp)
- {
- *valp = *valp << 1;
- return 0;
- }
- static int
- Operand_bs2_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x7 << 1)) != 0;
- *valp = *valp >> 1;
- return error;
- }
- static int
- Operand_br2_decode (uint32 *valp)
- {
- *valp = *valp << 1;
- return 0;
- }
- static int
- Operand_br2_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x7 << 1)) != 0;
- *valp = *valp >> 1;
- return error;
- }
- static int
- Operand_bt4_decode (uint32 *valp)
- {
- *valp = *valp << 2;
- return 0;
- }
- static int
- Operand_bt4_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x3 << 2)) != 0;
- *valp = *valp >> 2;
- return error;
- }
- static int
- Operand_bs4_decode (uint32 *valp)
- {
- *valp = *valp << 2;
- return 0;
- }
- static int
- Operand_bs4_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x3 << 2)) != 0;
- *valp = *valp >> 2;
- return error;
- }
- static int
- Operand_br4_decode (uint32 *valp)
- {
- *valp = *valp << 2;
- return 0;
- }
- static int
- Operand_br4_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x3 << 2)) != 0;
- *valp = *valp >> 2;
- return error;
- }
- static int
- Operand_bt8_decode (uint32 *valp)
- {
- *valp = *valp << 3;
- return 0;
- }
- static int
- Operand_bt8_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x1 << 3)) != 0;
- *valp = *valp >> 3;
- return error;
- }
- static int
- Operand_bs8_decode (uint32 *valp)
- {
- *valp = *valp << 3;
- return 0;
- }
- static int
- Operand_bs8_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x1 << 3)) != 0;
- *valp = *valp >> 3;
- return error;
- }
- static int
- Operand_br8_decode (uint32 *valp)
- {
- *valp = *valp << 3;
- return 0;
- }
- static int
- Operand_br8_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0x1 << 3)) != 0;
- *valp = *valp >> 3;
- return error;
- }
- static int
- Operand_bt16_decode (uint32 *valp)
- {
- *valp = *valp << 4;
- return 0;
- }
- static int
- Operand_bt16_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0 << 4)) != 0;
- *valp = *valp >> 4;
- return error;
- }
- static int
- Operand_bs16_decode (uint32 *valp)
- {
- *valp = *valp << 4;
- return 0;
- }
- static int
- Operand_bs16_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0 << 4)) != 0;
- *valp = *valp >> 4;
- return error;
- }
- static int
- Operand_br16_decode (uint32 *valp)
- {
- *valp = *valp << 4;
- return 0;
- }
- static int
- Operand_br16_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0 << 4)) != 0;
- *valp = *valp >> 4;
- return error;
- }
- static int
- Operand_brall_decode (uint32 *valp)
- {
- *valp = *valp << 4;
- return 0;
- }
- static int
- Operand_brall_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~(0 << 4)) != 0;
- *valp = *valp >> 4;
- return error;
- }
- static int
- Operand_tp7_decode (uint32 *valp)
- {
- unsigned tp7_0, t_0;
- t_0 = *valp & 0xf;
- tp7_0 = t_0 + 0x7;
- *valp = tp7_0;
- return 0;
- }
- static int
- Operand_tp7_encode (uint32 *valp)
- {
- unsigned t_0, tp7_0;
- tp7_0 = *valp;
- t_0 = (tp7_0 - 0x7) & 0xf;
- *valp = t_0;
- return 0;
- }
- static int
- Operand_xt_wbr15_label_decode (uint32 *valp)
- {
- unsigned xt_wbr15_label_0, xt_wbr15_imm_0;
- xt_wbr15_imm_0 = *valp & 0x7fff;
- xt_wbr15_label_0 = 0x4 + ((xt_wbr15_imm_0 ^ 0x4000) - 0x4000);
- *valp = xt_wbr15_label_0;
- return 0;
- }
- static int
- Operand_xt_wbr15_label_encode (uint32 *valp)
- {
- unsigned xt_wbr15_imm_0, xt_wbr15_label_0;
- xt_wbr15_label_0 = *valp;
- xt_wbr15_imm_0 = (xt_wbr15_label_0 - 0x4) & 0x7fff;
- *valp = xt_wbr15_imm_0;
- return 0;
- }
- static int
- Operand_xt_wbr15_label_ator (uint32 *valp, uint32 pc)
- {
- *valp -= pc;
- return 0;
- }
- static int
- Operand_xt_wbr15_label_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += pc;
- return 0;
- }
- static int
- Operand_xt_wbr18_label_decode (uint32 *valp)
- {
- unsigned xt_wbr18_label_0, xt_wbr18_imm_0;
- xt_wbr18_imm_0 = *valp & 0x3ffff;
- xt_wbr18_label_0 = 0x4 + ((xt_wbr18_imm_0 ^ 0x20000) - 0x20000);
- *valp = xt_wbr18_label_0;
- return 0;
- }
- static int
- Operand_xt_wbr18_label_encode (uint32 *valp)
- {
- unsigned xt_wbr18_imm_0, xt_wbr18_label_0;
- xt_wbr18_label_0 = *valp;
- xt_wbr18_imm_0 = (xt_wbr18_label_0 - 0x4) & 0x3ffff;
- *valp = xt_wbr18_imm_0;
- return 0;
- }
- static int
- Operand_xt_wbr18_label_ator (uint32 *valp, uint32 pc)
- {
- *valp -= pc;
- return 0;
- }
- static int
- Operand_xt_wbr18_label_rtoa (uint32 *valp, uint32 pc)
- {
- *valp += pc;
- return 0;
- }
- static int
- Operand_cimm8x4_decode (uint32 *valp)
- {
- unsigned cimm8x4_0, imm8_0;
- imm8_0 = *valp & 0xff;
- cimm8x4_0 = (imm8_0 << 2) | 0;
- *valp = cimm8x4_0;
- return 0;
- }
- static int
- Operand_cimm8x4_encode (uint32 *valp)
- {
- unsigned imm8_0, cimm8x4_0;
- cimm8x4_0 = *valp;
- imm8_0 = (cimm8x4_0 >> 2) & 0xff;
- *valp = imm8_0;
- return 0;
- }
- static int
- Operand_frr_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_frr_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static int
- Operand_frs_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_frs_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static int
- Operand_frt_decode (uint32 *valp ATTRIBUTE_UNUSED)
- {
- return 0;
- }
- static int
- Operand_frt_encode (uint32 *valp)
- {
- int error;
- error = (*valp & ~0xf) != 0;
- return error;
- }
- static xtensa_operand_internal operands[] = {
- { "soffsetx4", 10, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_soffsetx4_encode, Operand_soffsetx4_decode,
- Operand_soffsetx4_ator, Operand_soffsetx4_rtoa },
- { "uimm12x8", 3, -1, 0,
- 0,
- Operand_uimm12x8_encode, Operand_uimm12x8_decode,
- 0, 0 },
- { "simm4", 26, -1, 0,
- 0,
- Operand_simm4_encode, Operand_simm4_decode,
- 0, 0 },
- { "arr", 14, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_arr_encode, Operand_arr_decode,
- 0, 0 },
- { "ars", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_ars_encode, Operand_ars_decode,
- 0, 0 },
- { "*ars_invisible", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ars_encode, Operand_ars_decode,
- 0, 0 },
- { "art", 0, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_art_encode, Operand_art_decode,
- 0, 0 },
- { "ar0", 123, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar0_encode, Operand_ar0_decode,
- 0, 0 },
- { "ar4", 124, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar4_encode, Operand_ar4_decode,
- 0, 0 },
- { "ar8", 125, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar8_encode, Operand_ar8_decode,
- 0, 0 },
- { "ar12", 126, 0, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_ar12_encode, Operand_ar12_decode,
- 0, 0 },
- { "ars_entry", 5, 0, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_ars_entry_encode, Operand_ars_entry_decode,
- 0, 0 },
- { "immrx4", 14, -1, 0,
- 0,
- Operand_immrx4_encode, Operand_immrx4_decode,
- 0, 0 },
- { "lsi4x4", 14, -1, 0,
- 0,
- Operand_lsi4x4_encode, Operand_lsi4x4_decode,
- 0, 0 },
- { "simm7", 34, -1, 0,
- 0,
- Operand_simm7_encode, Operand_simm7_decode,
- 0, 0 },
- { "uimm6", 33, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_uimm6_encode, Operand_uimm6_decode,
- Operand_uimm6_ator, Operand_uimm6_rtoa },
- { "ai4const", 0, -1, 0,
- 0,
- Operand_ai4const_encode, Operand_ai4const_decode,
- 0, 0 },
- { "b4const", 14, -1, 0,
- 0,
- Operand_b4const_encode, Operand_b4const_decode,
- 0, 0 },
- { "b4constu", 14, -1, 0,
- 0,
- Operand_b4constu_encode, Operand_b4constu_decode,
- 0, 0 },
- { "uimm8", 4, -1, 0,
- 0,
- Operand_uimm8_encode, Operand_uimm8_decode,
- 0, 0 },
- { "uimm8x2", 4, -1, 0,
- 0,
- Operand_uimm8x2_encode, Operand_uimm8x2_decode,
- 0, 0 },
- { "uimm8x4", 4, -1, 0,
- 0,
- Operand_uimm8x4_encode, Operand_uimm8x4_decode,
- 0, 0 },
- { "uimm4x16", 13, -1, 0,
- 0,
- Operand_uimm4x16_encode, Operand_uimm4x16_decode,
- 0, 0 },
- { "simm8", 4, -1, 0,
- 0,
- Operand_simm8_encode, Operand_simm8_decode,
- 0, 0 },
- { "simm8x256", 4, -1, 0,
- 0,
- Operand_simm8x256_encode, Operand_simm8x256_decode,
- 0, 0 },
- { "simm12b", 6, -1, 0,
- 0,
- Operand_simm12b_encode, Operand_simm12b_decode,
- 0, 0 },
- { "msalp32", 18, -1, 0,
- 0,
- Operand_msalp32_encode, Operand_msalp32_decode,
- 0, 0 },
- { "op2p1", 13, -1, 0,
- 0,
- Operand_op2p1_encode, Operand_op2p1_decode,
- 0, 0 },
- { "label8", 4, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_label8_encode, Operand_label8_decode,
- Operand_label8_ator, Operand_label8_rtoa },
- { "ulabel8", 4, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_ulabel8_encode, Operand_ulabel8_decode,
- Operand_ulabel8_ator, Operand_ulabel8_rtoa },
- { "label12", 3, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_label12_encode, Operand_label12_decode,
- Operand_label12_ator, Operand_label12_rtoa },
- { "soffset", 10, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_soffset_encode, Operand_soffset_decode,
- Operand_soffset_ator, Operand_soffset_rtoa },
- { "uimm16x4", 7, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_uimm16x4_encode, Operand_uimm16x4_decode,
- Operand_uimm16x4_ator, Operand_uimm16x4_rtoa },
- { "mx", 43, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- Operand_mx_encode, Operand_mx_decode,
- 0, 0 },
- { "my", 42, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_UNKNOWN,
- Operand_my_encode, Operand_my_decode,
- 0, 0 },
- { "mw", 41, 1, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_mw_encode, Operand_mw_decode,
- 0, 0 },
- { "mr0", 127, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr0_encode, Operand_mr0_decode,
- 0, 0 },
- { "mr1", 128, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr1_encode, Operand_mr1_decode,
- 0, 0 },
- { "mr2", 129, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr2_encode, Operand_mr2_decode,
- 0, 0 },
- { "mr3", 130, 1, 1,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_mr3_encode, Operand_mr3_decode,
- 0, 0 },
- { "immt", 0, -1, 0,
- 0,
- Operand_immt_encode, Operand_immt_decode,
- 0, 0 },
- { "imms", 5, -1, 0,
- 0,
- Operand_imms_encode, Operand_imms_decode,
- 0, 0 },
- { "bt", 0, 2, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bt_encode, Operand_bt_decode,
- 0, 0 },
- { "bs", 5, 2, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bs_encode, Operand_bs_decode,
- 0, 0 },
- { "br", 14, 2, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_br_encode, Operand_br_decode,
- 0, 0 },
- { "bt2", 44, 2, 2,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bt2_encode, Operand_bt2_decode,
- 0, 0 },
- { "bs2", 45, 2, 2,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bs2_encode, Operand_bs2_decode,
- 0, 0 },
- { "br2", 46, 2, 2,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_br2_encode, Operand_br2_decode,
- 0, 0 },
- { "bt4", 47, 2, 4,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bt4_encode, Operand_bt4_decode,
- 0, 0 },
- { "bs4", 48, 2, 4,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bs4_encode, Operand_bs4_decode,
- 0, 0 },
- { "br4", 49, 2, 4,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_br4_encode, Operand_br4_decode,
- 0, 0 },
- { "bt8", 50, 2, 8,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bt8_encode, Operand_bt8_decode,
- 0, 0 },
- { "bs8", 51, 2, 8,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bs8_encode, Operand_bs8_decode,
- 0, 0 },
- { "br8", 52, 2, 8,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_br8_encode, Operand_br8_decode,
- 0, 0 },
- { "bt16", 131, 2, 16,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bt16_encode, Operand_bt16_decode,
- 0, 0 },
- { "bs16", 132, 2, 16,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_bs16_encode, Operand_bs16_decode,
- 0, 0 },
- { "br16", 133, 2, 16,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_br16_encode, Operand_br16_decode,
- 0, 0 },
- { "brall", 134, 2, 16,
- XTENSA_OPERAND_IS_REGISTER | XTENSA_OPERAND_IS_INVISIBLE,
- Operand_brall_encode, Operand_brall_decode,
- 0, 0 },
- { "tp7", 0, -1, 0,
- 0,
- Operand_tp7_encode, Operand_tp7_decode,
- 0, 0 },
- { "xt_wbr15_label", 53, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_xt_wbr15_label_encode, Operand_xt_wbr15_label_decode,
- Operand_xt_wbr15_label_ator, Operand_xt_wbr15_label_rtoa },
- { "xt_wbr18_label", 54, -1, 0,
- XTENSA_OPERAND_IS_PCRELATIVE,
- Operand_xt_wbr18_label_encode, Operand_xt_wbr18_label_decode,
- Operand_xt_wbr18_label_ator, Operand_xt_wbr18_label_rtoa },
- { "cimm8x4", 4, -1, 0,
- 0,
- Operand_cimm8x4_encode, Operand_cimm8x4_decode,
- 0, 0 },
- { "frr", 14, 3, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_frr_encode, Operand_frr_decode,
- 0, 0 },
- { "frs", 5, 3, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_frs_encode, Operand_frs_decode,
- 0, 0 },
- { "frt", 0, 3, 1,
- XTENSA_OPERAND_IS_REGISTER,
- Operand_frt_encode, Operand_frt_decode,
- 0, 0 },
- { "t", 0, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi4", 1, -1, 0, 0, 0, 0, 0, 0 },
- { "bbi", 2, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12", 3, -1, 0, 0, 0, 0, 0, 0 },
- { "imm8", 4, -1, 0, 0, 0, 0, 0, 0 },
- { "s", 5, -1, 0, 0, 0, 0, 0, 0 },
- { "imm12b", 6, -1, 0, 0, 0, 0, 0, 0 },
- { "imm16", 7, -1, 0, 0, 0, 0, 0, 0 },
- { "m", 8, -1, 0, 0, 0, 0, 0, 0 },
- { "n", 9, -1, 0, 0, 0, 0, 0, 0 },
- { "offset", 10, -1, 0, 0, 0, 0, 0, 0 },
- { "op0", 11, -1, 0, 0, 0, 0, 0, 0 },
- { "op1", 12, -1, 0, 0, 0, 0, 0, 0 },
- { "op2", 13, -1, 0, 0, 0, 0, 0, 0 },
- { "r", 14, -1, 0, 0, 0, 0, 0, 0 },
- { "sa4", 15, -1, 0, 0, 0, 0, 0, 0 },
- { "sae4", 16, -1, 0, 0, 0, 0, 0, 0 },
- { "sae", 17, -1, 0, 0, 0, 0, 0, 0 },
- { "sal", 18, -1, 0, 0, 0, 0, 0, 0 },
- { "sargt", 19, -1, 0, 0, 0, 0, 0, 0 },
- { "sas4", 20, -1, 0, 0, 0, 0, 0, 0 },
- { "sas", 21, -1, 0, 0, 0, 0, 0, 0 },
- { "sr", 22, -1, 0, 0, 0, 0, 0, 0 },
- { "st", 23, -1, 0, 0, 0, 0, 0, 0 },
- { "thi3", 24, -1, 0, 0, 0, 0, 0, 0 },
- { "imm4", 25, -1, 0, 0, 0, 0, 0, 0 },
- { "mn", 26, -1, 0, 0, 0, 0, 0, 0 },
- { "i", 27, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6lo", 28, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6hi", 29, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7lo", 30, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7hi", 31, -1, 0, 0, 0, 0, 0, 0 },
- { "z", 32, -1, 0, 0, 0, 0, 0, 0 },
- { "imm6", 33, -1, 0, 0, 0, 0, 0, 0 },
- { "imm7", 34, -1, 0, 0, 0, 0, 0, 0 },
- { "r3", 35, -1, 0, 0, 0, 0, 0, 0 },
- { "rbit2", 36, -1, 0, 0, 0, 0, 0, 0 },
- { "rhi", 37, -1, 0, 0, 0, 0, 0, 0 },
- { "t3", 38, -1, 0, 0, 0, 0, 0, 0 },
- { "tbit2", 39, -1, 0, 0, 0, 0, 0, 0 },
- { "tlo", 40, -1, 0, 0, 0, 0, 0, 0 },
- { "w", 41, -1, 0, 0, 0, 0, 0, 0 },
- { "y", 42, -1, 0, 0, 0, 0, 0, 0 },
- { "x", 43, -1, 0, 0, 0, 0, 0, 0 },
- { "t2", 44, -1, 0, 0, 0, 0, 0, 0 },
- { "s2", 45, -1, 0, 0, 0, 0, 0, 0 },
- { "r2", 46, -1, 0, 0, 0, 0, 0, 0 },
- { "t4", 47, -1, 0, 0, 0, 0, 0, 0 },
- { "s4", 48, -1, 0, 0, 0, 0, 0, 0 },
- { "r4", 49, -1, 0, 0, 0, 0, 0, 0 },
- { "t8", 50, -1, 0, 0, 0, 0, 0, 0 },
- { "s8", 51, -1, 0, 0, 0, 0, 0, 0 },
- { "r8", 52, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr15_imm", 53, -1, 0, 0, 0, 0, 0, 0 },
- { "xt_wbr18_imm", 54, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_xt_flix64_slot0_s3", 55, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld7", 56, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld8", 57, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld9", 58, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld11", 59, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld49xt_flix64_slot0", 60, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s4", 61, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld16", 62, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld19xt_flix64_slot1", 63, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld20xt_flix64_slot1", 64, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld21xt_flix64_slot1", 65, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld22xt_flix64_slot1", 66, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld23xt_flix64_slot1", 67, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld25xt_flix64_slot1", 68, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld26xt_flix64_slot1", 69, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld28xt_flix64_slot1", 70, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld30xt_flix64_slot1", 71, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld32xt_flix64_slot1", 72, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld33xt_flix64_slot1", 73, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld35xt_flix64_slot1", 74, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld51xt_flix64_slot1", 75, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld52xt_flix64_slot1", 76, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld53xt_flix64_slot1", 77, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld54xt_flix64_slot1", 78, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld57xt_flix64_slot1", 79, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld58xt_flix64_slot1", 80, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld60xt_flix64_slot1", 81, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld62xt_flix64_slot1", 82, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s5", 83, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld36xt_flix64_slot2", 84, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld37xt_flix64_slot2", 85, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld39xt_flix64_slot2", 86, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld41xt_flix64_slot2", 87, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld42xt_flix64_slot2", 88, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld44xt_flix64_slot2", 89, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld45xt_flix64_slot2", 90, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld47xt_flix64_slot2", 91, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld63xt_flix64_slot2", 92, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld64xt_flix64_slot2", 93, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld65xt_flix64_slot2", 94, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld66xt_flix64_slot2", 95, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld68xt_flix64_slot2", 96, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_s6", 97, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld70xt_flix64_slot3", 98, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld71", 99, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld72xt_flix64_slot3", 100, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld73xt_flix64_slot3", 101, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld74xt_flix64_slot3", 102, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld75xt_flix64_slot3", 103, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld76xt_flix64_slot3", 104, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld77xt_flix64_slot3", 105, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld78xt_flix64_slot3", 106, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld79xt_flix64_slot3", 107, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld80xt_flix64_slot3", 108, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld81xt_flix64_slot3", 109, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld82xt_flix64_slot3", 110, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld83xt_flix64_slot3", 111, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld84xt_flix64_slot3", 112, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld85xt_flix64_slot3", 113, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld86xt_flix64_slot3", 114, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld87xt_flix64_slot3", 115, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld88xt_flix64_slot3", 116, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld89xt_flix64_slot3", 117, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld90xt_flix64_slot3", 118, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld91xt_flix64_slot3", 119, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld92xt_flix64_slot3", 120, -1, 0, 0, 0, 0, 0, 0 },
- { "combined3e2c5767_fld93xt_flix64_slot3", 121, -1, 0, 0, 0, 0, 0, 0 },
- { "op0_xt_flix64_slot0", 122, -1, 0, 0, 0, 0, 0, 0 }
- };
- /* Iclass table. */
- static xtensa_arg_internal Iclass_xt_iclass_rfe_stateArgs[] = {
- { { STATE_PSRING }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_EPC1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rfde_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_call12_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 10 /* ar12 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_call12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_call8_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 9 /* ar8 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_call8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_call4_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 8 /* ar4 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_call4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_callx12_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 10 /* ar12 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_callx12_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_callx8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 9 /* ar8 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_callx8_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_callx4_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 8 /* ar4 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_callx4_stateArgs[] = {
- { { STATE_PSCALLINC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_entry_args[] = {
- { { 11 /* ars_entry */ }, 's' },
- { { 4 /* ars */ }, 'i' },
- { { 1 /* uimm12x8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_entry_stateArgs[] = {
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_movsp_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_movsp_stateArgs[] = {
- { { STATE_WindowBase }, 'i' },
- { { STATE_WindowStart }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rotw_args[] = {
- { { 2 /* simm4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rotw_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_retw_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_retw_stateArgs[] = {
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSWOE }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rfwou_stateArgs[] = {
- { { STATE_EPC1 }, 'i' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' },
- { { STATE_WindowStart }, 'm' },
- { { STATE_PSOWB }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l32e_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 12 /* immrx4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_s32e_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 12 /* immrx4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_s32e_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_windowbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowBase }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_windowstart_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_WindowStart }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_add_n_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_addi_n_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 16 /* ai4const */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bz6_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 15 /* uimm6 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_loadi4_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 13 /* lsi4x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mov_n_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_movi_n_args[] = {
- { { 4 /* ars */ }, 'o' },
- { { 14 /* simm7 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_retn_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_storei4_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 13 /* lsi4x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_rur_threadptr_args[] = {
- { { 3 /* arr */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_rur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'i' }
- };
- static xtensa_arg_internal Iclass_wur_threadptr_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_wur_threadptr_stateArgs[] = {
- { { STATE_THREADPTR }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_addi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 23 /* simm8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_addmi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 24 /* simm8x256 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_addsub_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bit_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bsi8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 17 /* b4const */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bsi8b_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 67 /* bbi */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bsi8u_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 18 /* b4constu */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bst8_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bsz12_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 30 /* label12 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_call0_args[] = {
- { { 0 /* soffsetx4 */ }, 'i' },
- { { 7 /* ar0 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_callx0_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 7 /* ar0 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_exti_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 82 /* sae */ }, 'i' },
- { { 27 /* op2p1 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_jump_args[] = {
- { { 31 /* soffset */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_jumpx_args[] = {
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l16ui_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l16si_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l32i_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l32r_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 32 /* uimm16x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l32r_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l8i_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 19 /* uimm8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_loop_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 29 /* ulabel8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_loop_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_loopz_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 29 /* ulabel8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_loopz_stateArgs[] = {
- { { STATE_LBEG }, 'o' },
- { { STATE_LEND }, 'o' },
- { { STATE_LCOUNT }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_movi_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 25 /* simm12b */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_movz_args[] = {
- { { 3 /* arr */ }, 'm' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_neg_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_return_args[] = {
- { { 5 /* *ars_invisible */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_s16i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 20 /* uimm8x2 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_s32i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_s8i_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 19 /* uimm8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sar_args[] = {
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sari_args[] = {
- { { 86 /* sas */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sari_stateArgs[] = {
- { { STATE_SAR }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_shifts_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_shifts_stateArgs[] = {
- { { STATE_SAR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_shiftst_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_shiftst_stateArgs[] = {
- { { STATE_SAR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_shiftt_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_shiftt_stateArgs[] = {
- { { STATE_SAR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_slli_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 26 /* msalp32 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_srai_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 84 /* sargt */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_srli_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 6 /* art */ }, 'i' },
- { { 70 /* s */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sync_stateArgs[] = {
- { { STATE_XTSYNC }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsil_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 70 /* s */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsil_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_lend_stateArgs[] = {
- { { STATE_LEND }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_lcount_stateArgs[] = {
- { { STATE_LCOUNT }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_lcount_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_LCOUNT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_lbeg_stateArgs[] = {
- { { STATE_LBEG }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'o' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_sar_stateArgs[] = {
- { { STATE_SAR }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'i' },
- { { STATE_LITBEN }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'o' },
- { { STATE_LITBEN }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_litbase_stateArgs[] = {
- { { STATE_LITBADDR }, 'm' },
- { { STATE_LITBEN }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_176_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_176_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_208_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_208_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'i' },
- { { STATE_PSCALLINC }, 'i' },
- { { STATE_PSOWB }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSUM }, 'i' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ps_stateArgs[] = {
- { { STATE_PSWOE }, 'm' },
- { { STATE_PSCALLINC }, 'm' },
- { { STATE_PSOWB }, 'm' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'm' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC1 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE1 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC2 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE2 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC3 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE3 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC4 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE4 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC5 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE5 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC6 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE6 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_epc7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPC7 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excsave7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCSAVE7 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS2 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS3 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps4_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS4 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps5_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS5 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps6_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS6 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_eps7_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EPS7 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_excvaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCVADDR }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_depc_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEPC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'i' },
- { { STATE_XTSYNC }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_exccause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_EXCCAUSE }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_misc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC0 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_misc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC1 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_misc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC2 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_misc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC2 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_misc2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC2 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_misc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC3 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_misc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC3 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_misc3_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_MISC3 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_prid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_vecbase_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_VECBASE }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_aa_stateArgs[] = {
- { { STATE_ACC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 34 /* my */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_ad_stateArgs[] = {
- { { STATE_ACC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_da_args[] = {
- { { 33 /* mx */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_da_stateArgs[] = {
- { { STATE_ACC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_args[] = {
- { { 33 /* mx */ }, 'i' },
- { { 34 /* my */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_dd_stateArgs[] = {
- { { STATE_ACC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16a_aa_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 34 /* my */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16a_ad_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_args[] = {
- { { 33 /* mx */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16a_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_args[] = {
- { { 33 /* mx */ }, 'i' },
- { { 34 /* my */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16a_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_args[] = {
- { { 35 /* mw */ }, 'o' },
- { { 4 /* ars */ }, 'm' },
- { { 33 /* mx */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16al_da_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_args[] = {
- { { 35 /* mw */ }, 'o' },
- { { 4 /* ars */ }, 'm' },
- { { 33 /* mx */ }, 'i' },
- { { 34 /* my */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16al_dd_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mac16_l_args[] = {
- { { 35 /* mw */ }, 'o' },
- { { 4 /* ars */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_mul16_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_m0_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 36 /* mr0 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_m0_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 36 /* mr0 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_m0_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 36 /* mr0 */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_m1_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 37 /* mr1 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_m1_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 37 /* mr1 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_m1_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 37 /* mr1 */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_m2_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 38 /* mr2 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_m2_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 38 /* mr2 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_m2_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 38 /* mr2 */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_m3_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 39 /* mr3 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_m3_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 39 /* mr3 */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_m3_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 39 /* mr3 */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_acclo_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_acchi_stateArgs[] = {
- { { STATE_ACC }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rfi_args[] = {
- { { 70 /* s */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rfi_stateArgs[] = {
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'm' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'm' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPC1 }, 'i' },
- { { STATE_EPC2 }, 'i' },
- { { STATE_EPC3 }, 'i' },
- { { STATE_EPC4 }, 'i' },
- { { STATE_EPC5 }, 'i' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_EPC7 }, 'i' },
- { { STATE_EPS2 }, 'i' },
- { { STATE_EPS3 }, 'i' },
- { { STATE_EPS4 }, 'i' },
- { { STATE_EPS5 }, 'i' },
- { { STATE_EPS6 }, 'i' },
- { { STATE_EPS7 }, 'i' },
- { { STATE_InOCDMode }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wait_args[] = {
- { { 70 /* s */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wait_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PSINTLEVEL }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_interrupt_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTERRUPT }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_intset_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_intclear_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_intenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INTENABLE }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_break_args[] = {
- { { 41 /* imms */ }, 'i' },
- { { 40 /* immt */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_break_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_break_n_args[] = {
- { { 41 /* imms */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_break_n_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSINTLEVEL }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC0 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKA1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'o' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dbreakc1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DBREAKC1 }, 'm' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA0 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreaka1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKA1 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ibreakenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_IBREAKENABLE }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'i' },
- { { STATE_DBNUM }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'o' },
- { { STATE_DBNUM }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_debugcause_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DEBUGCAUSE }, 'm' },
- { { STATE_DBNUM }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNT }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_icount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_ICOUNT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_icountlevel_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ICOUNTLEVEL }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DDR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_DDR }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rfdo_args[] = {
- { { 41 /* imms */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rfdo_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' },
- { { STATE_EPC6 }, 'i' },
- { { STATE_PSWOE }, 'o' },
- { { STATE_PSCALLINC }, 'o' },
- { { STATE_PSOWB }, 'o' },
- { { STATE_PSRING }, 'o' },
- { { STATE_PSUM }, 'o' },
- { { STATE_PSEXCM }, 'o' },
- { { STATE_PSINTLEVEL }, 'o' },
- { { STATE_EPS6 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rfdd_stateArgs[] = {
- { { STATE_InOCDMode }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_mmid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bbool1_args[] = {
- { { 44 /* br */ }, 'o' },
- { { 43 /* bs */ }, 'i' },
- { { 42 /* bt */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bbool4_args[] = {
- { { 42 /* bt */ }, 'o' },
- { { 49 /* bs4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bbool8_args[] = {
- { { 42 /* bt */ }, 'o' },
- { { 52 /* bs8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bbranch_args[] = {
- { { 43 /* bs */ }, 'i' },
- { { 28 /* label8 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_bmove_args[] = {
- { { 3 /* arr */ }, 'm' },
- { { 4 /* ars */ }, 'i' },
- { { 42 /* bt */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_RSR_BR_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 57 /* brall */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_WSR_BR_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 57 /* brall */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_XSR_BR_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 57 /* brall */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOUNT }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ccount_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' },
- { { STATE_CCOUNT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare0_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE0 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare1_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE1 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'o' },
- { { STATE_INTERRUPT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ccompare2_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CCOMPARE2 }, 'm' },
- { { STATE_INTERRUPT }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_icache_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_icache_lock_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 22 /* uimm4x16 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_icache_lock_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_icache_inv_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_icache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_licx_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_licx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sicx_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sicx_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_dcache_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 22 /* uimm4x16 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_dcache_ind_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_dcache_inv_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_dpf_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 22 /* uimm4x16 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_dcache_lock_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sdct_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sdct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_ldct_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_ldct_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'o' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_ptevaddr_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_PTBASE }, 'm' },
- { { STATE_EXCVADDR }, 'i' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_rasid_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'i' },
- { { STATE_ASID2 }, 'i' },
- { { STATE_ASID1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'o' },
- { { STATE_ASID2 }, 'o' },
- { { STATE_ASID1 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_rasid_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_ASID3 }, 'm' },
- { { STATE_ASID2 }, 'm' },
- { { STATE_ASID1 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_itlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_itlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_INSTPGSZID4 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_dtlbcfg_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_dtlbcfg_stateArgs[] = {
- { { STATE_XTSYNC }, 'o' },
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_DATAPGSZID4 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_idtlb_args[] = {
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_idtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rdtlb_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wdtlb_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wdtlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_XTSYNC }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_iitlb_args[] = {
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_iitlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_ritlb_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_ritlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_witlb_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_witlb_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_ldpte_stateArgs[] = {
- { { STATE_PTBASE }, 'i' },
- { { STATE_EXCVADDR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_hwwitlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_hwwdtlba_stateArgs[] = {
- { { STATE_EXCVADDR }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_cpenable_stateArgs[] = {
- { { STATE_PSEXCM }, 'i' },
- { { STATE_PSRING }, 'i' },
- { { STATE_CPENABLE }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_clamp_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 58 /* tp7 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_minmax_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_nsa_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_sx_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 58 /* tp7 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_l32ai_args[] = {
- { { 6 /* art */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_s32ri_args[] = {
- { { 6 /* art */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_s32c1i_args[] = {
- { { 6 /* art */ }, 'm' },
- { { 4 /* ars */ }, 'i' },
- { { 21 /* uimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_s32c1i_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' },
- { { STATE_SCOMPARE1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_args[] = {
- { { 6 /* art */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_rsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'o' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_args[] = {
- { { 6 /* art */ }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_xsr_scompare1_stateArgs[] = {
- { { STATE_SCOMPARE1 }, 'm' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_div_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_mul32_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_rur_fcr_args[] = {
- { { 3 /* arr */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_rur_fcr_stateArgs[] = {
- { { STATE_RoundMode }, 'i' },
- { { STATE_InvalidEnable }, 'i' },
- { { STATE_DivZeroEnable }, 'i' },
- { { STATE_OverflowEnable }, 'i' },
- { { STATE_UnderflowEnable }, 'i' },
- { { STATE_InexactEnable }, 'i' },
- { { STATE_FPreserved20 }, 'i' },
- { { STATE_FPreserved5 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_wur_fcr_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_wur_fcr_stateArgs[] = {
- { { STATE_RoundMode }, 'o' },
- { { STATE_InvalidEnable }, 'o' },
- { { STATE_DivZeroEnable }, 'o' },
- { { STATE_OverflowEnable }, 'o' },
- { { STATE_UnderflowEnable }, 'o' },
- { { STATE_InexactEnable }, 'o' },
- { { STATE_FPreserved20 }, 'o' },
- { { STATE_FPreserved5 }, 'o' },
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_rur_fsr_args[] = {
- { { 3 /* arr */ }, 'o' }
- };
- static xtensa_arg_internal Iclass_rur_fsr_stateArgs[] = {
- { { STATE_InvalidFlag }, 'i' },
- { { STATE_DivZeroFlag }, 'i' },
- { { STATE_OverflowFlag }, 'i' },
- { { STATE_UnderflowFlag }, 'i' },
- { { STATE_InexactFlag }, 'i' },
- { { STATE_FPreserved20a }, 'i' },
- { { STATE_FPreserved7 }, 'i' },
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_wur_fsr_args[] = {
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_wur_fsr_stateArgs[] = {
- { { STATE_InvalidFlag }, 'o' },
- { { STATE_DivZeroFlag }, 'o' },
- { { STATE_OverflowFlag }, 'o' },
- { { STATE_UnderflowFlag }, 'o' },
- { { STATE_InexactFlag }, 'o' },
- { { STATE_FPreserved20a }, 'o' },
- { { STATE_FPreserved7 }, 'o' },
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_args[] = {
- { { 62 /* frr */ }, 'o' },
- { { 63 /* frs */ }, 'i' },
- { { 64 /* frt */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_stateArgs[] = {
- { { STATE_RoundMode }, 'i' },
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_mac_args[] = {
- { { 62 /* frr */ }, 'm' },
- { { 63 /* frs */ }, 'i' },
- { { 64 /* frt */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_mac_stateArgs[] = {
- { { STATE_RoundMode }, 'i' },
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_cmov_args[] = {
- { { 62 /* frr */ }, 'm' },
- { { 63 /* frs */ }, 'i' },
- { { 42 /* bt */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_cmov_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_mov_args[] = {
- { { 62 /* frr */ }, 'm' },
- { { 63 /* frs */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_mov_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_mov2_args[] = {
- { { 62 /* frr */ }, 'o' },
- { { 63 /* frs */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_mov2_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_cmp_args[] = {
- { { 44 /* br */ }, 'o' },
- { { 63 /* frs */ }, 'i' },
- { { 64 /* frt */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_cmp_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_float_args[] = {
- { { 62 /* frr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 65 /* t */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_float_stateArgs[] = {
- { { STATE_RoundMode }, 'i' },
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_int_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 63 /* frs */ }, 'i' },
- { { 65 /* t */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_int_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_rfr_args[] = {
- { { 3 /* arr */ }, 'o' },
- { { 63 /* frs */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_rfr_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_wfr_args[] = {
- { { 62 /* frr */ }, 'o' },
- { { 4 /* ars */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_wfr_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_lsi_args[] = {
- { { 64 /* frt */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 61 /* cimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_lsi_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_lsiu_args[] = {
- { { 64 /* frt */ }, 'o' },
- { { 4 /* ars */ }, 'm' },
- { { 61 /* cimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_lsiu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_lsx_args[] = {
- { { 62 /* frr */ }, 'o' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_lsx_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_lsxu_args[] = {
- { { 62 /* frr */ }, 'o' },
- { { 4 /* ars */ }, 'm' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_lsxu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_ssi_args[] = {
- { { 64 /* frt */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 61 /* cimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_ssi_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_ssiu_args[] = {
- { { 64 /* frt */ }, 'i' },
- { { 4 /* ars */ }, 'm' },
- { { 61 /* cimm8x4 */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_ssiu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_ssx_args[] = {
- { { 62 /* frr */ }, 'i' },
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_ssx_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_ssxu_args[] = {
- { { 62 /* frr */ }, 'i' },
- { { 4 /* ars */ }, 'm' },
- { { 6 /* art */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_fp_ssxu_stateArgs[] = {
- { { STATE_CPENABLE }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wb18_0_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 60 /* xt_wbr18_label */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wb18_1_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 17 /* b4const */ }, 'i' },
- { { 60 /* xt_wbr18_label */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wb18_2_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 18 /* b4constu */ }, 'i' },
- { { 60 /* xt_wbr18_label */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wb18_3_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 67 /* bbi */ }, 'i' },
- { { 60 /* xt_wbr18_label */ }, 'i' }
- };
- static xtensa_arg_internal Iclass_xt_iclass_wb18_4_args[] = {
- { { 4 /* ars */ }, 'i' },
- { { 6 /* art */ }, 'i' },
- { { 60 /* xt_wbr18_label */ }, 'i' }
- };
- static xtensa_iclass_internal iclasses[] = {
- { 0, 0 /* xt_iclass_excw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_rfe */,
- 3, Iclass_xt_iclass_rfe_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfde */,
- 3, Iclass_xt_iclass_rfde_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_syscall */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_simcall */,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call12_args,
- 1, Iclass_xt_iclass_call12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call8_args,
- 1, Iclass_xt_iclass_call8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_call4_args,
- 1, Iclass_xt_iclass_call4_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx12_args,
- 1, Iclass_xt_iclass_callx12_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx8_args,
- 1, Iclass_xt_iclass_callx8_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_callx4_args,
- 1, Iclass_xt_iclass_callx4_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_entry_args,
- 5, Iclass_xt_iclass_entry_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movsp_args,
- 2, Iclass_xt_iclass_movsp_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rotw_args,
- 3, Iclass_xt_iclass_rotw_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_retw_args,
- 4, Iclass_xt_iclass_retw_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfwou */,
- 6, Iclass_xt_iclass_rfwou_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l32e_args,
- 2, Iclass_xt_iclass_l32e_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_s32e_args,
- 2, Iclass_xt_iclass_s32e_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowbase_args,
- 3, Iclass_xt_iclass_rsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowbase_args,
- 3, Iclass_xt_iclass_wsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowbase_args,
- 3, Iclass_xt_iclass_xsr_windowbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_windowstart_args,
- 3, Iclass_xt_iclass_rsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_windowstart_args,
- 3, Iclass_xt_iclass_wsr_windowstart_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_windowstart_args,
- 3, Iclass_xt_iclass_xsr_windowstart_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_add_n_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addi_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bz6_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill_n */,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_loadi4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_mov_n_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_movi_n_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nopn */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_retn_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_storei4_args,
- 0, 0, 0, 0 },
- { 1, Iclass_rur_threadptr_args,
- 1, Iclass_rur_threadptr_stateArgs, 0, 0 },
- { 1, Iclass_wur_threadptr_args,
- 1, Iclass_wur_threadptr_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_addi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addmi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_addsub_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bit_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8b_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bsi8u_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bst8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bsz12_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_call0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_callx0_args,
- 0, 0, 0, 0 },
- { 4, Iclass_xt_iclass_exti_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_ill */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jump_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_jumpx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16ui_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l16si_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_l32r_args,
- 2, Iclass_xt_iclass_l32r_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_l8i_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_loop_args,
- 3, Iclass_xt_iclass_loop_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_loopz_args,
- 3, Iclass_xt_iclass_loopz_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_movi_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_movz_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_neg_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_nop */,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_return_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s16i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32i_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s8i_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_sar_args,
- 1, Iclass_xt_iclass_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_sari_args,
- 1, Iclass_xt_iclass_sari_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shifts_args,
- 1, Iclass_xt_iclass_shifts_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_shiftst_args,
- 1, Iclass_xt_iclass_shiftst_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_shiftt_args,
- 1, Iclass_xt_iclass_shiftt_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_slli_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_srli_args,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_memw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_extw */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_isync */,
- 0, 0, 0, 0 },
- { 0, 0 /* xt_iclass_sync */,
- 1, Iclass_xt_iclass_sync_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rsil_args,
- 7, Iclass_xt_iclass_rsil_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lend_args,
- 1, Iclass_xt_iclass_rsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lend_args,
- 1, Iclass_xt_iclass_wsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lend_args,
- 1, Iclass_xt_iclass_xsr_lend_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lcount_args,
- 1, Iclass_xt_iclass_rsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lcount_args,
- 2, Iclass_xt_iclass_wsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lcount_args,
- 2, Iclass_xt_iclass_xsr_lcount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_lbeg_args,
- 1, Iclass_xt_iclass_rsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_lbeg_args,
- 1, Iclass_xt_iclass_wsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_lbeg_args,
- 1, Iclass_xt_iclass_xsr_lbeg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_sar_args,
- 1, Iclass_xt_iclass_rsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_sar_args,
- 2, Iclass_xt_iclass_wsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_sar_args,
- 1, Iclass_xt_iclass_xsr_sar_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_litbase_args,
- 2, Iclass_xt_iclass_rsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_litbase_args,
- 2, Iclass_xt_iclass_wsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_litbase_args,
- 2, Iclass_xt_iclass_xsr_litbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_176_args,
- 2, Iclass_xt_iclass_rsr_176_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_208_args,
- 2, Iclass_xt_iclass_rsr_208_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ps_args,
- 7, Iclass_xt_iclass_rsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ps_args,
- 7, Iclass_xt_iclass_wsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ps_args,
- 7, Iclass_xt_iclass_xsr_ps_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc1_args,
- 3, Iclass_xt_iclass_rsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc1_args,
- 3, Iclass_xt_iclass_wsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc1_args,
- 3, Iclass_xt_iclass_xsr_epc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave1_args,
- 3, Iclass_xt_iclass_rsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave1_args,
- 3, Iclass_xt_iclass_wsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave1_args,
- 3, Iclass_xt_iclass_xsr_excsave1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc2_args,
- 3, Iclass_xt_iclass_rsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc2_args,
- 3, Iclass_xt_iclass_wsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc2_args,
- 3, Iclass_xt_iclass_xsr_epc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave2_args,
- 3, Iclass_xt_iclass_rsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave2_args,
- 3, Iclass_xt_iclass_wsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave2_args,
- 3, Iclass_xt_iclass_xsr_excsave2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc3_args,
- 3, Iclass_xt_iclass_rsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc3_args,
- 3, Iclass_xt_iclass_wsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc3_args,
- 3, Iclass_xt_iclass_xsr_epc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave3_args,
- 3, Iclass_xt_iclass_rsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave3_args,
- 3, Iclass_xt_iclass_wsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave3_args,
- 3, Iclass_xt_iclass_xsr_excsave3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc4_args,
- 3, Iclass_xt_iclass_rsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc4_args,
- 3, Iclass_xt_iclass_wsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc4_args,
- 3, Iclass_xt_iclass_xsr_epc4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave4_args,
- 3, Iclass_xt_iclass_rsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave4_args,
- 3, Iclass_xt_iclass_wsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave4_args,
- 3, Iclass_xt_iclass_xsr_excsave4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc5_args,
- 3, Iclass_xt_iclass_rsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc5_args,
- 3, Iclass_xt_iclass_wsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc5_args,
- 3, Iclass_xt_iclass_xsr_epc5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave5_args,
- 3, Iclass_xt_iclass_rsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave5_args,
- 3, Iclass_xt_iclass_wsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave5_args,
- 3, Iclass_xt_iclass_xsr_excsave5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc6_args,
- 3, Iclass_xt_iclass_rsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc6_args,
- 3, Iclass_xt_iclass_wsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc6_args,
- 3, Iclass_xt_iclass_xsr_epc6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave6_args,
- 3, Iclass_xt_iclass_rsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave6_args,
- 3, Iclass_xt_iclass_wsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave6_args,
- 3, Iclass_xt_iclass_xsr_excsave6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_epc7_args,
- 3, Iclass_xt_iclass_rsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_epc7_args,
- 3, Iclass_xt_iclass_wsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_epc7_args,
- 3, Iclass_xt_iclass_xsr_epc7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excsave7_args,
- 3, Iclass_xt_iclass_rsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excsave7_args,
- 3, Iclass_xt_iclass_wsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excsave7_args,
- 3, Iclass_xt_iclass_xsr_excsave7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps2_args,
- 3, Iclass_xt_iclass_rsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps2_args,
- 3, Iclass_xt_iclass_wsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps2_args,
- 3, Iclass_xt_iclass_xsr_eps2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps3_args,
- 3, Iclass_xt_iclass_rsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps3_args,
- 3, Iclass_xt_iclass_wsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps3_args,
- 3, Iclass_xt_iclass_xsr_eps3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps4_args,
- 3, Iclass_xt_iclass_rsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps4_args,
- 3, Iclass_xt_iclass_wsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps4_args,
- 3, Iclass_xt_iclass_xsr_eps4_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps5_args,
- 3, Iclass_xt_iclass_rsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps5_args,
- 3, Iclass_xt_iclass_wsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps5_args,
- 3, Iclass_xt_iclass_xsr_eps5_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps6_args,
- 3, Iclass_xt_iclass_rsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps6_args,
- 3, Iclass_xt_iclass_wsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps6_args,
- 3, Iclass_xt_iclass_xsr_eps6_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_eps7_args,
- 3, Iclass_xt_iclass_rsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_eps7_args,
- 3, Iclass_xt_iclass_wsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_eps7_args,
- 3, Iclass_xt_iclass_xsr_eps7_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_excvaddr_args,
- 3, Iclass_xt_iclass_rsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_excvaddr_args,
- 3, Iclass_xt_iclass_wsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_excvaddr_args,
- 3, Iclass_xt_iclass_xsr_excvaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_depc_args,
- 3, Iclass_xt_iclass_rsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_depc_args,
- 3, Iclass_xt_iclass_wsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_depc_args,
- 3, Iclass_xt_iclass_xsr_depc_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_exccause_args,
- 4, Iclass_xt_iclass_rsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_exccause_args,
- 3, Iclass_xt_iclass_wsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_exccause_args,
- 3, Iclass_xt_iclass_xsr_exccause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc0_args,
- 3, Iclass_xt_iclass_rsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc0_args,
- 3, Iclass_xt_iclass_wsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc0_args,
- 3, Iclass_xt_iclass_xsr_misc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc1_args,
- 3, Iclass_xt_iclass_rsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc1_args,
- 3, Iclass_xt_iclass_wsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc1_args,
- 3, Iclass_xt_iclass_xsr_misc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc2_args,
- 3, Iclass_xt_iclass_rsr_misc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc2_args,
- 3, Iclass_xt_iclass_wsr_misc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc2_args,
- 3, Iclass_xt_iclass_xsr_misc2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_misc3_args,
- 3, Iclass_xt_iclass_rsr_misc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_misc3_args,
- 3, Iclass_xt_iclass_wsr_misc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_misc3_args,
- 3, Iclass_xt_iclass_xsr_misc3_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_prid_args,
- 2, Iclass_xt_iclass_rsr_prid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_vecbase_args,
- 3, Iclass_xt_iclass_rsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_vecbase_args,
- 3, Iclass_xt_iclass_wsr_vecbase_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_vecbase_args,
- 3, Iclass_xt_iclass_xsr_vecbase_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_aa_args,
- 1, Iclass_xt_iclass_mac16_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_ad_args,
- 1, Iclass_xt_iclass_mac16_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_da_args,
- 1, Iclass_xt_iclass_mac16_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_dd_args,
- 1, Iclass_xt_iclass_mac16_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_aa_args,
- 1, Iclass_xt_iclass_mac16a_aa_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_ad_args,
- 1, Iclass_xt_iclass_mac16a_ad_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_da_args,
- 1, Iclass_xt_iclass_mac16a_da_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16a_dd_args,
- 1, Iclass_xt_iclass_mac16a_dd_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_da_args,
- 1, Iclass_xt_iclass_mac16al_da_stateArgs, 0, 0 },
- { 4, Iclass_xt_iclass_mac16al_dd_args,
- 1, Iclass_xt_iclass_mac16al_dd_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_mac16_l_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_mul16_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m0_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m2_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_rsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_wsr_m3_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_xsr_m3_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acclo_args,
- 1, Iclass_xt_iclass_rsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acclo_args,
- 1, Iclass_xt_iclass_wsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acclo_args,
- 1, Iclass_xt_iclass_xsr_acclo_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_acchi_args,
- 1, Iclass_xt_iclass_rsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_acchi_args,
- 1, Iclass_xt_iclass_wsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_acchi_args,
- 1, Iclass_xt_iclass_xsr_acchi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfi_args,
- 21, Iclass_xt_iclass_rfi_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wait_args,
- 3, Iclass_xt_iclass_wait_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_interrupt_args,
- 3, Iclass_xt_iclass_rsr_interrupt_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intset_args,
- 4, Iclass_xt_iclass_wsr_intset_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intclear_args,
- 4, Iclass_xt_iclass_wsr_intclear_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_intenable_args,
- 3, Iclass_xt_iclass_rsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_intenable_args,
- 3, Iclass_xt_iclass_wsr_intenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_intenable_args,
- 3, Iclass_xt_iclass_xsr_intenable_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_break_args,
- 2, Iclass_xt_iclass_break_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_break_n_args,
- 2, Iclass_xt_iclass_break_n_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka0_args,
- 3, Iclass_xt_iclass_rsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka0_args,
- 4, Iclass_xt_iclass_wsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka0_args,
- 4, Iclass_xt_iclass_xsr_dbreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc0_args,
- 3, Iclass_xt_iclass_rsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc0_args,
- 4, Iclass_xt_iclass_wsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc0_args,
- 4, Iclass_xt_iclass_xsr_dbreakc0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreaka1_args,
- 3, Iclass_xt_iclass_rsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreaka1_args,
- 4, Iclass_xt_iclass_wsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreaka1_args,
- 4, Iclass_xt_iclass_xsr_dbreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dbreakc1_args,
- 3, Iclass_xt_iclass_rsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dbreakc1_args,
- 4, Iclass_xt_iclass_wsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dbreakc1_args,
- 4, Iclass_xt_iclass_xsr_dbreakc1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka0_args,
- 3, Iclass_xt_iclass_rsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka0_args,
- 3, Iclass_xt_iclass_wsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka0_args,
- 3, Iclass_xt_iclass_xsr_ibreaka0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreaka1_args,
- 3, Iclass_xt_iclass_rsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreaka1_args,
- 3, Iclass_xt_iclass_wsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreaka1_args,
- 3, Iclass_xt_iclass_xsr_ibreaka1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ibreakenable_args,
- 3, Iclass_xt_iclass_rsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ibreakenable_args,
- 3, Iclass_xt_iclass_wsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ibreakenable_args,
- 3, Iclass_xt_iclass_xsr_ibreakenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_debugcause_args,
- 4, Iclass_xt_iclass_rsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_debugcause_args,
- 4, Iclass_xt_iclass_wsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_debugcause_args,
- 4, Iclass_xt_iclass_xsr_debugcause_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icount_args,
- 3, Iclass_xt_iclass_rsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icount_args,
- 4, Iclass_xt_iclass_wsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icount_args,
- 4, Iclass_xt_iclass_xsr_icount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_icountlevel_args,
- 3, Iclass_xt_iclass_rsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_icountlevel_args,
- 3, Iclass_xt_iclass_wsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_icountlevel_args,
- 3, Iclass_xt_iclass_xsr_icountlevel_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ddr_args,
- 3, Iclass_xt_iclass_rsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ddr_args,
- 4, Iclass_xt_iclass_wsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ddr_args,
- 4, Iclass_xt_iclass_xsr_ddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rfdo_args,
- 10, Iclass_xt_iclass_rfdo_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_rfdd */,
- 1, Iclass_xt_iclass_rfdd_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_mmid_args,
- 3, Iclass_xt_iclass_wsr_mmid_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_bbool1_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbool4_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbool8_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_bbranch_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_bmove_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_RSR_BR_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_WSR_BR_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_XSR_BR_args,
- 0, 0, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccount_args,
- 3, Iclass_xt_iclass_rsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccount_args,
- 4, Iclass_xt_iclass_wsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccount_args,
- 4, Iclass_xt_iclass_xsr_ccount_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare0_args,
- 3, Iclass_xt_iclass_rsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare0_args,
- 4, Iclass_xt_iclass_wsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare0_args,
- 4, Iclass_xt_iclass_xsr_ccompare0_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare1_args,
- 3, Iclass_xt_iclass_rsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare1_args,
- 4, Iclass_xt_iclass_wsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare1_args,
- 4, Iclass_xt_iclass_xsr_ccompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ccompare2_args,
- 3, Iclass_xt_iclass_rsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ccompare2_args,
- 4, Iclass_xt_iclass_wsr_ccompare2_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ccompare2_args,
- 4, Iclass_xt_iclass_xsr_ccompare2_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_icache_lock_args,
- 2, Iclass_xt_iclass_icache_lock_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_icache_inv_args,
- 2, Iclass_xt_iclass_icache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_licx_args,
- 2, Iclass_xt_iclass_licx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sicx_args,
- 2, Iclass_xt_iclass_sicx_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_ind_args,
- 2, Iclass_xt_iclass_dcache_ind_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_inv_args,
- 2, Iclass_xt_iclass_dcache_inv_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_dpf_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_dcache_lock_args,
- 2, Iclass_xt_iclass_dcache_lock_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_sdct_args,
- 2, Iclass_xt_iclass_sdct_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ldct_args,
- 2, Iclass_xt_iclass_ldct_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_ptevaddr_args,
- 4, Iclass_xt_iclass_wsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_ptevaddr_args,
- 4, Iclass_xt_iclass_rsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_ptevaddr_args,
- 5, Iclass_xt_iclass_xsr_ptevaddr_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_rasid_args,
- 5, Iclass_xt_iclass_rsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_rasid_args,
- 6, Iclass_xt_iclass_wsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_rasid_args,
- 6, Iclass_xt_iclass_xsr_rasid_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_itlbcfg_args,
- 3, Iclass_xt_iclass_rsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_itlbcfg_args,
- 4, Iclass_xt_iclass_wsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_itlbcfg_args,
- 4, Iclass_xt_iclass_xsr_itlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_dtlbcfg_args,
- 3, Iclass_xt_iclass_rsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_dtlbcfg_args,
- 4, Iclass_xt_iclass_wsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_dtlbcfg_args,
- 4, Iclass_xt_iclass_xsr_dtlbcfg_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_idtlb_args,
- 3, Iclass_xt_iclass_idtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_rdtlb_args,
- 2, Iclass_xt_iclass_rdtlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_wdtlb_args,
- 3, Iclass_xt_iclass_wdtlb_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_iitlb_args,
- 2, Iclass_xt_iclass_iitlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_ritlb_args,
- 2, Iclass_xt_iclass_ritlb_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_witlb_args,
- 2, Iclass_xt_iclass_witlb_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_ldpte */,
- 2, Iclass_xt_iclass_ldpte_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwitlba */,
- 1, Iclass_xt_iclass_hwwitlba_stateArgs, 0, 0 },
- { 0, 0 /* xt_iclass_hwwdtlba */,
- 1, Iclass_xt_iclass_hwwdtlba_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_cpenable_args,
- 3, Iclass_xt_iclass_rsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_cpenable_args,
- 3, Iclass_xt_iclass_wsr_cpenable_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_cpenable_args,
- 3, Iclass_xt_iclass_xsr_cpenable_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_clamp_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_minmax_args,
- 0, 0, 0, 0 },
- { 2, Iclass_xt_iclass_nsa_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_sx_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_l32ai_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32ri_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_s32c1i_args,
- 2, Iclass_xt_iclass_s32c1i_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_rsr_scompare1_args,
- 1, Iclass_xt_iclass_rsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_wsr_scompare1_args,
- 1, Iclass_xt_iclass_wsr_scompare1_stateArgs, 0, 0 },
- { 1, Iclass_xt_iclass_xsr_scompare1_args,
- 1, Iclass_xt_iclass_xsr_scompare1_stateArgs, 0, 0 },
- { 3, Iclass_xt_iclass_div_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_mul32_args,
- 0, 0, 0, 0 },
- { 1, Iclass_rur_fcr_args,
- 9, Iclass_rur_fcr_stateArgs, 0, 0 },
- { 1, Iclass_wur_fcr_args,
- 9, Iclass_wur_fcr_stateArgs, 0, 0 },
- { 1, Iclass_rur_fsr_args,
- 8, Iclass_rur_fsr_stateArgs, 0, 0 },
- { 1, Iclass_wur_fsr_args,
- 8, Iclass_wur_fsr_stateArgs, 0, 0 },
- { 3, Iclass_fp_args,
- 2, Iclass_fp_stateArgs, 0, 0 },
- { 3, Iclass_fp_mac_args,
- 2, Iclass_fp_mac_stateArgs, 0, 0 },
- { 3, Iclass_fp_cmov_args,
- 1, Iclass_fp_cmov_stateArgs, 0, 0 },
- { 3, Iclass_fp_mov_args,
- 1, Iclass_fp_mov_stateArgs, 0, 0 },
- { 2, Iclass_fp_mov2_args,
- 1, Iclass_fp_mov2_stateArgs, 0, 0 },
- { 3, Iclass_fp_cmp_args,
- 1, Iclass_fp_cmp_stateArgs, 0, 0 },
- { 3, Iclass_fp_float_args,
- 2, Iclass_fp_float_stateArgs, 0, 0 },
- { 3, Iclass_fp_int_args,
- 1, Iclass_fp_int_stateArgs, 0, 0 },
- { 2, Iclass_fp_rfr_args,
- 1, Iclass_fp_rfr_stateArgs, 0, 0 },
- { 2, Iclass_fp_wfr_args,
- 1, Iclass_fp_wfr_stateArgs, 0, 0 },
- { 3, Iclass_fp_lsi_args,
- 1, Iclass_fp_lsi_stateArgs, 0, 0 },
- { 3, Iclass_fp_lsiu_args,
- 1, Iclass_fp_lsiu_stateArgs, 0, 0 },
- { 3, Iclass_fp_lsx_args,
- 1, Iclass_fp_lsx_stateArgs, 0, 0 },
- { 3, Iclass_fp_lsxu_args,
- 1, Iclass_fp_lsxu_stateArgs, 0, 0 },
- { 3, Iclass_fp_ssi_args,
- 1, Iclass_fp_ssi_stateArgs, 0, 0 },
- { 3, Iclass_fp_ssiu_args,
- 1, Iclass_fp_ssiu_stateArgs, 0, 0 },
- { 3, Iclass_fp_ssx_args,
- 1, Iclass_fp_ssx_stateArgs, 0, 0 },
- { 3, Iclass_fp_ssxu_args,
- 1, Iclass_fp_ssxu_stateArgs, 0, 0 },
- { 2, Iclass_xt_iclass_wb18_0_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_wb18_1_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_wb18_2_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_wb18_3_args,
- 0, 0, 0, 0 },
- { 3, Iclass_xt_iclass_wb18_4_args,
- 0, 0, 0, 0 }
- };
- /* Opcode encodings. */
- static void
- Opcode_excw_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2080;
- }
- static void
- Opcode_rfe_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3000;
- }
- static void
- Opcode_rfde_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3200;
- }
- static void
- Opcode_syscall_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5000;
- }
- static void
- Opcode_simcall_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5100;
- }
- static void
- Opcode_call12_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x35;
- }
- static void
- Opcode_call8_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x25;
- }
- static void
- Opcode_call4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x15;
- }
- static void
- Opcode_callx12_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf0;
- }
- static void
- Opcode_callx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe0;
- }
- static void
- Opcode_callx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd0;
- }
- static void
- Opcode_entry_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x36;
- }
- static void
- Opcode_movsp_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1000;
- }
- static void
- Opcode_rotw_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x408000;
- }
- static void
- Opcode_retw_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x90;
- }
- static void
- Opcode_retw_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf01d;
- }
- static void
- Opcode_rfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3400;
- }
- static void
- Opcode_rfwu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3500;
- }
- static void
- Opcode_l32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x90000;
- }
- static void
- Opcode_s32e_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x490000;
- }
- static void
- Opcode_rsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x34800;
- }
- static void
- Opcode_wsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x134800;
- }
- static void
- Opcode_xsr_windowbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x614800;
- }
- static void
- Opcode_rsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x34900;
- }
- static void
- Opcode_wsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x134900;
- }
- static void
- Opcode_xsr_windowstart_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x614900;
- }
- static void
- Opcode_add_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa;
- }
- static void
- Opcode_addi_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb;
- }
- static void
- Opcode_addi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3000;
- }
- static void
- Opcode_beqz_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8c;
- }
- static void
- Opcode_bnez_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xcc;
- }
- static void
- Opcode_ill_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf06d;
- }
- static void
- Opcode_l32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8;
- }
- static void
- Opcode_mov_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd;
- }
- static void
- Opcode_mov_n_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6000;
- }
- static void
- Opcode_mov_n_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa3000;
- }
- static void
- Opcode_mov_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc080;
- }
- static void
- Opcode_movi_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc;
- }
- static void
- Opcode_movi_n_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc000;
- }
- static void
- Opcode_nop_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf03d;
- }
- static void
- Opcode_ret_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf00d;
- }
- static void
- Opcode_s32i_n_Slot_inst16a_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9;
- }
- static void
- Opcode_rur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe30e70;
- }
- static void
- Opcode_wur_threadptr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf3e700;
- }
- static void
- Opcode_addi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc002;
- }
- static void
- Opcode_addi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x60000;
- }
- static void
- Opcode_addi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200c00;
- }
- static void
- Opcode_addmi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd002;
- }
- static void
- Opcode_addmi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x70000;
- }
- static void
- Opcode_addmi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200d00;
- }
- static void
- Opcode_add_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x800000;
- }
- static void
- Opcode_add_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x92000;
- }
- static void
- Opcode_add_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2000;
- }
- static void
- Opcode_add_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x80000;
- }
- static void
- Opcode_sub_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc00000;
- }
- static void
- Opcode_sub_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa8000;
- }
- static void
- Opcode_sub_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa000;
- }
- static void
- Opcode_sub_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc0000;
- }
- static void
- Opcode_addx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x900000;
- }
- static void
- Opcode_addx2_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x94000;
- }
- static void
- Opcode_addx2_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4000;
- }
- static void
- Opcode_addx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x90000;
- }
- static void
- Opcode_addx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa00000;
- }
- static void
- Opcode_addx4_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x98000;
- }
- static void
- Opcode_addx4_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5000;
- }
- static void
- Opcode_addx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa0000;
- }
- static void
- Opcode_addx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb00000;
- }
- static void
- Opcode_addx8_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x93000;
- }
- static void
- Opcode_addx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb0000;
- }
- static void
- Opcode_subx2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd00000;
- }
- static void
- Opcode_subx2_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd0000;
- }
- static void
- Opcode_subx4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe00000;
- }
- static void
- Opcode_subx4_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe0000;
- }
- static void
- Opcode_subx8_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf00000;
- }
- static void
- Opcode_subx8_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf0000;
- }
- static void
- Opcode_and_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x100000;
- }
- static void
- Opcode_and_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x95000;
- }
- static void
- Opcode_and_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6000;
- }
- static void
- Opcode_and_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x10000;
- }
- static void
- Opcode_or_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200000;
- }
- static void
- Opcode_or_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9e000;
- }
- static void
- Opcode_or_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7000;
- }
- static void
- Opcode_or_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x20000;
- }
- static void
- Opcode_xor_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x300000;
- }
- static void
- Opcode_xor_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb0000;
- }
- static void
- Opcode_xor_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb000;
- }
- static void
- Opcode_xor_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30000;
- }
- static void
- Opcode_beqi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x26;
- }
- static void
- Opcode_bnei_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x66;
- }
- static void
- Opcode_bgei_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe6;
- }
- static void
- Opcode_blti_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa6;
- }
- static void
- Opcode_bbci_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6007;
- }
- static void
- Opcode_bbsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe007;
- }
- static void
- Opcode_bgeui_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf6;
- }
- static void
- Opcode_bltui_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb6;
- }
- static void
- Opcode_beq_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1007;
- }
- static void
- Opcode_bne_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9007;
- }
- static void
- Opcode_bge_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa007;
- }
- static void
- Opcode_blt_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2007;
- }
- static void
- Opcode_bgeu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb007;
- }
- static void
- Opcode_bltu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3007;
- }
- static void
- Opcode_bany_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8007;
- }
- static void
- Opcode_bnone_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7;
- }
- static void
- Opcode_ball_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4007;
- }
- static void
- Opcode_bnall_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc007;
- }
- static void
- Opcode_bbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5007;
- }
- static void
- Opcode_bbs_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd007;
- }
- static void
- Opcode_beqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x16;
- }
- static void
- Opcode_bnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x56;
- }
- static void
- Opcode_bgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd6;
- }
- static void
- Opcode_bltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x96;
- }
- static void
- Opcode_call0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5;
- }
- static void
- Opcode_callx0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc0;
- }
- static void
- Opcode_extui_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40000;
- }
- static void
- Opcode_extui_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40000;
- }
- static void
- Opcode_extui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4000;
- }
- static void
- Opcode_ill_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0;
- }
- static void
- Opcode_j_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6;
- }
- static void
- Opcode_j_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc0000;
- }
- static void
- Opcode_jx_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa0;
- }
- static void
- Opcode_jx_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa3010;
- }
- static void
- Opcode_l16ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1002;
- }
- static void
- Opcode_l16ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200100;
- }
- static void
- Opcode_l16si_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9002;
- }
- static void
- Opcode_l16si_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200900;
- }
- static void
- Opcode_l32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2002;
- }
- static void
- Opcode_l32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200200;
- }
- static void
- Opcode_l32r_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1;
- }
- static void
- Opcode_l32r_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x100000;
- }
- static void
- Opcode_l8ui_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2;
- }
- static void
- Opcode_l8ui_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200000;
- }
- static void
- Opcode_loop_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8076;
- }
- static void
- Opcode_loopnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9076;
- }
- static void
- Opcode_loopgtz_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa076;
- }
- static void
- Opcode_movi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa002;
- }
- static void
- Opcode_movi_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x80000;
- }
- static void
- Opcode_movi_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200a00;
- }
- static void
- Opcode_moveqz_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x830000;
- }
- static void
- Opcode_moveqz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x96000;
- }
- static void
- Opcode_moveqz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x83000;
- }
- static void
- Opcode_movnez_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x930000;
- }
- static void
- Opcode_movnez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9a000;
- }
- static void
- Opcode_movnez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x93000;
- }
- static void
- Opcode_movltz_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa30000;
- }
- static void
- Opcode_movltz_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x99000;
- }
- static void
- Opcode_movltz_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa3000;
- }
- static void
- Opcode_movgez_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb30000;
- }
- static void
- Opcode_movgez_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x97000;
- }
- static void
- Opcode_movgez_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb3000;
- }
- static void
- Opcode_neg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x600000;
- }
- static void
- Opcode_neg_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa5000;
- }
- static void
- Opcode_neg_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd100;
- }
- static void
- Opcode_neg_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x60000;
- }
- static void
- Opcode_abs_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x600100;
- }
- static void
- Opcode_abs_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd000;
- }
- static void
- Opcode_abs_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x60010;
- }
- static void
- Opcode_nop_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x20f0;
- }
- static void
- Opcode_nop_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa3040;
- }
- static void
- Opcode_nop_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc090;
- }
- static void
- Opcode_nop_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc8000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_nop_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x20f;
- }
- static void
- Opcode_ret_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x80;
- }
- static void
- Opcode_s16i_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5002;
- }
- static void
- Opcode_s16i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200500;
- }
- static void
- Opcode_s32i_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6002;
- }
- static void
- Opcode_s32i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200600;
- }
- static void
- Opcode_s8i_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4002;
- }
- static void
- Opcode_s8i_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x200400;
- }
- static void
- Opcode_ssr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x400000;
- }
- static void
- Opcode_ssr_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40000;
- }
- static void
- Opcode_ssl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x401000;
- }
- static void
- Opcode_ssl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa3020;
- }
- static void
- Opcode_ssl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40100;
- }
- static void
- Opcode_ssa8l_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x402000;
- }
- static void
- Opcode_ssa8l_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40200;
- }
- static void
- Opcode_ssa8b_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x403000;
- }
- static void
- Opcode_ssa8b_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40300;
- }
- static void
- Opcode_ssai_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x404000;
- }
- static void
- Opcode_ssai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40400;
- }
- static void
- Opcode_sll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa10000;
- }
- static void
- Opcode_sll_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa6000;
- }
- static void
- Opcode_sll_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa1000;
- }
- static void
- Opcode_src_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x810000;
- }
- static void
- Opcode_src_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa2000;
- }
- static void
- Opcode_src_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x81000;
- }
- static void
- Opcode_srl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x910000;
- }
- static void
- Opcode_srl_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa5200;
- }
- static void
- Opcode_srl_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd400;
- }
- static void
- Opcode_srl_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x91000;
- }
- static void
- Opcode_sra_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb10000;
- }
- static void
- Opcode_sra_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa5100;
- }
- static void
- Opcode_sra_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd200;
- }
- static void
- Opcode_sra_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb1000;
- }
- static void
- Opcode_slli_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x10000;
- }
- static void
- Opcode_slli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x90000;
- }
- static void
- Opcode_slli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1000;
- }
- static void
- Opcode_srai_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x210000;
- }
- static void
- Opcode_srai_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa0000;
- }
- static void
- Opcode_srai_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe000;
- }
- static void
- Opcode_srai_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x21000;
- }
- static void
- Opcode_srli_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x410000;
- }
- static void
- Opcode_srli_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa4000;
- }
- static void
- Opcode_srli_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9000;
- }
- static void
- Opcode_srli_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x41000;
- }
- static void
- Opcode_memw_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x20c0;
- }
- static void
- Opcode_extw_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x20d0;
- }
- static void
- Opcode_isync_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2000;
- }
- static void
- Opcode_rsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2010;
- }
- static void
- Opcode_esync_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2020;
- }
- static void
- Opcode_dsync_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2030;
- }
- static void
- Opcode_rsil_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6000;
- }
- static void
- Opcode_rsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30100;
- }
- static void
- Opcode_wsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x130100;
- }
- static void
- Opcode_xsr_lend_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x610100;
- }
- static void
- Opcode_rsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30200;
- }
- static void
- Opcode_wsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x130200;
- }
- static void
- Opcode_xsr_lcount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x610200;
- }
- static void
- Opcode_rsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30000;
- }
- static void
- Opcode_wsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x130000;
- }
- static void
- Opcode_xsr_lbeg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x610000;
- }
- static void
- Opcode_rsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30300;
- }
- static void
- Opcode_wsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x130300;
- }
- static void
- Opcode_xsr_sar_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x610300;
- }
- static void
- Opcode_rsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30500;
- }
- static void
- Opcode_wsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x130500;
- }
- static void
- Opcode_xsr_litbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x610500;
- }
- static void
- Opcode_rsr_176_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b000;
- }
- static void
- Opcode_rsr_208_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d000;
- }
- static void
- Opcode_rsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3e600;
- }
- static void
- Opcode_wsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13e600;
- }
- static void
- Opcode_xsr_ps_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61e600;
- }
- static void
- Opcode_rsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b100;
- }
- static void
- Opcode_wsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13b100;
- }
- static void
- Opcode_xsr_epc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61b100;
- }
- static void
- Opcode_rsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d100;
- }
- static void
- Opcode_wsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13d100;
- }
- static void
- Opcode_xsr_excsave1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61d100;
- }
- static void
- Opcode_rsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b200;
- }
- static void
- Opcode_wsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13b200;
- }
- static void
- Opcode_xsr_epc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61b200;
- }
- static void
- Opcode_rsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d200;
- }
- static void
- Opcode_wsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13d200;
- }
- static void
- Opcode_xsr_excsave2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61d200;
- }
- static void
- Opcode_rsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b300;
- }
- static void
- Opcode_wsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13b300;
- }
- static void
- Opcode_xsr_epc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61b300;
- }
- static void
- Opcode_rsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d300;
- }
- static void
- Opcode_wsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13d300;
- }
- static void
- Opcode_xsr_excsave3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61d300;
- }
- static void
- Opcode_rsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b400;
- }
- static void
- Opcode_wsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13b400;
- }
- static void
- Opcode_xsr_epc4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61b400;
- }
- static void
- Opcode_rsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d400;
- }
- static void
- Opcode_wsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13d400;
- }
- static void
- Opcode_xsr_excsave4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61d400;
- }
- static void
- Opcode_rsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b500;
- }
- static void
- Opcode_wsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13b500;
- }
- static void
- Opcode_xsr_epc5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61b500;
- }
- static void
- Opcode_rsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d500;
- }
- static void
- Opcode_wsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13d500;
- }
- static void
- Opcode_xsr_excsave5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61d500;
- }
- static void
- Opcode_rsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b600;
- }
- static void
- Opcode_wsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13b600;
- }
- static void
- Opcode_xsr_epc6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61b600;
- }
- static void
- Opcode_rsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d600;
- }
- static void
- Opcode_wsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13d600;
- }
- static void
- Opcode_xsr_excsave6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61d600;
- }
- static void
- Opcode_rsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b700;
- }
- static void
- Opcode_wsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13b700;
- }
- static void
- Opcode_xsr_epc7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61b700;
- }
- static void
- Opcode_rsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d700;
- }
- static void
- Opcode_wsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13d700;
- }
- static void
- Opcode_xsr_excsave7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61d700;
- }
- static void
- Opcode_rsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3c200;
- }
- static void
- Opcode_wsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13c200;
- }
- static void
- Opcode_xsr_eps2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61c200;
- }
- static void
- Opcode_rsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3c300;
- }
- static void
- Opcode_wsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13c300;
- }
- static void
- Opcode_xsr_eps3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61c300;
- }
- static void
- Opcode_rsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3c400;
- }
- static void
- Opcode_wsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13c400;
- }
- static void
- Opcode_xsr_eps4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61c400;
- }
- static void
- Opcode_rsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3c500;
- }
- static void
- Opcode_wsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13c500;
- }
- static void
- Opcode_xsr_eps5_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61c500;
- }
- static void
- Opcode_rsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3c600;
- }
- static void
- Opcode_wsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13c600;
- }
- static void
- Opcode_xsr_eps6_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61c600;
- }
- static void
- Opcode_rsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3c700;
- }
- static void
- Opcode_wsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13c700;
- }
- static void
- Opcode_xsr_eps7_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61c700;
- }
- static void
- Opcode_rsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3ee00;
- }
- static void
- Opcode_wsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13ee00;
- }
- static void
- Opcode_xsr_excvaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61ee00;
- }
- static void
- Opcode_rsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3c000;
- }
- static void
- Opcode_wsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13c000;
- }
- static void
- Opcode_xsr_depc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61c000;
- }
- static void
- Opcode_rsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3e800;
- }
- static void
- Opcode_wsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13e800;
- }
- static void
- Opcode_xsr_exccause_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61e800;
- }
- static void
- Opcode_rsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3f400;
- }
- static void
- Opcode_wsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13f400;
- }
- static void
- Opcode_xsr_misc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61f400;
- }
- static void
- Opcode_rsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3f500;
- }
- static void
- Opcode_wsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13f500;
- }
- static void
- Opcode_xsr_misc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61f500;
- }
- static void
- Opcode_rsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3f600;
- }
- static void
- Opcode_wsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13f600;
- }
- static void
- Opcode_xsr_misc2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61f600;
- }
- static void
- Opcode_rsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3f700;
- }
- static void
- Opcode_wsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13f700;
- }
- static void
- Opcode_xsr_misc3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61f700;
- }
- static void
- Opcode_rsr_prid_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3eb00;
- }
- static void
- Opcode_rsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3e700;
- }
- static void
- Opcode_wsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13e700;
- }
- static void
- Opcode_xsr_vecbase_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61e700;
- }
- static void
- Opcode_mul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x740004;
- }
- static void
- Opcode_mul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x750004;
- }
- static void
- Opcode_mul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x760004;
- }
- static void
- Opcode_mul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x770004;
- }
- static void
- Opcode_umul_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x700004;
- }
- static void
- Opcode_umul_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x710004;
- }
- static void
- Opcode_umul_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x720004;
- }
- static void
- Opcode_umul_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x730004;
- }
- static void
- Opcode_mul_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x340004;
- }
- static void
- Opcode_mul_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x350004;
- }
- static void
- Opcode_mul_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x360004;
- }
- static void
- Opcode_mul_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x370004;
- }
- static void
- Opcode_mul_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x640004;
- }
- static void
- Opcode_mul_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x650004;
- }
- static void
- Opcode_mul_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x660004;
- }
- static void
- Opcode_mul_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x670004;
- }
- static void
- Opcode_mul_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x240004;
- }
- static void
- Opcode_mul_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x250004;
- }
- static void
- Opcode_mul_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x260004;
- }
- static void
- Opcode_mul_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x270004;
- }
- static void
- Opcode_mula_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x780004;
- }
- static void
- Opcode_mula_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x790004;
- }
- static void
- Opcode_mula_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7a0004;
- }
- static void
- Opcode_mula_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7b0004;
- }
- static void
- Opcode_muls_aa_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7c0004;
- }
- static void
- Opcode_muls_aa_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7d0004;
- }
- static void
- Opcode_muls_aa_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7e0004;
- }
- static void
- Opcode_muls_aa_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7f0004;
- }
- static void
- Opcode_mula_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x380004;
- }
- static void
- Opcode_mula_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x390004;
- }
- static void
- Opcode_mula_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3a0004;
- }
- static void
- Opcode_mula_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b0004;
- }
- static void
- Opcode_muls_ad_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3c0004;
- }
- static void
- Opcode_muls_ad_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3d0004;
- }
- static void
- Opcode_muls_ad_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3e0004;
- }
- static void
- Opcode_muls_ad_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3f0004;
- }
- static void
- Opcode_mula_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x680004;
- }
- static void
- Opcode_mula_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x690004;
- }
- static void
- Opcode_mula_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6a0004;
- }
- static void
- Opcode_mula_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6b0004;
- }
- static void
- Opcode_muls_da_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6c0004;
- }
- static void
- Opcode_muls_da_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6d0004;
- }
- static void
- Opcode_muls_da_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6e0004;
- }
- static void
- Opcode_muls_da_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6f0004;
- }
- static void
- Opcode_mula_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x280004;
- }
- static void
- Opcode_mula_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x290004;
- }
- static void
- Opcode_mula_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2a0004;
- }
- static void
- Opcode_mula_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2b0004;
- }
- static void
- Opcode_muls_dd_ll_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2c0004;
- }
- static void
- Opcode_muls_dd_hl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2d0004;
- }
- static void
- Opcode_muls_dd_lh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2e0004;
- }
- static void
- Opcode_muls_dd_hh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2f0004;
- }
- static void
- Opcode_mula_da_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x580004;
- }
- static void
- Opcode_mula_da_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x480004;
- }
- static void
- Opcode_mula_da_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x590004;
- }
- static void
- Opcode_mula_da_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x490004;
- }
- static void
- Opcode_mula_da_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5a0004;
- }
- static void
- Opcode_mula_da_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4a0004;
- }
- static void
- Opcode_mula_da_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5b0004;
- }
- static void
- Opcode_mula_da_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4b0004;
- }
- static void
- Opcode_mula_dd_ll_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x180004;
- }
- static void
- Opcode_mula_dd_ll_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x80004;
- }
- static void
- Opcode_mula_dd_hl_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x190004;
- }
- static void
- Opcode_mula_dd_hl_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x90004;
- }
- static void
- Opcode_mula_dd_lh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1a0004;
- }
- static void
- Opcode_mula_dd_lh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa0004;
- }
- static void
- Opcode_mula_dd_hh_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1b0004;
- }
- static void
- Opcode_mula_dd_hh_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb0004;
- }
- static void
- Opcode_lddec_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x900004;
- }
- static void
- Opcode_ldinc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x800004;
- }
- static void
- Opcode_mul16u_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc10000;
- }
- static void
- Opcode_mul16u_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9b000;
- }
- static void
- Opcode_mul16u_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc1000;
- }
- static void
- Opcode_mul16s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd10000;
- }
- static void
- Opcode_mul16s_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9c000;
- }
- static void
- Opcode_mul16s_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd1000;
- }
- static void
- Opcode_rsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x32000;
- }
- static void
- Opcode_wsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x132000;
- }
- static void
- Opcode_xsr_m0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x612000;
- }
- static void
- Opcode_rsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x32100;
- }
- static void
- Opcode_wsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x132100;
- }
- static void
- Opcode_xsr_m1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x612100;
- }
- static void
- Opcode_rsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x32200;
- }
- static void
- Opcode_wsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x132200;
- }
- static void
- Opcode_xsr_m2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x612200;
- }
- static void
- Opcode_rsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x32300;
- }
- static void
- Opcode_wsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x132300;
- }
- static void
- Opcode_xsr_m3_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x612300;
- }
- static void
- Opcode_rsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x31000;
- }
- static void
- Opcode_wsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x131000;
- }
- static void
- Opcode_xsr_acclo_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x611000;
- }
- static void
- Opcode_rsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x31100;
- }
- static void
- Opcode_wsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x131100;
- }
- static void
- Opcode_xsr_acchi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x611100;
- }
- static void
- Opcode_rfi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3010;
- }
- static void
- Opcode_waiti_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7000;
- }
- static void
- Opcode_rsr_interrupt_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3e200;
- }
- static void
- Opcode_wsr_intset_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13e200;
- }
- static void
- Opcode_wsr_intclear_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13e300;
- }
- static void
- Opcode_rsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3e400;
- }
- static void
- Opcode_wsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13e400;
- }
- static void
- Opcode_xsr_intenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61e400;
- }
- static void
- Opcode_break_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4000;
- }
- static void
- Opcode_break_n_Slot_inst16b_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf02d;
- }
- static void
- Opcode_rsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x39000;
- }
- static void
- Opcode_wsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x139000;
- }
- static void
- Opcode_xsr_dbreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x619000;
- }
- static void
- Opcode_rsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3a000;
- }
- static void
- Opcode_wsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13a000;
- }
- static void
- Opcode_xsr_dbreakc0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61a000;
- }
- static void
- Opcode_rsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x39100;
- }
- static void
- Opcode_wsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x139100;
- }
- static void
- Opcode_xsr_dbreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x619100;
- }
- static void
- Opcode_rsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3a100;
- }
- static void
- Opcode_wsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13a100;
- }
- static void
- Opcode_xsr_dbreakc1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61a100;
- }
- static void
- Opcode_rsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x38000;
- }
- static void
- Opcode_wsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x138000;
- }
- static void
- Opcode_xsr_ibreaka0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x618000;
- }
- static void
- Opcode_rsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x38100;
- }
- static void
- Opcode_wsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x138100;
- }
- static void
- Opcode_xsr_ibreaka1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x618100;
- }
- static void
- Opcode_rsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x36000;
- }
- static void
- Opcode_wsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x136000;
- }
- static void
- Opcode_xsr_ibreakenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x616000;
- }
- static void
- Opcode_rsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3e900;
- }
- static void
- Opcode_wsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13e900;
- }
- static void
- Opcode_xsr_debugcause_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61e900;
- }
- static void
- Opcode_rsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3ec00;
- }
- static void
- Opcode_wsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13ec00;
- }
- static void
- Opcode_xsr_icount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61ec00;
- }
- static void
- Opcode_rsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3ed00;
- }
- static void
- Opcode_wsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13ed00;
- }
- static void
- Opcode_xsr_icountlevel_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61ed00;
- }
- static void
- Opcode_rsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x36800;
- }
- static void
- Opcode_wsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x136800;
- }
- static void
- Opcode_xsr_ddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x616800;
- }
- static void
- Opcode_rfdo_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf1e000;
- }
- static void
- Opcode_rfdd_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf1e010;
- }
- static void
- Opcode_wsr_mmid_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x135900;
- }
- static void
- Opcode_andb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x20000;
- }
- static void
- Opcode_andbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x120000;
- }
- static void
- Opcode_orb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x220000;
- }
- static void
- Opcode_orbc_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x320000;
- }
- static void
- Opcode_xorb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x420000;
- }
- static void
- Opcode_any4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8000;
- }
- static void
- Opcode_all4_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9000;
- }
- static void
- Opcode_any8_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa000;
- }
- static void
- Opcode_all8_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb000;
- }
- static void
- Opcode_bf_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x76;
- }
- static void
- Opcode_bt_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1076;
- }
- static void
- Opcode_movf_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc30000;
- }
- static void
- Opcode_movt_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd30000;
- }
- static void
- Opcode_rsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30400;
- }
- static void
- Opcode_wsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x130400;
- }
- static void
- Opcode_xsr_br_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x610400;
- }
- static void
- Opcode_rsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3ea00;
- }
- static void
- Opcode_wsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13ea00;
- }
- static void
- Opcode_xsr_ccount_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61ea00;
- }
- static void
- Opcode_rsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3f000;
- }
- static void
- Opcode_wsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13f000;
- }
- static void
- Opcode_xsr_ccompare0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61f000;
- }
- static void
- Opcode_rsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3f100;
- }
- static void
- Opcode_wsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13f100;
- }
- static void
- Opcode_xsr_ccompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61f100;
- }
- static void
- Opcode_rsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3f200;
- }
- static void
- Opcode_wsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13f200;
- }
- static void
- Opcode_xsr_ccompare2_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61f200;
- }
- static void
- Opcode_ipf_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x70c2;
- }
- static void
- Opcode_ihi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x70e2;
- }
- static void
- Opcode_ipfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x70d2;
- }
- static void
- Opcode_ihu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x270d2;
- }
- static void
- Opcode_iiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x370d2;
- }
- static void
- Opcode_iii_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x70f2;
- }
- static void
- Opcode_lict_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf10000;
- }
- static void
- Opcode_licw_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf12000;
- }
- static void
- Opcode_sict_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf11000;
- }
- static void
- Opcode_sicw_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf13000;
- }
- static void
- Opcode_dhwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7042;
- }
- static void
- Opcode_dhwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7052;
- }
- static void
- Opcode_diwb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x47082;
- }
- static void
- Opcode_diwbi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x57082;
- }
- static void
- Opcode_dhi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7062;
- }
- static void
- Opcode_dii_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7072;
- }
- static void
- Opcode_dpfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7002;
- }
- static void
- Opcode_dpfw_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7012;
- }
- static void
- Opcode_dpfro_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7022;
- }
- static void
- Opcode_dpfwo_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7032;
- }
- static void
- Opcode_dpfl_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7082;
- }
- static void
- Opcode_dhu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x27082;
- }
- static void
- Opcode_diu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x37082;
- }
- static void
- Opcode_sdct_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf19000;
- }
- static void
- Opcode_ldct_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf18000;
- }
- static void
- Opcode_wsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x135300;
- }
- static void
- Opcode_rsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x35300;
- }
- static void
- Opcode_xsr_ptevaddr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x615300;
- }
- static void
- Opcode_rsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x35a00;
- }
- static void
- Opcode_wsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x135a00;
- }
- static void
- Opcode_xsr_rasid_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x615a00;
- }
- static void
- Opcode_rsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x35b00;
- }
- static void
- Opcode_wsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x135b00;
- }
- static void
- Opcode_xsr_itlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x615b00;
- }
- static void
- Opcode_rsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x35c00;
- }
- static void
- Opcode_wsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x135c00;
- }
- static void
- Opcode_xsr_dtlbcfg_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x615c00;
- }
- static void
- Opcode_idtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x50c000;
- }
- static void
- Opcode_pdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x50d000;
- }
- static void
- Opcode_rdtlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x50b000;
- }
- static void
- Opcode_rdtlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x50f000;
- }
- static void
- Opcode_wdtlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x50e000;
- }
- static void
- Opcode_iitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x504000;
- }
- static void
- Opcode_pitlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x505000;
- }
- static void
- Opcode_ritlb0_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x503000;
- }
- static void
- Opcode_ritlb1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x507000;
- }
- static void
- Opcode_witlb_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x506000;
- }
- static void
- Opcode_ldpte_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf1f000;
- }
- static void
- Opcode_hwwitlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x501000;
- }
- static void
- Opcode_hwwdtlba_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x509000;
- }
- static void
- Opcode_rsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3e000;
- }
- static void
- Opcode_wsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x13e000;
- }
- static void
- Opcode_xsr_cpenable_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x61e000;
- }
- static void
- Opcode_clamps_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x330000;
- }
- static void
- Opcode_clamps_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x33000;
- }
- static void
- Opcode_min_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x430000;
- }
- static void
- Opcode_min_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x43000;
- }
- static void
- Opcode_max_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x530000;
- }
- static void
- Opcode_max_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x53000;
- }
- static void
- Opcode_minu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x630000;
- }
- static void
- Opcode_minu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x63000;
- }
- static void
- Opcode_maxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x730000;
- }
- static void
- Opcode_maxu_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x73000;
- }
- static void
- Opcode_nsa_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40e000;
- }
- static void
- Opcode_nsa_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40e00;
- }
- static void
- Opcode_nsau_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40f000;
- }
- static void
- Opcode_nsau_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40f00;
- }
- static void
- Opcode_sext_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x230000;
- }
- static void
- Opcode_sext_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9f000;
- }
- static void
- Opcode_sext_Slot_xt_flix64_slot2_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8000;
- }
- static void
- Opcode_sext_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x23000;
- }
- static void
- Opcode_l32ai_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb002;
- }
- static void
- Opcode_s32ri_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf002;
- }
- static void
- Opcode_s32c1i_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe002;
- }
- static void
- Opcode_rsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30c00;
- }
- static void
- Opcode_wsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x130c00;
- }
- static void
- Opcode_xsr_scompare1_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x610c00;
- }
- static void
- Opcode_quou_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc20000;
- }
- static void
- Opcode_quos_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xd20000;
- }
- static void
- Opcode_remu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe20000;
- }
- static void
- Opcode_rems_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf20000;
- }
- static void
- Opcode_mull_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x820000;
- }
- static void
- Opcode_mull_Slot_xt_flix64_slot1_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9d000;
- }
- static void
- Opcode_mull_Slot_xt_flix64_slot0_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x82000;
- }
- static void
- Opcode_muluh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa20000;
- }
- static void
- Opcode_mulsh_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb20000;
- }
- static void
- Opcode_rur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe30e80;
- }
- static void
- Opcode_wur_fcr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf3e800;
- }
- static void
- Opcode_rur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xe30e90;
- }
- static void
- Opcode_wur_fsr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xf3e900;
- }
- static void
- Opcode_add_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa0000;
- }
- static void
- Opcode_sub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1a0000;
- }
- static void
- Opcode_mul_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2a0000;
- }
- static void
- Opcode_madd_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4a0000;
- }
- static void
- Opcode_msub_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5a0000;
- }
- static void
- Opcode_movf_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xcb0000;
- }
- static void
- Opcode_movt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xdb0000;
- }
- static void
- Opcode_moveqz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8b0000;
- }
- static void
- Opcode_movnez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9b0000;
- }
- static void
- Opcode_movltz_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xab0000;
- }
- static void
- Opcode_movgez_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xbb0000;
- }
- static void
- Opcode_abs_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xfa0010;
- }
- static void
- Opcode_mov_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xfa0000;
- }
- static void
- Opcode_neg_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xfa0060;
- }
- static void
- Opcode_un_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x1b0000;
- }
- static void
- Opcode_oeq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x2b0000;
- }
- static void
- Opcode_ueq_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3b0000;
- }
- static void
- Opcode_olt_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4b0000;
- }
- static void
- Opcode_ult_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x5b0000;
- }
- static void
- Opcode_ole_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x6b0000;
- }
- static void
- Opcode_ule_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x7b0000;
- }
- static void
- Opcode_float_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xca0000;
- }
- static void
- Opcode_ufloat_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xda0000;
- }
- static void
- Opcode_round_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8a0000;
- }
- static void
- Opcode_ceil_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xba0000;
- }
- static void
- Opcode_floor_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xaa0000;
- }
- static void
- Opcode_trunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x9a0000;
- }
- static void
- Opcode_utrunc_s_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xea0000;
- }
- static void
- Opcode_rfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xfa0040;
- }
- static void
- Opcode_wfr_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xfa0050;
- }
- static void
- Opcode_lsi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x3;
- }
- static void
- Opcode_lsiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8003;
- }
- static void
- Opcode_lsx_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x80000;
- }
- static void
- Opcode_lsxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x180000;
- }
- static void
- Opcode_ssi_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x4003;
- }
- static void
- Opcode_ssiu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc003;
- }
- static void
- Opcode_ssx_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x480000;
- }
- static void
- Opcode_ssxu_Slot_inst_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x580000;
- }
- static void
- Opcode_beqz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa8000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bnez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xc0000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bgez_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb0000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bltz_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xb8000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_beqi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x40000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bnei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x98000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bgei_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x50000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_blti_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x70000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x60000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bltui_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x80000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bbci_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x8000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x10000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_beq_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x38000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bne_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x90000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bge_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x48000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_blt_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x68000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x58000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bltu_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x78000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bany_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x20000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bnone_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0xa0000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_ball_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x18000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bnall_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x88000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bbc_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x28000000;
- slotbuf[1] = 0;
- }
- static void
- Opcode_bbs_w18_Slot_xt_flix64_slot3_encode (xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = 0x30000000;
- slotbuf[1] = 0;
- }
- const xtensa_opcode_encode_fn Opcode_excw_encode_fns[] = {
- Opcode_excw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rfe_encode_fns[] = {
- Opcode_rfe_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rfde_encode_fns[] = {
- Opcode_rfde_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_syscall_encode_fns[] = {
- Opcode_syscall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_simcall_encode_fns[] = {
- Opcode_simcall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_call12_encode_fns[] = {
- Opcode_call12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_call8_encode_fns[] = {
- Opcode_call8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_call4_encode_fns[] = {
- Opcode_call4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_callx12_encode_fns[] = {
- Opcode_callx12_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_callx8_encode_fns[] = {
- Opcode_callx8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_callx4_encode_fns[] = {
- Opcode_callx4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_entry_encode_fns[] = {
- Opcode_entry_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movsp_encode_fns[] = {
- Opcode_movsp_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rotw_encode_fns[] = {
- Opcode_rotw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_retw_encode_fns[] = {
- Opcode_retw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_retw_n_encode_fns[] = {
- 0, 0, Opcode_retw_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rfwo_encode_fns[] = {
- Opcode_rfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rfwu_encode_fns[] = {
- Opcode_rfwu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_l32e_encode_fns[] = {
- Opcode_l32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_s32e_encode_fns[] = {
- Opcode_s32e_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_windowbase_encode_fns[] = {
- Opcode_rsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_windowbase_encode_fns[] = {
- Opcode_wsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_windowbase_encode_fns[] = {
- Opcode_xsr_windowbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_windowstart_encode_fns[] = {
- Opcode_rsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_windowstart_encode_fns[] = {
- Opcode_wsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_windowstart_encode_fns[] = {
- Opcode_xsr_windowstart_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_add_n_encode_fns[] = {
- 0, Opcode_add_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_addi_n_encode_fns[] = {
- 0, Opcode_addi_n_Slot_inst16a_encode, 0, 0, 0, 0, Opcode_addi_n_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_beqz_n_encode_fns[] = {
- 0, 0, Opcode_beqz_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bnez_n_encode_fns[] = {
- 0, 0, Opcode_bnez_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ill_n_encode_fns[] = {
- 0, 0, Opcode_ill_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_l32i_n_encode_fns[] = {
- 0, Opcode_l32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mov_n_encode_fns[] = {
- 0, 0, Opcode_mov_n_Slot_inst16b_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot0_encode, Opcode_mov_n_Slot_xt_flix64_slot1_encode, Opcode_mov_n_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_movi_n_encode_fns[] = {
- 0, 0, Opcode_movi_n_Slot_inst16b_encode, 0, 0, 0, Opcode_movi_n_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_nop_n_encode_fns[] = {
- 0, 0, Opcode_nop_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ret_n_encode_fns[] = {
- 0, 0, Opcode_ret_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_s32i_n_encode_fns[] = {
- 0, Opcode_s32i_n_Slot_inst16a_encode, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rur_threadptr_encode_fns[] = {
- Opcode_rur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wur_threadptr_encode_fns[] = {
- Opcode_wur_threadptr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_addi_encode_fns[] = {
- Opcode_addi_Slot_inst_encode, 0, 0, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot0_encode, Opcode_addi_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_addmi_encode_fns[] = {
- Opcode_addmi_Slot_inst_encode, 0, 0, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot0_encode, Opcode_addmi_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_add_encode_fns[] = {
- Opcode_add_Slot_inst_encode, 0, 0, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot0_encode, Opcode_add_Slot_xt_flix64_slot1_encode, Opcode_add_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_sub_encode_fns[] = {
- Opcode_sub_Slot_inst_encode, 0, 0, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot0_encode, Opcode_sub_Slot_xt_flix64_slot1_encode, Opcode_sub_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_addx2_encode_fns[] = {
- Opcode_addx2_Slot_inst_encode, 0, 0, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot0_encode, Opcode_addx2_Slot_xt_flix64_slot1_encode, Opcode_addx2_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_addx4_encode_fns[] = {
- Opcode_addx4_Slot_inst_encode, 0, 0, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot0_encode, Opcode_addx4_Slot_xt_flix64_slot1_encode, Opcode_addx4_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_addx8_encode_fns[] = {
- Opcode_addx8_Slot_inst_encode, 0, 0, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot0_encode, Opcode_addx8_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_subx2_encode_fns[] = {
- Opcode_subx2_Slot_inst_encode, 0, 0, Opcode_subx2_Slot_xt_flix64_slot0_encode, Opcode_subx2_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_subx4_encode_fns[] = {
- Opcode_subx4_Slot_inst_encode, 0, 0, Opcode_subx4_Slot_xt_flix64_slot0_encode, Opcode_subx4_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_subx8_encode_fns[] = {
- Opcode_subx8_Slot_inst_encode, 0, 0, Opcode_subx8_Slot_xt_flix64_slot0_encode, Opcode_subx8_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_and_encode_fns[] = {
- Opcode_and_Slot_inst_encode, 0, 0, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot0_encode, Opcode_and_Slot_xt_flix64_slot1_encode, Opcode_and_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_or_encode_fns[] = {
- Opcode_or_Slot_inst_encode, 0, 0, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot0_encode, Opcode_or_Slot_xt_flix64_slot1_encode, Opcode_or_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_xor_encode_fns[] = {
- Opcode_xor_Slot_inst_encode, 0, 0, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot0_encode, Opcode_xor_Slot_xt_flix64_slot1_encode, Opcode_xor_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_beqi_encode_fns[] = {
- Opcode_beqi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bnei_encode_fns[] = {
- Opcode_bnei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bgei_encode_fns[] = {
- Opcode_bgei_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_blti_encode_fns[] = {
- Opcode_blti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bbci_encode_fns[] = {
- Opcode_bbci_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bbsi_encode_fns[] = {
- Opcode_bbsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bgeui_encode_fns[] = {
- Opcode_bgeui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bltui_encode_fns[] = {
- Opcode_bltui_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_beq_encode_fns[] = {
- Opcode_beq_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bne_encode_fns[] = {
- Opcode_bne_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bge_encode_fns[] = {
- Opcode_bge_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_blt_encode_fns[] = {
- Opcode_blt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bgeu_encode_fns[] = {
- Opcode_bgeu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bltu_encode_fns[] = {
- Opcode_bltu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bany_encode_fns[] = {
- Opcode_bany_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bnone_encode_fns[] = {
- Opcode_bnone_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ball_encode_fns[] = {
- Opcode_ball_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bnall_encode_fns[] = {
- Opcode_bnall_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bbc_encode_fns[] = {
- Opcode_bbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bbs_encode_fns[] = {
- Opcode_bbs_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_beqz_encode_fns[] = {
- Opcode_beqz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bnez_encode_fns[] = {
- Opcode_bnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bgez_encode_fns[] = {
- Opcode_bgez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bltz_encode_fns[] = {
- Opcode_bltz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_call0_encode_fns[] = {
- Opcode_call0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_callx0_encode_fns[] = {
- Opcode_callx0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_extui_encode_fns[] = {
- Opcode_extui_Slot_inst_encode, 0, 0, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot0_encode, Opcode_extui_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ill_encode_fns[] = {
- Opcode_ill_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_j_encode_fns[] = {
- Opcode_j_Slot_inst_encode, 0, 0, 0, 0, Opcode_j_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_jx_encode_fns[] = {
- Opcode_jx_Slot_inst_encode, 0, 0, 0, 0, Opcode_jx_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_l16ui_encode_fns[] = {
- Opcode_l16ui_Slot_inst_encode, 0, 0, Opcode_l16ui_Slot_xt_flix64_slot0_encode, Opcode_l16ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_l16si_encode_fns[] = {
- Opcode_l16si_Slot_inst_encode, 0, 0, Opcode_l16si_Slot_xt_flix64_slot0_encode, Opcode_l16si_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_l32i_encode_fns[] = {
- Opcode_l32i_Slot_inst_encode, 0, 0, Opcode_l32i_Slot_xt_flix64_slot0_encode, Opcode_l32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_l32r_encode_fns[] = {
- Opcode_l32r_Slot_inst_encode, 0, 0, Opcode_l32r_Slot_xt_flix64_slot0_encode, Opcode_l32r_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_l8ui_encode_fns[] = {
- Opcode_l8ui_Slot_inst_encode, 0, 0, Opcode_l8ui_Slot_xt_flix64_slot0_encode, Opcode_l8ui_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_loop_encode_fns[] = {
- Opcode_loop_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_loopnez_encode_fns[] = {
- Opcode_loopnez_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_loopgtz_encode_fns[] = {
- Opcode_loopgtz_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movi_encode_fns[] = {
- Opcode_movi_Slot_inst_encode, 0, 0, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot0_encode, Opcode_movi_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_moveqz_encode_fns[] = {
- Opcode_moveqz_Slot_inst_encode, 0, 0, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot0_encode, Opcode_moveqz_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movnez_encode_fns[] = {
- Opcode_movnez_Slot_inst_encode, 0, 0, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot0_encode, Opcode_movnez_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movltz_encode_fns[] = {
- Opcode_movltz_Slot_inst_encode, 0, 0, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot0_encode, Opcode_movltz_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movgez_encode_fns[] = {
- Opcode_movgez_Slot_inst_encode, 0, 0, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot0_encode, Opcode_movgez_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_neg_encode_fns[] = {
- Opcode_neg_Slot_inst_encode, 0, 0, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot0_encode, Opcode_neg_Slot_xt_flix64_slot1_encode, Opcode_neg_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_abs_encode_fns[] = {
- Opcode_abs_Slot_inst_encode, 0, 0, Opcode_abs_Slot_xt_flix64_slot0_encode, Opcode_abs_Slot_xt_flix64_slot0_encode, 0, Opcode_abs_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_nop_encode_fns[] = {
- Opcode_nop_Slot_inst_encode, 0, 0, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot0_encode, Opcode_nop_Slot_xt_flix64_slot1_encode, Opcode_nop_Slot_xt_flix64_slot2_encode, Opcode_nop_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_ret_encode_fns[] = {
- Opcode_ret_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_s16i_encode_fns[] = {
- Opcode_s16i_Slot_inst_encode, 0, 0, Opcode_s16i_Slot_xt_flix64_slot0_encode, Opcode_s16i_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_s32i_encode_fns[] = {
- Opcode_s32i_Slot_inst_encode, 0, 0, Opcode_s32i_Slot_xt_flix64_slot0_encode, Opcode_s32i_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_s8i_encode_fns[] = {
- Opcode_s8i_Slot_inst_encode, 0, 0, Opcode_s8i_Slot_xt_flix64_slot0_encode, Opcode_s8i_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssr_encode_fns[] = {
- Opcode_ssr_Slot_inst_encode, 0, 0, Opcode_ssr_Slot_xt_flix64_slot0_encode, Opcode_ssr_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssl_encode_fns[] = {
- Opcode_ssl_Slot_inst_encode, 0, 0, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot0_encode, Opcode_ssl_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssa8l_encode_fns[] = {
- Opcode_ssa8l_Slot_inst_encode, 0, 0, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, Opcode_ssa8l_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssa8b_encode_fns[] = {
- Opcode_ssa8b_Slot_inst_encode, 0, 0, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, Opcode_ssa8b_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssai_encode_fns[] = {
- Opcode_ssai_Slot_inst_encode, 0, 0, Opcode_ssai_Slot_xt_flix64_slot0_encode, Opcode_ssai_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_sll_encode_fns[] = {
- Opcode_sll_Slot_inst_encode, 0, 0, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot0_encode, Opcode_sll_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_src_encode_fns[] = {
- Opcode_src_Slot_inst_encode, 0, 0, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot0_encode, Opcode_src_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_srl_encode_fns[] = {
- Opcode_srl_Slot_inst_encode, 0, 0, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot0_encode, Opcode_srl_Slot_xt_flix64_slot1_encode, Opcode_srl_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_sra_encode_fns[] = {
- Opcode_sra_Slot_inst_encode, 0, 0, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot0_encode, Opcode_sra_Slot_xt_flix64_slot1_encode, Opcode_sra_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_slli_encode_fns[] = {
- Opcode_slli_Slot_inst_encode, 0, 0, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot0_encode, Opcode_slli_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_srai_encode_fns[] = {
- Opcode_srai_Slot_inst_encode, 0, 0, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot0_encode, Opcode_srai_Slot_xt_flix64_slot1_encode, Opcode_srai_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_srli_encode_fns[] = {
- Opcode_srli_Slot_inst_encode, 0, 0, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot0_encode, Opcode_srli_Slot_xt_flix64_slot1_encode, Opcode_srli_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_memw_encode_fns[] = {
- Opcode_memw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_extw_encode_fns[] = {
- Opcode_extw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_isync_encode_fns[] = {
- Opcode_isync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsync_encode_fns[] = {
- Opcode_rsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_esync_encode_fns[] = {
- Opcode_esync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dsync_encode_fns[] = {
- Opcode_dsync_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsil_encode_fns[] = {
- Opcode_rsil_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_lend_encode_fns[] = {
- Opcode_rsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_lend_encode_fns[] = {
- Opcode_wsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_lend_encode_fns[] = {
- Opcode_xsr_lend_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_lcount_encode_fns[] = {
- Opcode_rsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_lcount_encode_fns[] = {
- Opcode_wsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_lcount_encode_fns[] = {
- Opcode_xsr_lcount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_lbeg_encode_fns[] = {
- Opcode_rsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_lbeg_encode_fns[] = {
- Opcode_wsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_lbeg_encode_fns[] = {
- Opcode_xsr_lbeg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_sar_encode_fns[] = {
- Opcode_rsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_sar_encode_fns[] = {
- Opcode_wsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_sar_encode_fns[] = {
- Opcode_xsr_sar_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_litbase_encode_fns[] = {
- Opcode_rsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_litbase_encode_fns[] = {
- Opcode_wsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_litbase_encode_fns[] = {
- Opcode_xsr_litbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_176_encode_fns[] = {
- Opcode_rsr_176_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_208_encode_fns[] = {
- Opcode_rsr_208_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ps_encode_fns[] = {
- Opcode_rsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ps_encode_fns[] = {
- Opcode_wsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ps_encode_fns[] = {
- Opcode_xsr_ps_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_epc1_encode_fns[] = {
- Opcode_rsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_epc1_encode_fns[] = {
- Opcode_wsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_epc1_encode_fns[] = {
- Opcode_xsr_epc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_excsave1_encode_fns[] = {
- Opcode_rsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_excsave1_encode_fns[] = {
- Opcode_wsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_excsave1_encode_fns[] = {
- Opcode_xsr_excsave1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_epc2_encode_fns[] = {
- Opcode_rsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_epc2_encode_fns[] = {
- Opcode_wsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_epc2_encode_fns[] = {
- Opcode_xsr_epc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_excsave2_encode_fns[] = {
- Opcode_rsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_excsave2_encode_fns[] = {
- Opcode_wsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_excsave2_encode_fns[] = {
- Opcode_xsr_excsave2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_epc3_encode_fns[] = {
- Opcode_rsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_epc3_encode_fns[] = {
- Opcode_wsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_epc3_encode_fns[] = {
- Opcode_xsr_epc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_excsave3_encode_fns[] = {
- Opcode_rsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_excsave3_encode_fns[] = {
- Opcode_wsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_excsave3_encode_fns[] = {
- Opcode_xsr_excsave3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_epc4_encode_fns[] = {
- Opcode_rsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_epc4_encode_fns[] = {
- Opcode_wsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_epc4_encode_fns[] = {
- Opcode_xsr_epc4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_excsave4_encode_fns[] = {
- Opcode_rsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_excsave4_encode_fns[] = {
- Opcode_wsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_excsave4_encode_fns[] = {
- Opcode_xsr_excsave4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_epc5_encode_fns[] = {
- Opcode_rsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_epc5_encode_fns[] = {
- Opcode_wsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_epc5_encode_fns[] = {
- Opcode_xsr_epc5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_excsave5_encode_fns[] = {
- Opcode_rsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_excsave5_encode_fns[] = {
- Opcode_wsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_excsave5_encode_fns[] = {
- Opcode_xsr_excsave5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_epc6_encode_fns[] = {
- Opcode_rsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_epc6_encode_fns[] = {
- Opcode_wsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_epc6_encode_fns[] = {
- Opcode_xsr_epc6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_excsave6_encode_fns[] = {
- Opcode_rsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_excsave6_encode_fns[] = {
- Opcode_wsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_excsave6_encode_fns[] = {
- Opcode_xsr_excsave6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_epc7_encode_fns[] = {
- Opcode_rsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_epc7_encode_fns[] = {
- Opcode_wsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_epc7_encode_fns[] = {
- Opcode_xsr_epc7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_excsave7_encode_fns[] = {
- Opcode_rsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_excsave7_encode_fns[] = {
- Opcode_wsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_excsave7_encode_fns[] = {
- Opcode_xsr_excsave7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_eps2_encode_fns[] = {
- Opcode_rsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_eps2_encode_fns[] = {
- Opcode_wsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_eps2_encode_fns[] = {
- Opcode_xsr_eps2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_eps3_encode_fns[] = {
- Opcode_rsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_eps3_encode_fns[] = {
- Opcode_wsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_eps3_encode_fns[] = {
- Opcode_xsr_eps3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_eps4_encode_fns[] = {
- Opcode_rsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_eps4_encode_fns[] = {
- Opcode_wsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_eps4_encode_fns[] = {
- Opcode_xsr_eps4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_eps5_encode_fns[] = {
- Opcode_rsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_eps5_encode_fns[] = {
- Opcode_wsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_eps5_encode_fns[] = {
- Opcode_xsr_eps5_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_eps6_encode_fns[] = {
- Opcode_rsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_eps6_encode_fns[] = {
- Opcode_wsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_eps6_encode_fns[] = {
- Opcode_xsr_eps6_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_eps7_encode_fns[] = {
- Opcode_rsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_eps7_encode_fns[] = {
- Opcode_wsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_eps7_encode_fns[] = {
- Opcode_xsr_eps7_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_excvaddr_encode_fns[] = {
- Opcode_rsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_excvaddr_encode_fns[] = {
- Opcode_wsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_excvaddr_encode_fns[] = {
- Opcode_xsr_excvaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_depc_encode_fns[] = {
- Opcode_rsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_depc_encode_fns[] = {
- Opcode_wsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_depc_encode_fns[] = {
- Opcode_xsr_depc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_exccause_encode_fns[] = {
- Opcode_rsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_exccause_encode_fns[] = {
- Opcode_wsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_exccause_encode_fns[] = {
- Opcode_xsr_exccause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_misc0_encode_fns[] = {
- Opcode_rsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_misc0_encode_fns[] = {
- Opcode_wsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_misc0_encode_fns[] = {
- Opcode_xsr_misc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_misc1_encode_fns[] = {
- Opcode_rsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_misc1_encode_fns[] = {
- Opcode_wsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_misc1_encode_fns[] = {
- Opcode_xsr_misc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_misc2_encode_fns[] = {
- Opcode_rsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_misc2_encode_fns[] = {
- Opcode_wsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_misc2_encode_fns[] = {
- Opcode_xsr_misc2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_misc3_encode_fns[] = {
- Opcode_rsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_misc3_encode_fns[] = {
- Opcode_wsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_misc3_encode_fns[] = {
- Opcode_xsr_misc3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_prid_encode_fns[] = {
- Opcode_rsr_prid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_vecbase_encode_fns[] = {
- Opcode_rsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_vecbase_encode_fns[] = {
- Opcode_wsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_vecbase_encode_fns[] = {
- Opcode_xsr_vecbase_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_aa_ll_encode_fns[] = {
- Opcode_mul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_aa_hl_encode_fns[] = {
- Opcode_mul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_aa_lh_encode_fns[] = {
- Opcode_mul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_aa_hh_encode_fns[] = {
- Opcode_mul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_umul_aa_ll_encode_fns[] = {
- Opcode_umul_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_umul_aa_hl_encode_fns[] = {
- Opcode_umul_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_umul_aa_lh_encode_fns[] = {
- Opcode_umul_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_umul_aa_hh_encode_fns[] = {
- Opcode_umul_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_ad_ll_encode_fns[] = {
- Opcode_mul_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_ad_hl_encode_fns[] = {
- Opcode_mul_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_ad_lh_encode_fns[] = {
- Opcode_mul_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_ad_hh_encode_fns[] = {
- Opcode_mul_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_da_ll_encode_fns[] = {
- Opcode_mul_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_da_hl_encode_fns[] = {
- Opcode_mul_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_da_lh_encode_fns[] = {
- Opcode_mul_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_da_hh_encode_fns[] = {
- Opcode_mul_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_dd_ll_encode_fns[] = {
- Opcode_mul_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_dd_hl_encode_fns[] = {
- Opcode_mul_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_dd_lh_encode_fns[] = {
- Opcode_mul_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_dd_hh_encode_fns[] = {
- Opcode_mul_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_aa_ll_encode_fns[] = {
- Opcode_mula_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_aa_hl_encode_fns[] = {
- Opcode_mula_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_aa_lh_encode_fns[] = {
- Opcode_mula_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_aa_hh_encode_fns[] = {
- Opcode_mula_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_aa_ll_encode_fns[] = {
- Opcode_muls_aa_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_aa_hl_encode_fns[] = {
- Opcode_muls_aa_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_aa_lh_encode_fns[] = {
- Opcode_muls_aa_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_aa_hh_encode_fns[] = {
- Opcode_muls_aa_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_ad_ll_encode_fns[] = {
- Opcode_mula_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_ad_hl_encode_fns[] = {
- Opcode_mula_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_ad_lh_encode_fns[] = {
- Opcode_mula_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_ad_hh_encode_fns[] = {
- Opcode_mula_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_ad_ll_encode_fns[] = {
- Opcode_muls_ad_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_ad_hl_encode_fns[] = {
- Opcode_muls_ad_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_ad_lh_encode_fns[] = {
- Opcode_muls_ad_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_ad_hh_encode_fns[] = {
- Opcode_muls_ad_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_ll_encode_fns[] = {
- Opcode_mula_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_hl_encode_fns[] = {
- Opcode_mula_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_lh_encode_fns[] = {
- Opcode_mula_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_hh_encode_fns[] = {
- Opcode_mula_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_da_ll_encode_fns[] = {
- Opcode_muls_da_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_da_hl_encode_fns[] = {
- Opcode_muls_da_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_da_lh_encode_fns[] = {
- Opcode_muls_da_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_da_hh_encode_fns[] = {
- Opcode_muls_da_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_ll_encode_fns[] = {
- Opcode_mula_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_hl_encode_fns[] = {
- Opcode_mula_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_lh_encode_fns[] = {
- Opcode_mula_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_hh_encode_fns[] = {
- Opcode_mula_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_dd_ll_encode_fns[] = {
- Opcode_muls_dd_ll_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_dd_hl_encode_fns[] = {
- Opcode_muls_dd_hl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_dd_lh_encode_fns[] = {
- Opcode_muls_dd_lh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muls_dd_hh_encode_fns[] = {
- Opcode_muls_dd_hh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_ll_lddec_encode_fns[] = {
- Opcode_mula_da_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_ll_ldinc_encode_fns[] = {
- Opcode_mula_da_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_hl_lddec_encode_fns[] = {
- Opcode_mula_da_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_hl_ldinc_encode_fns[] = {
- Opcode_mula_da_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_lh_lddec_encode_fns[] = {
- Opcode_mula_da_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_lh_ldinc_encode_fns[] = {
- Opcode_mula_da_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_hh_lddec_encode_fns[] = {
- Opcode_mula_da_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_da_hh_ldinc_encode_fns[] = {
- Opcode_mula_da_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_ll_lddec_encode_fns[] = {
- Opcode_mula_dd_ll_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_ll_ldinc_encode_fns[] = {
- Opcode_mula_dd_ll_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_hl_lddec_encode_fns[] = {
- Opcode_mula_dd_hl_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_hl_ldinc_encode_fns[] = {
- Opcode_mula_dd_hl_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_lh_lddec_encode_fns[] = {
- Opcode_mula_dd_lh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_lh_ldinc_encode_fns[] = {
- Opcode_mula_dd_lh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_hh_lddec_encode_fns[] = {
- Opcode_mula_dd_hh_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mula_dd_hh_ldinc_encode_fns[] = {
- Opcode_mula_dd_hh_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_lddec_encode_fns[] = {
- Opcode_lddec_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ldinc_encode_fns[] = {
- Opcode_ldinc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul16u_encode_fns[] = {
- Opcode_mul16u_Slot_inst_encode, 0, 0, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot0_encode, Opcode_mul16u_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul16s_encode_fns[] = {
- Opcode_mul16s_Slot_inst_encode, 0, 0, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot0_encode, Opcode_mul16s_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_m0_encode_fns[] = {
- Opcode_rsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_m0_encode_fns[] = {
- Opcode_wsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_m0_encode_fns[] = {
- Opcode_xsr_m0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_m1_encode_fns[] = {
- Opcode_rsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_m1_encode_fns[] = {
- Opcode_wsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_m1_encode_fns[] = {
- Opcode_xsr_m1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_m2_encode_fns[] = {
- Opcode_rsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_m2_encode_fns[] = {
- Opcode_wsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_m2_encode_fns[] = {
- Opcode_xsr_m2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_m3_encode_fns[] = {
- Opcode_rsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_m3_encode_fns[] = {
- Opcode_wsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_m3_encode_fns[] = {
- Opcode_xsr_m3_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_acclo_encode_fns[] = {
- Opcode_rsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_acclo_encode_fns[] = {
- Opcode_wsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_acclo_encode_fns[] = {
- Opcode_xsr_acclo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_acchi_encode_fns[] = {
- Opcode_rsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_acchi_encode_fns[] = {
- Opcode_wsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_acchi_encode_fns[] = {
- Opcode_xsr_acchi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rfi_encode_fns[] = {
- Opcode_rfi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_waiti_encode_fns[] = {
- Opcode_waiti_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_interrupt_encode_fns[] = {
- Opcode_rsr_interrupt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_intset_encode_fns[] = {
- Opcode_wsr_intset_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_intclear_encode_fns[] = {
- Opcode_wsr_intclear_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_intenable_encode_fns[] = {
- Opcode_rsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_intenable_encode_fns[] = {
- Opcode_wsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_intenable_encode_fns[] = {
- Opcode_xsr_intenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_break_encode_fns[] = {
- Opcode_break_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_break_n_encode_fns[] = {
- 0, 0, Opcode_break_n_Slot_inst16b_encode, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_dbreaka0_encode_fns[] = {
- Opcode_rsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_dbreaka0_encode_fns[] = {
- Opcode_wsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_dbreaka0_encode_fns[] = {
- Opcode_xsr_dbreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_dbreakc0_encode_fns[] = {
- Opcode_rsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_dbreakc0_encode_fns[] = {
- Opcode_wsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_dbreakc0_encode_fns[] = {
- Opcode_xsr_dbreakc0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_dbreaka1_encode_fns[] = {
- Opcode_rsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_dbreaka1_encode_fns[] = {
- Opcode_wsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_dbreaka1_encode_fns[] = {
- Opcode_xsr_dbreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_dbreakc1_encode_fns[] = {
- Opcode_rsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_dbreakc1_encode_fns[] = {
- Opcode_wsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_dbreakc1_encode_fns[] = {
- Opcode_xsr_dbreakc1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ibreaka0_encode_fns[] = {
- Opcode_rsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ibreaka0_encode_fns[] = {
- Opcode_wsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ibreaka0_encode_fns[] = {
- Opcode_xsr_ibreaka0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ibreaka1_encode_fns[] = {
- Opcode_rsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ibreaka1_encode_fns[] = {
- Opcode_wsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ibreaka1_encode_fns[] = {
- Opcode_xsr_ibreaka1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ibreakenable_encode_fns[] = {
- Opcode_rsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ibreakenable_encode_fns[] = {
- Opcode_wsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ibreakenable_encode_fns[] = {
- Opcode_xsr_ibreakenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_debugcause_encode_fns[] = {
- Opcode_rsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_debugcause_encode_fns[] = {
- Opcode_wsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_debugcause_encode_fns[] = {
- Opcode_xsr_debugcause_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_icount_encode_fns[] = {
- Opcode_rsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_icount_encode_fns[] = {
- Opcode_wsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_icount_encode_fns[] = {
- Opcode_xsr_icount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_icountlevel_encode_fns[] = {
- Opcode_rsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_icountlevel_encode_fns[] = {
- Opcode_wsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_icountlevel_encode_fns[] = {
- Opcode_xsr_icountlevel_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ddr_encode_fns[] = {
- Opcode_rsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ddr_encode_fns[] = {
- Opcode_wsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ddr_encode_fns[] = {
- Opcode_xsr_ddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rfdo_encode_fns[] = {
- Opcode_rfdo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rfdd_encode_fns[] = {
- Opcode_rfdd_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_mmid_encode_fns[] = {
- Opcode_wsr_mmid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_andb_encode_fns[] = {
- Opcode_andb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_andbc_encode_fns[] = {
- Opcode_andbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_orb_encode_fns[] = {
- Opcode_orb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_orbc_encode_fns[] = {
- Opcode_orbc_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xorb_encode_fns[] = {
- Opcode_xorb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_any4_encode_fns[] = {
- Opcode_any4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_all4_encode_fns[] = {
- Opcode_all4_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_any8_encode_fns[] = {
- Opcode_any8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_all8_encode_fns[] = {
- Opcode_all8_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bf_encode_fns[] = {
- Opcode_bf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_bt_encode_fns[] = {
- Opcode_bt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movf_encode_fns[] = {
- Opcode_movf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movt_encode_fns[] = {
- Opcode_movt_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_br_encode_fns[] = {
- Opcode_rsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_br_encode_fns[] = {
- Opcode_wsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_br_encode_fns[] = {
- Opcode_xsr_br_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ccount_encode_fns[] = {
- Opcode_rsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ccount_encode_fns[] = {
- Opcode_wsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ccount_encode_fns[] = {
- Opcode_xsr_ccount_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ccompare0_encode_fns[] = {
- Opcode_rsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ccompare0_encode_fns[] = {
- Opcode_wsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ccompare0_encode_fns[] = {
- Opcode_xsr_ccompare0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ccompare1_encode_fns[] = {
- Opcode_rsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ccompare1_encode_fns[] = {
- Opcode_wsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ccompare1_encode_fns[] = {
- Opcode_xsr_ccompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ccompare2_encode_fns[] = {
- Opcode_rsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ccompare2_encode_fns[] = {
- Opcode_wsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ccompare2_encode_fns[] = {
- Opcode_xsr_ccompare2_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ipf_encode_fns[] = {
- Opcode_ipf_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ihi_encode_fns[] = {
- Opcode_ihi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ipfl_encode_fns[] = {
- Opcode_ipfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ihu_encode_fns[] = {
- Opcode_ihu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_iiu_encode_fns[] = {
- Opcode_iiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_iii_encode_fns[] = {
- Opcode_iii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_lict_encode_fns[] = {
- Opcode_lict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_licw_encode_fns[] = {
- Opcode_licw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_sict_encode_fns[] = {
- Opcode_sict_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_sicw_encode_fns[] = {
- Opcode_sicw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dhwb_encode_fns[] = {
- Opcode_dhwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dhwbi_encode_fns[] = {
- Opcode_dhwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_diwb_encode_fns[] = {
- Opcode_diwb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_diwbi_encode_fns[] = {
- Opcode_diwbi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dhi_encode_fns[] = {
- Opcode_dhi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dii_encode_fns[] = {
- Opcode_dii_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dpfr_encode_fns[] = {
- Opcode_dpfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dpfw_encode_fns[] = {
- Opcode_dpfw_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dpfro_encode_fns[] = {
- Opcode_dpfro_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dpfwo_encode_fns[] = {
- Opcode_dpfwo_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dpfl_encode_fns[] = {
- Opcode_dpfl_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_dhu_encode_fns[] = {
- Opcode_dhu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_diu_encode_fns[] = {
- Opcode_diu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_sdct_encode_fns[] = {
- Opcode_sdct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ldct_encode_fns[] = {
- Opcode_ldct_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_ptevaddr_encode_fns[] = {
- Opcode_wsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_ptevaddr_encode_fns[] = {
- Opcode_rsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_ptevaddr_encode_fns[] = {
- Opcode_xsr_ptevaddr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_rasid_encode_fns[] = {
- Opcode_rsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_rasid_encode_fns[] = {
- Opcode_wsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_rasid_encode_fns[] = {
- Opcode_xsr_rasid_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_itlbcfg_encode_fns[] = {
- Opcode_rsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_itlbcfg_encode_fns[] = {
- Opcode_wsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_itlbcfg_encode_fns[] = {
- Opcode_xsr_itlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_dtlbcfg_encode_fns[] = {
- Opcode_rsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_dtlbcfg_encode_fns[] = {
- Opcode_wsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_dtlbcfg_encode_fns[] = {
- Opcode_xsr_dtlbcfg_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_idtlb_encode_fns[] = {
- Opcode_idtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_pdtlb_encode_fns[] = {
- Opcode_pdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rdtlb0_encode_fns[] = {
- Opcode_rdtlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rdtlb1_encode_fns[] = {
- Opcode_rdtlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wdtlb_encode_fns[] = {
- Opcode_wdtlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_iitlb_encode_fns[] = {
- Opcode_iitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_pitlb_encode_fns[] = {
- Opcode_pitlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ritlb0_encode_fns[] = {
- Opcode_ritlb0_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ritlb1_encode_fns[] = {
- Opcode_ritlb1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_witlb_encode_fns[] = {
- Opcode_witlb_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ldpte_encode_fns[] = {
- Opcode_ldpte_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_hwwitlba_encode_fns[] = {
- Opcode_hwwitlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_hwwdtlba_encode_fns[] = {
- Opcode_hwwdtlba_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_cpenable_encode_fns[] = {
- Opcode_rsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_cpenable_encode_fns[] = {
- Opcode_wsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_cpenable_encode_fns[] = {
- Opcode_xsr_cpenable_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_clamps_encode_fns[] = {
- Opcode_clamps_Slot_inst_encode, 0, 0, Opcode_clamps_Slot_xt_flix64_slot0_encode, Opcode_clamps_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_min_encode_fns[] = {
- Opcode_min_Slot_inst_encode, 0, 0, Opcode_min_Slot_xt_flix64_slot0_encode, Opcode_min_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_max_encode_fns[] = {
- Opcode_max_Slot_inst_encode, 0, 0, Opcode_max_Slot_xt_flix64_slot0_encode, Opcode_max_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_minu_encode_fns[] = {
- Opcode_minu_Slot_inst_encode, 0, 0, Opcode_minu_Slot_xt_flix64_slot0_encode, Opcode_minu_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_maxu_encode_fns[] = {
- Opcode_maxu_Slot_inst_encode, 0, 0, Opcode_maxu_Slot_xt_flix64_slot0_encode, Opcode_maxu_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_nsa_encode_fns[] = {
- Opcode_nsa_Slot_inst_encode, 0, 0, Opcode_nsa_Slot_xt_flix64_slot0_encode, Opcode_nsa_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_nsau_encode_fns[] = {
- Opcode_nsau_Slot_inst_encode, 0, 0, Opcode_nsau_Slot_xt_flix64_slot0_encode, Opcode_nsau_Slot_xt_flix64_slot0_encode, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_sext_encode_fns[] = {
- Opcode_sext_Slot_inst_encode, 0, 0, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot0_encode, Opcode_sext_Slot_xt_flix64_slot1_encode, Opcode_sext_Slot_xt_flix64_slot2_encode, 0
- };
- const xtensa_opcode_encode_fn Opcode_l32ai_encode_fns[] = {
- Opcode_l32ai_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_s32ri_encode_fns[] = {
- Opcode_s32ri_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_s32c1i_encode_fns[] = {
- Opcode_s32c1i_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rsr_scompare1_encode_fns[] = {
- Opcode_rsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wsr_scompare1_encode_fns[] = {
- Opcode_wsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_xsr_scompare1_encode_fns[] = {
- Opcode_xsr_scompare1_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_quou_encode_fns[] = {
- Opcode_quou_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_quos_encode_fns[] = {
- Opcode_quos_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_remu_encode_fns[] = {
- Opcode_remu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rems_encode_fns[] = {
- Opcode_rems_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mull_encode_fns[] = {
- Opcode_mull_Slot_inst_encode, 0, 0, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot0_encode, Opcode_mull_Slot_xt_flix64_slot1_encode, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_muluh_encode_fns[] = {
- Opcode_muluh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mulsh_encode_fns[] = {
- Opcode_mulsh_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rur_fcr_encode_fns[] = {
- Opcode_rur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wur_fcr_encode_fns[] = {
- Opcode_wur_fcr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rur_fsr_encode_fns[] = {
- Opcode_rur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wur_fsr_encode_fns[] = {
- Opcode_wur_fsr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_add_s_encode_fns[] = {
- Opcode_add_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_sub_s_encode_fns[] = {
- Opcode_sub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mul_s_encode_fns[] = {
- Opcode_mul_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_madd_s_encode_fns[] = {
- Opcode_madd_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_msub_s_encode_fns[] = {
- Opcode_msub_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movf_s_encode_fns[] = {
- Opcode_movf_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movt_s_encode_fns[] = {
- Opcode_movt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_moveqz_s_encode_fns[] = {
- Opcode_moveqz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movnez_s_encode_fns[] = {
- Opcode_movnez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movltz_s_encode_fns[] = {
- Opcode_movltz_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_movgez_s_encode_fns[] = {
- Opcode_movgez_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_abs_s_encode_fns[] = {
- Opcode_abs_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_mov_s_encode_fns[] = {
- Opcode_mov_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_neg_s_encode_fns[] = {
- Opcode_neg_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_un_s_encode_fns[] = {
- Opcode_un_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_oeq_s_encode_fns[] = {
- Opcode_oeq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ueq_s_encode_fns[] = {
- Opcode_ueq_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_olt_s_encode_fns[] = {
- Opcode_olt_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ult_s_encode_fns[] = {
- Opcode_ult_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ole_s_encode_fns[] = {
- Opcode_ole_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ule_s_encode_fns[] = {
- Opcode_ule_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_float_s_encode_fns[] = {
- Opcode_float_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ufloat_s_encode_fns[] = {
- Opcode_ufloat_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_round_s_encode_fns[] = {
- Opcode_round_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ceil_s_encode_fns[] = {
- Opcode_ceil_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_floor_s_encode_fns[] = {
- Opcode_floor_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_trunc_s_encode_fns[] = {
- Opcode_trunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_utrunc_s_encode_fns[] = {
- Opcode_utrunc_s_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_rfr_encode_fns[] = {
- Opcode_rfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_wfr_encode_fns[] = {
- Opcode_wfr_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_lsi_encode_fns[] = {
- Opcode_lsi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_lsiu_encode_fns[] = {
- Opcode_lsiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_lsx_encode_fns[] = {
- Opcode_lsx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_lsxu_encode_fns[] = {
- Opcode_lsxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssi_encode_fns[] = {
- Opcode_ssi_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssiu_encode_fns[] = {
- Opcode_ssiu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssx_encode_fns[] = {
- Opcode_ssx_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_ssxu_encode_fns[] = {
- Opcode_ssxu_Slot_inst_encode, 0, 0, 0, 0, 0, 0, 0
- };
- const xtensa_opcode_encode_fn Opcode_beqz_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_beqz_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bnez_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bnez_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bgez_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bgez_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bltz_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bltz_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_beqi_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_beqi_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bnei_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bnei_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bgei_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bgei_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_blti_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_blti_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bgeui_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bgeui_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bltui_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bltui_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bbci_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bbci_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bbsi_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bbsi_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_beq_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_beq_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bne_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bne_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bge_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bge_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_blt_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_blt_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bgeu_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bgeu_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bltu_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bltu_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bany_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bany_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bnone_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bnone_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_ball_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_ball_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bnall_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bnall_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bbc_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bbc_w18_Slot_xt_flix64_slot3_encode
- };
- const xtensa_opcode_encode_fn Opcode_bbs_w18_encode_fns[] = {
- 0, 0, 0, 0, 0, 0, 0, Opcode_bbs_w18_Slot_xt_flix64_slot3_encode
- };
- /* Opcode table. */
- static xtensa_opcode_internal opcodes[] = {
- { "excw", 0 /* xt_iclass_excw */,
- 0,
- Opcode_excw_encode_fns, 0, 0 },
- { "rfe", 1 /* xt_iclass_rfe */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfe_encode_fns, 0, 0 },
- { "rfde", 2 /* xt_iclass_rfde */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfde_encode_fns, 0, 0 },
- { "syscall", 3 /* xt_iclass_syscall */,
- 0,
- Opcode_syscall_encode_fns, 0, 0 },
- { "simcall", 4 /* xt_iclass_simcall */,
- 0,
- Opcode_simcall_encode_fns, 0, 0 },
- { "call12", 5 /* xt_iclass_call12 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call12_encode_fns, 0, 0 },
- { "call8", 6 /* xt_iclass_call8 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call8_encode_fns, 0, 0 },
- { "call4", 7 /* xt_iclass_call4 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call4_encode_fns, 0, 0 },
- { "callx12", 8 /* xt_iclass_callx12 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx12_encode_fns, 0, 0 },
- { "callx8", 9 /* xt_iclass_callx8 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx8_encode_fns, 0, 0 },
- { "callx4", 10 /* xt_iclass_callx4 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx4_encode_fns, 0, 0 },
- { "entry", 11 /* xt_iclass_entry */,
- 0,
- Opcode_entry_encode_fns, 0, 0 },
- { "movsp", 12 /* xt_iclass_movsp */,
- 0,
- Opcode_movsp_encode_fns, 0, 0 },
- { "rotw", 13 /* xt_iclass_rotw */,
- 0,
- Opcode_rotw_encode_fns, 0, 0 },
- { "retw", 14 /* xt_iclass_retw */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_encode_fns, 0, 0 },
- { "retw.n", 14 /* xt_iclass_retw */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_retw_n_encode_fns, 0, 0 },
- { "rfwo", 15 /* xt_iclass_rfwou */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwo_encode_fns, 0, 0 },
- { "rfwu", 15 /* xt_iclass_rfwou */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfwu_encode_fns, 0, 0 },
- { "l32e", 16 /* xt_iclass_l32e */,
- 0,
- Opcode_l32e_encode_fns, 0, 0 },
- { "s32e", 17 /* xt_iclass_s32e */,
- 0,
- Opcode_s32e_encode_fns, 0, 0 },
- { "rsr.windowbase", 18 /* xt_iclass_rsr.windowbase */,
- 0,
- Opcode_rsr_windowbase_encode_fns, 0, 0 },
- { "wsr.windowbase", 19 /* xt_iclass_wsr.windowbase */,
- 0,
- Opcode_wsr_windowbase_encode_fns, 0, 0 },
- { "xsr.windowbase", 20 /* xt_iclass_xsr.windowbase */,
- 0,
- Opcode_xsr_windowbase_encode_fns, 0, 0 },
- { "rsr.windowstart", 21 /* xt_iclass_rsr.windowstart */,
- 0,
- Opcode_rsr_windowstart_encode_fns, 0, 0 },
- { "wsr.windowstart", 22 /* xt_iclass_wsr.windowstart */,
- 0,
- Opcode_wsr_windowstart_encode_fns, 0, 0 },
- { "xsr.windowstart", 23 /* xt_iclass_xsr.windowstart */,
- 0,
- Opcode_xsr_windowstart_encode_fns, 0, 0 },
- { "add.n", 24 /* xt_iclass_add.n */,
- 0,
- Opcode_add_n_encode_fns, 0, 0 },
- { "addi.n", 25 /* xt_iclass_addi.n */,
- 0,
- Opcode_addi_n_encode_fns, 0, 0 },
- { "beqz.n", 26 /* xt_iclass_bz6 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_n_encode_fns, 0, 0 },
- { "bnez.n", 26 /* xt_iclass_bz6 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_n_encode_fns, 0, 0 },
- { "ill.n", 27 /* xt_iclass_ill.n */,
- 0,
- Opcode_ill_n_encode_fns, 0, 0 },
- { "l32i.n", 28 /* xt_iclass_loadi4 */,
- 0,
- Opcode_l32i_n_encode_fns, 0, 0 },
- { "mov.n", 29 /* xt_iclass_mov.n */,
- 0,
- Opcode_mov_n_encode_fns, 0, 0 },
- { "movi.n", 30 /* xt_iclass_movi.n */,
- 0,
- Opcode_movi_n_encode_fns, 0, 0 },
- { "nop.n", 31 /* xt_iclass_nopn */,
- 0,
- Opcode_nop_n_encode_fns, 0, 0 },
- { "ret.n", 32 /* xt_iclass_retn */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_n_encode_fns, 0, 0 },
- { "s32i.n", 33 /* xt_iclass_storei4 */,
- 0,
- Opcode_s32i_n_encode_fns, 0, 0 },
- { "rur.threadptr", 34 /* rur_threadptr */,
- 0,
- Opcode_rur_threadptr_encode_fns, 0, 0 },
- { "wur.threadptr", 35 /* wur_threadptr */,
- 0,
- Opcode_wur_threadptr_encode_fns, 0, 0 },
- { "addi", 36 /* xt_iclass_addi */,
- 0,
- Opcode_addi_encode_fns, 0, 0 },
- { "addmi", 37 /* xt_iclass_addmi */,
- 0,
- Opcode_addmi_encode_fns, 0, 0 },
- { "add", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_add_encode_fns, 0, 0 },
- { "sub", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_sub_encode_fns, 0, 0 },
- { "addx2", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_addx2_encode_fns, 0, 0 },
- { "addx4", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_addx4_encode_fns, 0, 0 },
- { "addx8", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_addx8_encode_fns, 0, 0 },
- { "subx2", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_subx2_encode_fns, 0, 0 },
- { "subx4", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_subx4_encode_fns, 0, 0 },
- { "subx8", 38 /* xt_iclass_addsub */,
- 0,
- Opcode_subx8_encode_fns, 0, 0 },
- { "and", 39 /* xt_iclass_bit */,
- 0,
- Opcode_and_encode_fns, 0, 0 },
- { "or", 39 /* xt_iclass_bit */,
- 0,
- Opcode_or_encode_fns, 0, 0 },
- { "xor", 39 /* xt_iclass_bit */,
- 0,
- Opcode_xor_encode_fns, 0, 0 },
- { "beqi", 40 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_encode_fns, 0, 0 },
- { "bnei", 40 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_encode_fns, 0, 0 },
- { "bgei", 40 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_encode_fns, 0, 0 },
- { "blti", 40 /* xt_iclass_bsi8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_encode_fns, 0, 0 },
- { "bbci", 41 /* xt_iclass_bsi8b */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_encode_fns, 0, 0 },
- { "bbsi", 41 /* xt_iclass_bsi8b */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_encode_fns, 0, 0 },
- { "bgeui", 42 /* xt_iclass_bsi8u */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_encode_fns, 0, 0 },
- { "bltui", 42 /* xt_iclass_bsi8u */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_encode_fns, 0, 0 },
- { "beq", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_encode_fns, 0, 0 },
- { "bne", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_encode_fns, 0, 0 },
- { "bge", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_encode_fns, 0, 0 },
- { "blt", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_encode_fns, 0, 0 },
- { "bgeu", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_encode_fns, 0, 0 },
- { "bltu", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_encode_fns, 0, 0 },
- { "bany", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_encode_fns, 0, 0 },
- { "bnone", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_encode_fns, 0, 0 },
- { "ball", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_encode_fns, 0, 0 },
- { "bnall", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_encode_fns, 0, 0 },
- { "bbc", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_encode_fns, 0, 0 },
- { "bbs", 43 /* xt_iclass_bst8 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_encode_fns, 0, 0 },
- { "beqz", 44 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_encode_fns, 0, 0 },
- { "bnez", 44 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_encode_fns, 0, 0 },
- { "bgez", 44 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_encode_fns, 0, 0 },
- { "bltz", 44 /* xt_iclass_bsz12 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_encode_fns, 0, 0 },
- { "call0", 45 /* xt_iclass_call0 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_call0_encode_fns, 0, 0 },
- { "callx0", 46 /* xt_iclass_callx0 */,
- XTENSA_OPCODE_IS_CALL,
- Opcode_callx0_encode_fns, 0, 0 },
- { "extui", 47 /* xt_iclass_exti */,
- 0,
- Opcode_extui_encode_fns, 0, 0 },
- { "ill", 48 /* xt_iclass_ill */,
- 0,
- Opcode_ill_encode_fns, 0, 0 },
- { "j", 49 /* xt_iclass_jump */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_j_encode_fns, 0, 0 },
- { "jx", 50 /* xt_iclass_jumpx */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_jx_encode_fns, 0, 0 },
- { "l16ui", 51 /* xt_iclass_l16ui */,
- 0,
- Opcode_l16ui_encode_fns, 0, 0 },
- { "l16si", 52 /* xt_iclass_l16si */,
- 0,
- Opcode_l16si_encode_fns, 0, 0 },
- { "l32i", 53 /* xt_iclass_l32i */,
- 0,
- Opcode_l32i_encode_fns, 0, 0 },
- { "l32r", 54 /* xt_iclass_l32r */,
- 0,
- Opcode_l32r_encode_fns, 0, 0 },
- { "l8ui", 55 /* xt_iclass_l8i */,
- 0,
- Opcode_l8ui_encode_fns, 0, 0 },
- { "loop", 56 /* xt_iclass_loop */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loop_encode_fns, 0, 0 },
- { "loopnez", 57 /* xt_iclass_loopz */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopnez_encode_fns, 0, 0 },
- { "loopgtz", 57 /* xt_iclass_loopz */,
- XTENSA_OPCODE_IS_LOOP,
- Opcode_loopgtz_encode_fns, 0, 0 },
- { "movi", 58 /* xt_iclass_movi */,
- 0,
- Opcode_movi_encode_fns, 0, 0 },
- { "moveqz", 59 /* xt_iclass_movz */,
- 0,
- Opcode_moveqz_encode_fns, 0, 0 },
- { "movnez", 59 /* xt_iclass_movz */,
- 0,
- Opcode_movnez_encode_fns, 0, 0 },
- { "movltz", 59 /* xt_iclass_movz */,
- 0,
- Opcode_movltz_encode_fns, 0, 0 },
- { "movgez", 59 /* xt_iclass_movz */,
- 0,
- Opcode_movgez_encode_fns, 0, 0 },
- { "neg", 60 /* xt_iclass_neg */,
- 0,
- Opcode_neg_encode_fns, 0, 0 },
- { "abs", 60 /* xt_iclass_neg */,
- 0,
- Opcode_abs_encode_fns, 0, 0 },
- { "nop", 61 /* xt_iclass_nop */,
- 0,
- Opcode_nop_encode_fns, 0, 0 },
- { "ret", 62 /* xt_iclass_return */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_ret_encode_fns, 0, 0 },
- { "s16i", 63 /* xt_iclass_s16i */,
- 0,
- Opcode_s16i_encode_fns, 0, 0 },
- { "s32i", 64 /* xt_iclass_s32i */,
- 0,
- Opcode_s32i_encode_fns, 0, 0 },
- { "s8i", 65 /* xt_iclass_s8i */,
- 0,
- Opcode_s8i_encode_fns, 0, 0 },
- { "ssr", 66 /* xt_iclass_sar */,
- 0,
- Opcode_ssr_encode_fns, 0, 0 },
- { "ssl", 66 /* xt_iclass_sar */,
- 0,
- Opcode_ssl_encode_fns, 0, 0 },
- { "ssa8l", 66 /* xt_iclass_sar */,
- 0,
- Opcode_ssa8l_encode_fns, 0, 0 },
- { "ssa8b", 66 /* xt_iclass_sar */,
- 0,
- Opcode_ssa8b_encode_fns, 0, 0 },
- { "ssai", 67 /* xt_iclass_sari */,
- 0,
- Opcode_ssai_encode_fns, 0, 0 },
- { "sll", 68 /* xt_iclass_shifts */,
- 0,
- Opcode_sll_encode_fns, 0, 0 },
- { "src", 69 /* xt_iclass_shiftst */,
- 0,
- Opcode_src_encode_fns, 0, 0 },
- { "srl", 70 /* xt_iclass_shiftt */,
- 0,
- Opcode_srl_encode_fns, 0, 0 },
- { "sra", 70 /* xt_iclass_shiftt */,
- 0,
- Opcode_sra_encode_fns, 0, 0 },
- { "slli", 71 /* xt_iclass_slli */,
- 0,
- Opcode_slli_encode_fns, 0, 0 },
- { "srai", 72 /* xt_iclass_srai */,
- 0,
- Opcode_srai_encode_fns, 0, 0 },
- { "srli", 73 /* xt_iclass_srli */,
- 0,
- Opcode_srli_encode_fns, 0, 0 },
- { "memw", 74 /* xt_iclass_memw */,
- 0,
- Opcode_memw_encode_fns, 0, 0 },
- { "extw", 75 /* xt_iclass_extw */,
- 0,
- Opcode_extw_encode_fns, 0, 0 },
- { "isync", 76 /* xt_iclass_isync */,
- 0,
- Opcode_isync_encode_fns, 0, 0 },
- { "rsync", 77 /* xt_iclass_sync */,
- 0,
- Opcode_rsync_encode_fns, 0, 0 },
- { "esync", 77 /* xt_iclass_sync */,
- 0,
- Opcode_esync_encode_fns, 0, 0 },
- { "dsync", 77 /* xt_iclass_sync */,
- 0,
- Opcode_dsync_encode_fns, 0, 0 },
- { "rsil", 78 /* xt_iclass_rsil */,
- 0,
- Opcode_rsil_encode_fns, 0, 0 },
- { "rsr.lend", 79 /* xt_iclass_rsr.lend */,
- 0,
- Opcode_rsr_lend_encode_fns, 0, 0 },
- { "wsr.lend", 80 /* xt_iclass_wsr.lend */,
- 0,
- Opcode_wsr_lend_encode_fns, 0, 0 },
- { "xsr.lend", 81 /* xt_iclass_xsr.lend */,
- 0,
- Opcode_xsr_lend_encode_fns, 0, 0 },
- { "rsr.lcount", 82 /* xt_iclass_rsr.lcount */,
- 0,
- Opcode_rsr_lcount_encode_fns, 0, 0 },
- { "wsr.lcount", 83 /* xt_iclass_wsr.lcount */,
- 0,
- Opcode_wsr_lcount_encode_fns, 0, 0 },
- { "xsr.lcount", 84 /* xt_iclass_xsr.lcount */,
- 0,
- Opcode_xsr_lcount_encode_fns, 0, 0 },
- { "rsr.lbeg", 85 /* xt_iclass_rsr.lbeg */,
- 0,
- Opcode_rsr_lbeg_encode_fns, 0, 0 },
- { "wsr.lbeg", 86 /* xt_iclass_wsr.lbeg */,
- 0,
- Opcode_wsr_lbeg_encode_fns, 0, 0 },
- { "xsr.lbeg", 87 /* xt_iclass_xsr.lbeg */,
- 0,
- Opcode_xsr_lbeg_encode_fns, 0, 0 },
- { "rsr.sar", 88 /* xt_iclass_rsr.sar */,
- 0,
- Opcode_rsr_sar_encode_fns, 0, 0 },
- { "wsr.sar", 89 /* xt_iclass_wsr.sar */,
- 0,
- Opcode_wsr_sar_encode_fns, 0, 0 },
- { "xsr.sar", 90 /* xt_iclass_xsr.sar */,
- 0,
- Opcode_xsr_sar_encode_fns, 0, 0 },
- { "rsr.litbase", 91 /* xt_iclass_rsr.litbase */,
- 0,
- Opcode_rsr_litbase_encode_fns, 0, 0 },
- { "wsr.litbase", 92 /* xt_iclass_wsr.litbase */,
- 0,
- Opcode_wsr_litbase_encode_fns, 0, 0 },
- { "xsr.litbase", 93 /* xt_iclass_xsr.litbase */,
- 0,
- Opcode_xsr_litbase_encode_fns, 0, 0 },
- { "rsr.176", 94 /* xt_iclass_rsr.176 */,
- 0,
- Opcode_rsr_176_encode_fns, 0, 0 },
- { "rsr.208", 95 /* xt_iclass_rsr.208 */,
- 0,
- Opcode_rsr_208_encode_fns, 0, 0 },
- { "rsr.ps", 96 /* xt_iclass_rsr.ps */,
- 0,
- Opcode_rsr_ps_encode_fns, 0, 0 },
- { "wsr.ps", 97 /* xt_iclass_wsr.ps */,
- 0,
- Opcode_wsr_ps_encode_fns, 0, 0 },
- { "xsr.ps", 98 /* xt_iclass_xsr.ps */,
- 0,
- Opcode_xsr_ps_encode_fns, 0, 0 },
- { "rsr.epc1", 99 /* xt_iclass_rsr.epc1 */,
- 0,
- Opcode_rsr_epc1_encode_fns, 0, 0 },
- { "wsr.epc1", 100 /* xt_iclass_wsr.epc1 */,
- 0,
- Opcode_wsr_epc1_encode_fns, 0, 0 },
- { "xsr.epc1", 101 /* xt_iclass_xsr.epc1 */,
- 0,
- Opcode_xsr_epc1_encode_fns, 0, 0 },
- { "rsr.excsave1", 102 /* xt_iclass_rsr.excsave1 */,
- 0,
- Opcode_rsr_excsave1_encode_fns, 0, 0 },
- { "wsr.excsave1", 103 /* xt_iclass_wsr.excsave1 */,
- 0,
- Opcode_wsr_excsave1_encode_fns, 0, 0 },
- { "xsr.excsave1", 104 /* xt_iclass_xsr.excsave1 */,
- 0,
- Opcode_xsr_excsave1_encode_fns, 0, 0 },
- { "rsr.epc2", 105 /* xt_iclass_rsr.epc2 */,
- 0,
- Opcode_rsr_epc2_encode_fns, 0, 0 },
- { "wsr.epc2", 106 /* xt_iclass_wsr.epc2 */,
- 0,
- Opcode_wsr_epc2_encode_fns, 0, 0 },
- { "xsr.epc2", 107 /* xt_iclass_xsr.epc2 */,
- 0,
- Opcode_xsr_epc2_encode_fns, 0, 0 },
- { "rsr.excsave2", 108 /* xt_iclass_rsr.excsave2 */,
- 0,
- Opcode_rsr_excsave2_encode_fns, 0, 0 },
- { "wsr.excsave2", 109 /* xt_iclass_wsr.excsave2 */,
- 0,
- Opcode_wsr_excsave2_encode_fns, 0, 0 },
- { "xsr.excsave2", 110 /* xt_iclass_xsr.excsave2 */,
- 0,
- Opcode_xsr_excsave2_encode_fns, 0, 0 },
- { "rsr.epc3", 111 /* xt_iclass_rsr.epc3 */,
- 0,
- Opcode_rsr_epc3_encode_fns, 0, 0 },
- { "wsr.epc3", 112 /* xt_iclass_wsr.epc3 */,
- 0,
- Opcode_wsr_epc3_encode_fns, 0, 0 },
- { "xsr.epc3", 113 /* xt_iclass_xsr.epc3 */,
- 0,
- Opcode_xsr_epc3_encode_fns, 0, 0 },
- { "rsr.excsave3", 114 /* xt_iclass_rsr.excsave3 */,
- 0,
- Opcode_rsr_excsave3_encode_fns, 0, 0 },
- { "wsr.excsave3", 115 /* xt_iclass_wsr.excsave3 */,
- 0,
- Opcode_wsr_excsave3_encode_fns, 0, 0 },
- { "xsr.excsave3", 116 /* xt_iclass_xsr.excsave3 */,
- 0,
- Opcode_xsr_excsave3_encode_fns, 0, 0 },
- { "rsr.epc4", 117 /* xt_iclass_rsr.epc4 */,
- 0,
- Opcode_rsr_epc4_encode_fns, 0, 0 },
- { "wsr.epc4", 118 /* xt_iclass_wsr.epc4 */,
- 0,
- Opcode_wsr_epc4_encode_fns, 0, 0 },
- { "xsr.epc4", 119 /* xt_iclass_xsr.epc4 */,
- 0,
- Opcode_xsr_epc4_encode_fns, 0, 0 },
- { "rsr.excsave4", 120 /* xt_iclass_rsr.excsave4 */,
- 0,
- Opcode_rsr_excsave4_encode_fns, 0, 0 },
- { "wsr.excsave4", 121 /* xt_iclass_wsr.excsave4 */,
- 0,
- Opcode_wsr_excsave4_encode_fns, 0, 0 },
- { "xsr.excsave4", 122 /* xt_iclass_xsr.excsave4 */,
- 0,
- Opcode_xsr_excsave4_encode_fns, 0, 0 },
- { "rsr.epc5", 123 /* xt_iclass_rsr.epc5 */,
- 0,
- Opcode_rsr_epc5_encode_fns, 0, 0 },
- { "wsr.epc5", 124 /* xt_iclass_wsr.epc5 */,
- 0,
- Opcode_wsr_epc5_encode_fns, 0, 0 },
- { "xsr.epc5", 125 /* xt_iclass_xsr.epc5 */,
- 0,
- Opcode_xsr_epc5_encode_fns, 0, 0 },
- { "rsr.excsave5", 126 /* xt_iclass_rsr.excsave5 */,
- 0,
- Opcode_rsr_excsave5_encode_fns, 0, 0 },
- { "wsr.excsave5", 127 /* xt_iclass_wsr.excsave5 */,
- 0,
- Opcode_wsr_excsave5_encode_fns, 0, 0 },
- { "xsr.excsave5", 128 /* xt_iclass_xsr.excsave5 */,
- 0,
- Opcode_xsr_excsave5_encode_fns, 0, 0 },
- { "rsr.epc6", 129 /* xt_iclass_rsr.epc6 */,
- 0,
- Opcode_rsr_epc6_encode_fns, 0, 0 },
- { "wsr.epc6", 130 /* xt_iclass_wsr.epc6 */,
- 0,
- Opcode_wsr_epc6_encode_fns, 0, 0 },
- { "xsr.epc6", 131 /* xt_iclass_xsr.epc6 */,
- 0,
- Opcode_xsr_epc6_encode_fns, 0, 0 },
- { "rsr.excsave6", 132 /* xt_iclass_rsr.excsave6 */,
- 0,
- Opcode_rsr_excsave6_encode_fns, 0, 0 },
- { "wsr.excsave6", 133 /* xt_iclass_wsr.excsave6 */,
- 0,
- Opcode_wsr_excsave6_encode_fns, 0, 0 },
- { "xsr.excsave6", 134 /* xt_iclass_xsr.excsave6 */,
- 0,
- Opcode_xsr_excsave6_encode_fns, 0, 0 },
- { "rsr.epc7", 135 /* xt_iclass_rsr.epc7 */,
- 0,
- Opcode_rsr_epc7_encode_fns, 0, 0 },
- { "wsr.epc7", 136 /* xt_iclass_wsr.epc7 */,
- 0,
- Opcode_wsr_epc7_encode_fns, 0, 0 },
- { "xsr.epc7", 137 /* xt_iclass_xsr.epc7 */,
- 0,
- Opcode_xsr_epc7_encode_fns, 0, 0 },
- { "rsr.excsave7", 138 /* xt_iclass_rsr.excsave7 */,
- 0,
- Opcode_rsr_excsave7_encode_fns, 0, 0 },
- { "wsr.excsave7", 139 /* xt_iclass_wsr.excsave7 */,
- 0,
- Opcode_wsr_excsave7_encode_fns, 0, 0 },
- { "xsr.excsave7", 140 /* xt_iclass_xsr.excsave7 */,
- 0,
- Opcode_xsr_excsave7_encode_fns, 0, 0 },
- { "rsr.eps2", 141 /* xt_iclass_rsr.eps2 */,
- 0,
- Opcode_rsr_eps2_encode_fns, 0, 0 },
- { "wsr.eps2", 142 /* xt_iclass_wsr.eps2 */,
- 0,
- Opcode_wsr_eps2_encode_fns, 0, 0 },
- { "xsr.eps2", 143 /* xt_iclass_xsr.eps2 */,
- 0,
- Opcode_xsr_eps2_encode_fns, 0, 0 },
- { "rsr.eps3", 144 /* xt_iclass_rsr.eps3 */,
- 0,
- Opcode_rsr_eps3_encode_fns, 0, 0 },
- { "wsr.eps3", 145 /* xt_iclass_wsr.eps3 */,
- 0,
- Opcode_wsr_eps3_encode_fns, 0, 0 },
- { "xsr.eps3", 146 /* xt_iclass_xsr.eps3 */,
- 0,
- Opcode_xsr_eps3_encode_fns, 0, 0 },
- { "rsr.eps4", 147 /* xt_iclass_rsr.eps4 */,
- 0,
- Opcode_rsr_eps4_encode_fns, 0, 0 },
- { "wsr.eps4", 148 /* xt_iclass_wsr.eps4 */,
- 0,
- Opcode_wsr_eps4_encode_fns, 0, 0 },
- { "xsr.eps4", 149 /* xt_iclass_xsr.eps4 */,
- 0,
- Opcode_xsr_eps4_encode_fns, 0, 0 },
- { "rsr.eps5", 150 /* xt_iclass_rsr.eps5 */,
- 0,
- Opcode_rsr_eps5_encode_fns, 0, 0 },
- { "wsr.eps5", 151 /* xt_iclass_wsr.eps5 */,
- 0,
- Opcode_wsr_eps5_encode_fns, 0, 0 },
- { "xsr.eps5", 152 /* xt_iclass_xsr.eps5 */,
- 0,
- Opcode_xsr_eps5_encode_fns, 0, 0 },
- { "rsr.eps6", 153 /* xt_iclass_rsr.eps6 */,
- 0,
- Opcode_rsr_eps6_encode_fns, 0, 0 },
- { "wsr.eps6", 154 /* xt_iclass_wsr.eps6 */,
- 0,
- Opcode_wsr_eps6_encode_fns, 0, 0 },
- { "xsr.eps6", 155 /* xt_iclass_xsr.eps6 */,
- 0,
- Opcode_xsr_eps6_encode_fns, 0, 0 },
- { "rsr.eps7", 156 /* xt_iclass_rsr.eps7 */,
- 0,
- Opcode_rsr_eps7_encode_fns, 0, 0 },
- { "wsr.eps7", 157 /* xt_iclass_wsr.eps7 */,
- 0,
- Opcode_wsr_eps7_encode_fns, 0, 0 },
- { "xsr.eps7", 158 /* xt_iclass_xsr.eps7 */,
- 0,
- Opcode_xsr_eps7_encode_fns, 0, 0 },
- { "rsr.excvaddr", 159 /* xt_iclass_rsr.excvaddr */,
- 0,
- Opcode_rsr_excvaddr_encode_fns, 0, 0 },
- { "wsr.excvaddr", 160 /* xt_iclass_wsr.excvaddr */,
- 0,
- Opcode_wsr_excvaddr_encode_fns, 0, 0 },
- { "xsr.excvaddr", 161 /* xt_iclass_xsr.excvaddr */,
- 0,
- Opcode_xsr_excvaddr_encode_fns, 0, 0 },
- { "rsr.depc", 162 /* xt_iclass_rsr.depc */,
- 0,
- Opcode_rsr_depc_encode_fns, 0, 0 },
- { "wsr.depc", 163 /* xt_iclass_wsr.depc */,
- 0,
- Opcode_wsr_depc_encode_fns, 0, 0 },
- { "xsr.depc", 164 /* xt_iclass_xsr.depc */,
- 0,
- Opcode_xsr_depc_encode_fns, 0, 0 },
- { "rsr.exccause", 165 /* xt_iclass_rsr.exccause */,
- 0,
- Opcode_rsr_exccause_encode_fns, 0, 0 },
- { "wsr.exccause", 166 /* xt_iclass_wsr.exccause */,
- 0,
- Opcode_wsr_exccause_encode_fns, 0, 0 },
- { "xsr.exccause", 167 /* xt_iclass_xsr.exccause */,
- 0,
- Opcode_xsr_exccause_encode_fns, 0, 0 },
- { "rsr.misc0", 168 /* xt_iclass_rsr.misc0 */,
- 0,
- Opcode_rsr_misc0_encode_fns, 0, 0 },
- { "wsr.misc0", 169 /* xt_iclass_wsr.misc0 */,
- 0,
- Opcode_wsr_misc0_encode_fns, 0, 0 },
- { "xsr.misc0", 170 /* xt_iclass_xsr.misc0 */,
- 0,
- Opcode_xsr_misc0_encode_fns, 0, 0 },
- { "rsr.misc1", 171 /* xt_iclass_rsr.misc1 */,
- 0,
- Opcode_rsr_misc1_encode_fns, 0, 0 },
- { "wsr.misc1", 172 /* xt_iclass_wsr.misc1 */,
- 0,
- Opcode_wsr_misc1_encode_fns, 0, 0 },
- { "xsr.misc1", 173 /* xt_iclass_xsr.misc1 */,
- 0,
- Opcode_xsr_misc1_encode_fns, 0, 0 },
- { "rsr.misc2", 174 /* xt_iclass_rsr.misc2 */,
- 0,
- Opcode_rsr_misc2_encode_fns, 0, 0 },
- { "wsr.misc2", 175 /* xt_iclass_wsr.misc2 */,
- 0,
- Opcode_wsr_misc2_encode_fns, 0, 0 },
- { "xsr.misc2", 176 /* xt_iclass_xsr.misc2 */,
- 0,
- Opcode_xsr_misc2_encode_fns, 0, 0 },
- { "rsr.misc3", 177 /* xt_iclass_rsr.misc3 */,
- 0,
- Opcode_rsr_misc3_encode_fns, 0, 0 },
- { "wsr.misc3", 178 /* xt_iclass_wsr.misc3 */,
- 0,
- Opcode_wsr_misc3_encode_fns, 0, 0 },
- { "xsr.misc3", 179 /* xt_iclass_xsr.misc3 */,
- 0,
- Opcode_xsr_misc3_encode_fns, 0, 0 },
- { "rsr.prid", 180 /* xt_iclass_rsr.prid */,
- 0,
- Opcode_rsr_prid_encode_fns, 0, 0 },
- { "rsr.vecbase", 181 /* xt_iclass_rsr.vecbase */,
- 0,
- Opcode_rsr_vecbase_encode_fns, 0, 0 },
- { "wsr.vecbase", 182 /* xt_iclass_wsr.vecbase */,
- 0,
- Opcode_wsr_vecbase_encode_fns, 0, 0 },
- { "xsr.vecbase", 183 /* xt_iclass_xsr.vecbase */,
- 0,
- Opcode_xsr_vecbase_encode_fns, 0, 0 },
- { "mul.aa.ll", 184 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_mul_aa_ll_encode_fns, 0, 0 },
- { "mul.aa.hl", 184 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_mul_aa_hl_encode_fns, 0, 0 },
- { "mul.aa.lh", 184 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_mul_aa_lh_encode_fns, 0, 0 },
- { "mul.aa.hh", 184 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_mul_aa_hh_encode_fns, 0, 0 },
- { "umul.aa.ll", 184 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_umul_aa_ll_encode_fns, 0, 0 },
- { "umul.aa.hl", 184 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_umul_aa_hl_encode_fns, 0, 0 },
- { "umul.aa.lh", 184 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_umul_aa_lh_encode_fns, 0, 0 },
- { "umul.aa.hh", 184 /* xt_iclass_mac16_aa */,
- 0,
- Opcode_umul_aa_hh_encode_fns, 0, 0 },
- { "mul.ad.ll", 185 /* xt_iclass_mac16_ad */,
- 0,
- Opcode_mul_ad_ll_encode_fns, 0, 0 },
- { "mul.ad.hl", 185 /* xt_iclass_mac16_ad */,
- 0,
- Opcode_mul_ad_hl_encode_fns, 0, 0 },
- { "mul.ad.lh", 185 /* xt_iclass_mac16_ad */,
- 0,
- Opcode_mul_ad_lh_encode_fns, 0, 0 },
- { "mul.ad.hh", 185 /* xt_iclass_mac16_ad */,
- 0,
- Opcode_mul_ad_hh_encode_fns, 0, 0 },
- { "mul.da.ll", 186 /* xt_iclass_mac16_da */,
- 0,
- Opcode_mul_da_ll_encode_fns, 0, 0 },
- { "mul.da.hl", 186 /* xt_iclass_mac16_da */,
- 0,
- Opcode_mul_da_hl_encode_fns, 0, 0 },
- { "mul.da.lh", 186 /* xt_iclass_mac16_da */,
- 0,
- Opcode_mul_da_lh_encode_fns, 0, 0 },
- { "mul.da.hh", 186 /* xt_iclass_mac16_da */,
- 0,
- Opcode_mul_da_hh_encode_fns, 0, 0 },
- { "mul.dd.ll", 187 /* xt_iclass_mac16_dd */,
- 0,
- Opcode_mul_dd_ll_encode_fns, 0, 0 },
- { "mul.dd.hl", 187 /* xt_iclass_mac16_dd */,
- 0,
- Opcode_mul_dd_hl_encode_fns, 0, 0 },
- { "mul.dd.lh", 187 /* xt_iclass_mac16_dd */,
- 0,
- Opcode_mul_dd_lh_encode_fns, 0, 0 },
- { "mul.dd.hh", 187 /* xt_iclass_mac16_dd */,
- 0,
- Opcode_mul_dd_hh_encode_fns, 0, 0 },
- { "mula.aa.ll", 188 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_mula_aa_ll_encode_fns, 0, 0 },
- { "mula.aa.hl", 188 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_mula_aa_hl_encode_fns, 0, 0 },
- { "mula.aa.lh", 188 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_mula_aa_lh_encode_fns, 0, 0 },
- { "mula.aa.hh", 188 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_mula_aa_hh_encode_fns, 0, 0 },
- { "muls.aa.ll", 188 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_muls_aa_ll_encode_fns, 0, 0 },
- { "muls.aa.hl", 188 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_muls_aa_hl_encode_fns, 0, 0 },
- { "muls.aa.lh", 188 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_muls_aa_lh_encode_fns, 0, 0 },
- { "muls.aa.hh", 188 /* xt_iclass_mac16a_aa */,
- 0,
- Opcode_muls_aa_hh_encode_fns, 0, 0 },
- { "mula.ad.ll", 189 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_mula_ad_ll_encode_fns, 0, 0 },
- { "mula.ad.hl", 189 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_mula_ad_hl_encode_fns, 0, 0 },
- { "mula.ad.lh", 189 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_mula_ad_lh_encode_fns, 0, 0 },
- { "mula.ad.hh", 189 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_mula_ad_hh_encode_fns, 0, 0 },
- { "muls.ad.ll", 189 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_muls_ad_ll_encode_fns, 0, 0 },
- { "muls.ad.hl", 189 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_muls_ad_hl_encode_fns, 0, 0 },
- { "muls.ad.lh", 189 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_muls_ad_lh_encode_fns, 0, 0 },
- { "muls.ad.hh", 189 /* xt_iclass_mac16a_ad */,
- 0,
- Opcode_muls_ad_hh_encode_fns, 0, 0 },
- { "mula.da.ll", 190 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_mula_da_ll_encode_fns, 0, 0 },
- { "mula.da.hl", 190 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_mula_da_hl_encode_fns, 0, 0 },
- { "mula.da.lh", 190 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_mula_da_lh_encode_fns, 0, 0 },
- { "mula.da.hh", 190 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_mula_da_hh_encode_fns, 0, 0 },
- { "muls.da.ll", 190 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_muls_da_ll_encode_fns, 0, 0 },
- { "muls.da.hl", 190 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_muls_da_hl_encode_fns, 0, 0 },
- { "muls.da.lh", 190 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_muls_da_lh_encode_fns, 0, 0 },
- { "muls.da.hh", 190 /* xt_iclass_mac16a_da */,
- 0,
- Opcode_muls_da_hh_encode_fns, 0, 0 },
- { "mula.dd.ll", 191 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_mula_dd_ll_encode_fns, 0, 0 },
- { "mula.dd.hl", 191 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_mula_dd_hl_encode_fns, 0, 0 },
- { "mula.dd.lh", 191 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_mula_dd_lh_encode_fns, 0, 0 },
- { "mula.dd.hh", 191 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_mula_dd_hh_encode_fns, 0, 0 },
- { "muls.dd.ll", 191 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_muls_dd_ll_encode_fns, 0, 0 },
- { "muls.dd.hl", 191 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_muls_dd_hl_encode_fns, 0, 0 },
- { "muls.dd.lh", 191 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_muls_dd_lh_encode_fns, 0, 0 },
- { "muls.dd.hh", 191 /* xt_iclass_mac16a_dd */,
- 0,
- Opcode_muls_dd_hh_encode_fns, 0, 0 },
- { "mula.da.ll.lddec", 192 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_ll_lddec_encode_fns, 0, 0 },
- { "mula.da.ll.ldinc", 192 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_ll_ldinc_encode_fns, 0, 0 },
- { "mula.da.hl.lddec", 192 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_hl_lddec_encode_fns, 0, 0 },
- { "mula.da.hl.ldinc", 192 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_hl_ldinc_encode_fns, 0, 0 },
- { "mula.da.lh.lddec", 192 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_lh_lddec_encode_fns, 0, 0 },
- { "mula.da.lh.ldinc", 192 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_lh_ldinc_encode_fns, 0, 0 },
- { "mula.da.hh.lddec", 192 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_hh_lddec_encode_fns, 0, 0 },
- { "mula.da.hh.ldinc", 192 /* xt_iclass_mac16al_da */,
- 0,
- Opcode_mula_da_hh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.ll.lddec", 193 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_ll_lddec_encode_fns, 0, 0 },
- { "mula.dd.ll.ldinc", 193 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_ll_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hl.lddec", 193 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_hl_lddec_encode_fns, 0, 0 },
- { "mula.dd.hl.ldinc", 193 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_hl_ldinc_encode_fns, 0, 0 },
- { "mula.dd.lh.lddec", 193 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_lh_lddec_encode_fns, 0, 0 },
- { "mula.dd.lh.ldinc", 193 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_lh_ldinc_encode_fns, 0, 0 },
- { "mula.dd.hh.lddec", 193 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_hh_lddec_encode_fns, 0, 0 },
- { "mula.dd.hh.ldinc", 193 /* xt_iclass_mac16al_dd */,
- 0,
- Opcode_mula_dd_hh_ldinc_encode_fns, 0, 0 },
- { "lddec", 194 /* xt_iclass_mac16_l */,
- 0,
- Opcode_lddec_encode_fns, 0, 0 },
- { "ldinc", 194 /* xt_iclass_mac16_l */,
- 0,
- Opcode_ldinc_encode_fns, 0, 0 },
- { "mul16u", 195 /* xt_iclass_mul16 */,
- 0,
- Opcode_mul16u_encode_fns, 0, 0 },
- { "mul16s", 195 /* xt_iclass_mul16 */,
- 0,
- Opcode_mul16s_encode_fns, 0, 0 },
- { "rsr.m0", 196 /* xt_iclass_rsr.m0 */,
- 0,
- Opcode_rsr_m0_encode_fns, 0, 0 },
- { "wsr.m0", 197 /* xt_iclass_wsr.m0 */,
- 0,
- Opcode_wsr_m0_encode_fns, 0, 0 },
- { "xsr.m0", 198 /* xt_iclass_xsr.m0 */,
- 0,
- Opcode_xsr_m0_encode_fns, 0, 0 },
- { "rsr.m1", 199 /* xt_iclass_rsr.m1 */,
- 0,
- Opcode_rsr_m1_encode_fns, 0, 0 },
- { "wsr.m1", 200 /* xt_iclass_wsr.m1 */,
- 0,
- Opcode_wsr_m1_encode_fns, 0, 0 },
- { "xsr.m1", 201 /* xt_iclass_xsr.m1 */,
- 0,
- Opcode_xsr_m1_encode_fns, 0, 0 },
- { "rsr.m2", 202 /* xt_iclass_rsr.m2 */,
- 0,
- Opcode_rsr_m2_encode_fns, 0, 0 },
- { "wsr.m2", 203 /* xt_iclass_wsr.m2 */,
- 0,
- Opcode_wsr_m2_encode_fns, 0, 0 },
- { "xsr.m2", 204 /* xt_iclass_xsr.m2 */,
- 0,
- Opcode_xsr_m2_encode_fns, 0, 0 },
- { "rsr.m3", 205 /* xt_iclass_rsr.m3 */,
- 0,
- Opcode_rsr_m3_encode_fns, 0, 0 },
- { "wsr.m3", 206 /* xt_iclass_wsr.m3 */,
- 0,
- Opcode_wsr_m3_encode_fns, 0, 0 },
- { "xsr.m3", 207 /* xt_iclass_xsr.m3 */,
- 0,
- Opcode_xsr_m3_encode_fns, 0, 0 },
- { "rsr.acclo", 208 /* xt_iclass_rsr.acclo */,
- 0,
- Opcode_rsr_acclo_encode_fns, 0, 0 },
- { "wsr.acclo", 209 /* xt_iclass_wsr.acclo */,
- 0,
- Opcode_wsr_acclo_encode_fns, 0, 0 },
- { "xsr.acclo", 210 /* xt_iclass_xsr.acclo */,
- 0,
- Opcode_xsr_acclo_encode_fns, 0, 0 },
- { "rsr.acchi", 211 /* xt_iclass_rsr.acchi */,
- 0,
- Opcode_rsr_acchi_encode_fns, 0, 0 },
- { "wsr.acchi", 212 /* xt_iclass_wsr.acchi */,
- 0,
- Opcode_wsr_acchi_encode_fns, 0, 0 },
- { "xsr.acchi", 213 /* xt_iclass_xsr.acchi */,
- 0,
- Opcode_xsr_acchi_encode_fns, 0, 0 },
- { "rfi", 214 /* xt_iclass_rfi */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfi_encode_fns, 0, 0 },
- { "waiti", 215 /* xt_iclass_wait */,
- 0,
- Opcode_waiti_encode_fns, 0, 0 },
- { "rsr.interrupt", 216 /* xt_iclass_rsr.interrupt */,
- 0,
- Opcode_rsr_interrupt_encode_fns, 0, 0 },
- { "wsr.intset", 217 /* xt_iclass_wsr.intset */,
- 0,
- Opcode_wsr_intset_encode_fns, 0, 0 },
- { "wsr.intclear", 218 /* xt_iclass_wsr.intclear */,
- 0,
- Opcode_wsr_intclear_encode_fns, 0, 0 },
- { "rsr.intenable", 219 /* xt_iclass_rsr.intenable */,
- 0,
- Opcode_rsr_intenable_encode_fns, 0, 0 },
- { "wsr.intenable", 220 /* xt_iclass_wsr.intenable */,
- 0,
- Opcode_wsr_intenable_encode_fns, 0, 0 },
- { "xsr.intenable", 221 /* xt_iclass_xsr.intenable */,
- 0,
- Opcode_xsr_intenable_encode_fns, 0, 0 },
- { "break", 222 /* xt_iclass_break */,
- 0,
- Opcode_break_encode_fns, 0, 0 },
- { "break.n", 223 /* xt_iclass_break.n */,
- 0,
- Opcode_break_n_encode_fns, 0, 0 },
- { "rsr.dbreaka0", 224 /* xt_iclass_rsr.dbreaka0 */,
- 0,
- Opcode_rsr_dbreaka0_encode_fns, 0, 0 },
- { "wsr.dbreaka0", 225 /* xt_iclass_wsr.dbreaka0 */,
- 0,
- Opcode_wsr_dbreaka0_encode_fns, 0, 0 },
- { "xsr.dbreaka0", 226 /* xt_iclass_xsr.dbreaka0 */,
- 0,
- Opcode_xsr_dbreaka0_encode_fns, 0, 0 },
- { "rsr.dbreakc0", 227 /* xt_iclass_rsr.dbreakc0 */,
- 0,
- Opcode_rsr_dbreakc0_encode_fns, 0, 0 },
- { "wsr.dbreakc0", 228 /* xt_iclass_wsr.dbreakc0 */,
- 0,
- Opcode_wsr_dbreakc0_encode_fns, 0, 0 },
- { "xsr.dbreakc0", 229 /* xt_iclass_xsr.dbreakc0 */,
- 0,
- Opcode_xsr_dbreakc0_encode_fns, 0, 0 },
- { "rsr.dbreaka1", 230 /* xt_iclass_rsr.dbreaka1 */,
- 0,
- Opcode_rsr_dbreaka1_encode_fns, 0, 0 },
- { "wsr.dbreaka1", 231 /* xt_iclass_wsr.dbreaka1 */,
- 0,
- Opcode_wsr_dbreaka1_encode_fns, 0, 0 },
- { "xsr.dbreaka1", 232 /* xt_iclass_xsr.dbreaka1 */,
- 0,
- Opcode_xsr_dbreaka1_encode_fns, 0, 0 },
- { "rsr.dbreakc1", 233 /* xt_iclass_rsr.dbreakc1 */,
- 0,
- Opcode_rsr_dbreakc1_encode_fns, 0, 0 },
- { "wsr.dbreakc1", 234 /* xt_iclass_wsr.dbreakc1 */,
- 0,
- Opcode_wsr_dbreakc1_encode_fns, 0, 0 },
- { "xsr.dbreakc1", 235 /* xt_iclass_xsr.dbreakc1 */,
- 0,
- Opcode_xsr_dbreakc1_encode_fns, 0, 0 },
- { "rsr.ibreaka0", 236 /* xt_iclass_rsr.ibreaka0 */,
- 0,
- Opcode_rsr_ibreaka0_encode_fns, 0, 0 },
- { "wsr.ibreaka0", 237 /* xt_iclass_wsr.ibreaka0 */,
- 0,
- Opcode_wsr_ibreaka0_encode_fns, 0, 0 },
- { "xsr.ibreaka0", 238 /* xt_iclass_xsr.ibreaka0 */,
- 0,
- Opcode_xsr_ibreaka0_encode_fns, 0, 0 },
- { "rsr.ibreaka1", 239 /* xt_iclass_rsr.ibreaka1 */,
- 0,
- Opcode_rsr_ibreaka1_encode_fns, 0, 0 },
- { "wsr.ibreaka1", 240 /* xt_iclass_wsr.ibreaka1 */,
- 0,
- Opcode_wsr_ibreaka1_encode_fns, 0, 0 },
- { "xsr.ibreaka1", 241 /* xt_iclass_xsr.ibreaka1 */,
- 0,
- Opcode_xsr_ibreaka1_encode_fns, 0, 0 },
- { "rsr.ibreakenable", 242 /* xt_iclass_rsr.ibreakenable */,
- 0,
- Opcode_rsr_ibreakenable_encode_fns, 0, 0 },
- { "wsr.ibreakenable", 243 /* xt_iclass_wsr.ibreakenable */,
- 0,
- Opcode_wsr_ibreakenable_encode_fns, 0, 0 },
- { "xsr.ibreakenable", 244 /* xt_iclass_xsr.ibreakenable */,
- 0,
- Opcode_xsr_ibreakenable_encode_fns, 0, 0 },
- { "rsr.debugcause", 245 /* xt_iclass_rsr.debugcause */,
- 0,
- Opcode_rsr_debugcause_encode_fns, 0, 0 },
- { "wsr.debugcause", 246 /* xt_iclass_wsr.debugcause */,
- 0,
- Opcode_wsr_debugcause_encode_fns, 0, 0 },
- { "xsr.debugcause", 247 /* xt_iclass_xsr.debugcause */,
- 0,
- Opcode_xsr_debugcause_encode_fns, 0, 0 },
- { "rsr.icount", 248 /* xt_iclass_rsr.icount */,
- 0,
- Opcode_rsr_icount_encode_fns, 0, 0 },
- { "wsr.icount", 249 /* xt_iclass_wsr.icount */,
- 0,
- Opcode_wsr_icount_encode_fns, 0, 0 },
- { "xsr.icount", 250 /* xt_iclass_xsr.icount */,
- 0,
- Opcode_xsr_icount_encode_fns, 0, 0 },
- { "rsr.icountlevel", 251 /* xt_iclass_rsr.icountlevel */,
- 0,
- Opcode_rsr_icountlevel_encode_fns, 0, 0 },
- { "wsr.icountlevel", 252 /* xt_iclass_wsr.icountlevel */,
- 0,
- Opcode_wsr_icountlevel_encode_fns, 0, 0 },
- { "xsr.icountlevel", 253 /* xt_iclass_xsr.icountlevel */,
- 0,
- Opcode_xsr_icountlevel_encode_fns, 0, 0 },
- { "rsr.ddr", 254 /* xt_iclass_rsr.ddr */,
- 0,
- Opcode_rsr_ddr_encode_fns, 0, 0 },
- { "wsr.ddr", 255 /* xt_iclass_wsr.ddr */,
- 0,
- Opcode_wsr_ddr_encode_fns, 0, 0 },
- { "xsr.ddr", 256 /* xt_iclass_xsr.ddr */,
- 0,
- Opcode_xsr_ddr_encode_fns, 0, 0 },
- { "rfdo", 257 /* xt_iclass_rfdo */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdo_encode_fns, 0, 0 },
- { "rfdd", 258 /* xt_iclass_rfdd */,
- XTENSA_OPCODE_IS_JUMP,
- Opcode_rfdd_encode_fns, 0, 0 },
- { "wsr.mmid", 259 /* xt_iclass_wsr.mmid */,
- 0,
- Opcode_wsr_mmid_encode_fns, 0, 0 },
- { "andb", 260 /* xt_iclass_bbool1 */,
- 0,
- Opcode_andb_encode_fns, 0, 0 },
- { "andbc", 260 /* xt_iclass_bbool1 */,
- 0,
- Opcode_andbc_encode_fns, 0, 0 },
- { "orb", 260 /* xt_iclass_bbool1 */,
- 0,
- Opcode_orb_encode_fns, 0, 0 },
- { "orbc", 260 /* xt_iclass_bbool1 */,
- 0,
- Opcode_orbc_encode_fns, 0, 0 },
- { "xorb", 260 /* xt_iclass_bbool1 */,
- 0,
- Opcode_xorb_encode_fns, 0, 0 },
- { "any4", 261 /* xt_iclass_bbool4 */,
- 0,
- Opcode_any4_encode_fns, 0, 0 },
- { "all4", 261 /* xt_iclass_bbool4 */,
- 0,
- Opcode_all4_encode_fns, 0, 0 },
- { "any8", 262 /* xt_iclass_bbool8 */,
- 0,
- Opcode_any8_encode_fns, 0, 0 },
- { "all8", 262 /* xt_iclass_bbool8 */,
- 0,
- Opcode_all8_encode_fns, 0, 0 },
- { "bf", 263 /* xt_iclass_bbranch */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bf_encode_fns, 0, 0 },
- { "bt", 263 /* xt_iclass_bbranch */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bt_encode_fns, 0, 0 },
- { "movf", 264 /* xt_iclass_bmove */,
- 0,
- Opcode_movf_encode_fns, 0, 0 },
- { "movt", 264 /* xt_iclass_bmove */,
- 0,
- Opcode_movt_encode_fns, 0, 0 },
- { "rsr.br", 265 /* xt_iclass_RSR.BR */,
- 0,
- Opcode_rsr_br_encode_fns, 0, 0 },
- { "wsr.br", 266 /* xt_iclass_WSR.BR */,
- 0,
- Opcode_wsr_br_encode_fns, 0, 0 },
- { "xsr.br", 267 /* xt_iclass_XSR.BR */,
- 0,
- Opcode_xsr_br_encode_fns, 0, 0 },
- { "rsr.ccount", 268 /* xt_iclass_rsr.ccount */,
- 0,
- Opcode_rsr_ccount_encode_fns, 0, 0 },
- { "wsr.ccount", 269 /* xt_iclass_wsr.ccount */,
- 0,
- Opcode_wsr_ccount_encode_fns, 0, 0 },
- { "xsr.ccount", 270 /* xt_iclass_xsr.ccount */,
- 0,
- Opcode_xsr_ccount_encode_fns, 0, 0 },
- { "rsr.ccompare0", 271 /* xt_iclass_rsr.ccompare0 */,
- 0,
- Opcode_rsr_ccompare0_encode_fns, 0, 0 },
- { "wsr.ccompare0", 272 /* xt_iclass_wsr.ccompare0 */,
- 0,
- Opcode_wsr_ccompare0_encode_fns, 0, 0 },
- { "xsr.ccompare0", 273 /* xt_iclass_xsr.ccompare0 */,
- 0,
- Opcode_xsr_ccompare0_encode_fns, 0, 0 },
- { "rsr.ccompare1", 274 /* xt_iclass_rsr.ccompare1 */,
- 0,
- Opcode_rsr_ccompare1_encode_fns, 0, 0 },
- { "wsr.ccompare1", 275 /* xt_iclass_wsr.ccompare1 */,
- 0,
- Opcode_wsr_ccompare1_encode_fns, 0, 0 },
- { "xsr.ccompare1", 276 /* xt_iclass_xsr.ccompare1 */,
- 0,
- Opcode_xsr_ccompare1_encode_fns, 0, 0 },
- { "rsr.ccompare2", 277 /* xt_iclass_rsr.ccompare2 */,
- 0,
- Opcode_rsr_ccompare2_encode_fns, 0, 0 },
- { "wsr.ccompare2", 278 /* xt_iclass_wsr.ccompare2 */,
- 0,
- Opcode_wsr_ccompare2_encode_fns, 0, 0 },
- { "xsr.ccompare2", 279 /* xt_iclass_xsr.ccompare2 */,
- 0,
- Opcode_xsr_ccompare2_encode_fns, 0, 0 },
- { "ipf", 280 /* xt_iclass_icache */,
- 0,
- Opcode_ipf_encode_fns, 0, 0 },
- { "ihi", 280 /* xt_iclass_icache */,
- 0,
- Opcode_ihi_encode_fns, 0, 0 },
- { "ipfl", 281 /* xt_iclass_icache_lock */,
- 0,
- Opcode_ipfl_encode_fns, 0, 0 },
- { "ihu", 281 /* xt_iclass_icache_lock */,
- 0,
- Opcode_ihu_encode_fns, 0, 0 },
- { "iiu", 281 /* xt_iclass_icache_lock */,
- 0,
- Opcode_iiu_encode_fns, 0, 0 },
- { "iii", 282 /* xt_iclass_icache_inv */,
- 0,
- Opcode_iii_encode_fns, 0, 0 },
- { "lict", 283 /* xt_iclass_licx */,
- 0,
- Opcode_lict_encode_fns, 0, 0 },
- { "licw", 283 /* xt_iclass_licx */,
- 0,
- Opcode_licw_encode_fns, 0, 0 },
- { "sict", 284 /* xt_iclass_sicx */,
- 0,
- Opcode_sict_encode_fns, 0, 0 },
- { "sicw", 284 /* xt_iclass_sicx */,
- 0,
- Opcode_sicw_encode_fns, 0, 0 },
- { "dhwb", 285 /* xt_iclass_dcache */,
- 0,
- Opcode_dhwb_encode_fns, 0, 0 },
- { "dhwbi", 285 /* xt_iclass_dcache */,
- 0,
- Opcode_dhwbi_encode_fns, 0, 0 },
- { "diwb", 286 /* xt_iclass_dcache_ind */,
- 0,
- Opcode_diwb_encode_fns, 0, 0 },
- { "diwbi", 286 /* xt_iclass_dcache_ind */,
- 0,
- Opcode_diwbi_encode_fns, 0, 0 },
- { "dhi", 287 /* xt_iclass_dcache_inv */,
- 0,
- Opcode_dhi_encode_fns, 0, 0 },
- { "dii", 287 /* xt_iclass_dcache_inv */,
- 0,
- Opcode_dii_encode_fns, 0, 0 },
- { "dpfr", 288 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfr_encode_fns, 0, 0 },
- { "dpfw", 288 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfw_encode_fns, 0, 0 },
- { "dpfro", 288 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfro_encode_fns, 0, 0 },
- { "dpfwo", 288 /* xt_iclass_dpf */,
- 0,
- Opcode_dpfwo_encode_fns, 0, 0 },
- { "dpfl", 289 /* xt_iclass_dcache_lock */,
- 0,
- Opcode_dpfl_encode_fns, 0, 0 },
- { "dhu", 289 /* xt_iclass_dcache_lock */,
- 0,
- Opcode_dhu_encode_fns, 0, 0 },
- { "diu", 289 /* xt_iclass_dcache_lock */,
- 0,
- Opcode_diu_encode_fns, 0, 0 },
- { "sdct", 290 /* xt_iclass_sdct */,
- 0,
- Opcode_sdct_encode_fns, 0, 0 },
- { "ldct", 291 /* xt_iclass_ldct */,
- 0,
- Opcode_ldct_encode_fns, 0, 0 },
- { "wsr.ptevaddr", 292 /* xt_iclass_wsr.ptevaddr */,
- 0,
- Opcode_wsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.ptevaddr", 293 /* xt_iclass_rsr.ptevaddr */,
- 0,
- Opcode_rsr_ptevaddr_encode_fns, 0, 0 },
- { "xsr.ptevaddr", 294 /* xt_iclass_xsr.ptevaddr */,
- 0,
- Opcode_xsr_ptevaddr_encode_fns, 0, 0 },
- { "rsr.rasid", 295 /* xt_iclass_rsr.rasid */,
- 0,
- Opcode_rsr_rasid_encode_fns, 0, 0 },
- { "wsr.rasid", 296 /* xt_iclass_wsr.rasid */,
- 0,
- Opcode_wsr_rasid_encode_fns, 0, 0 },
- { "xsr.rasid", 297 /* xt_iclass_xsr.rasid */,
- 0,
- Opcode_xsr_rasid_encode_fns, 0, 0 },
- { "rsr.itlbcfg", 298 /* xt_iclass_rsr.itlbcfg */,
- 0,
- Opcode_rsr_itlbcfg_encode_fns, 0, 0 },
- { "wsr.itlbcfg", 299 /* xt_iclass_wsr.itlbcfg */,
- 0,
- Opcode_wsr_itlbcfg_encode_fns, 0, 0 },
- { "xsr.itlbcfg", 300 /* xt_iclass_xsr.itlbcfg */,
- 0,
- Opcode_xsr_itlbcfg_encode_fns, 0, 0 },
- { "rsr.dtlbcfg", 301 /* xt_iclass_rsr.dtlbcfg */,
- 0,
- Opcode_rsr_dtlbcfg_encode_fns, 0, 0 },
- { "wsr.dtlbcfg", 302 /* xt_iclass_wsr.dtlbcfg */,
- 0,
- Opcode_wsr_dtlbcfg_encode_fns, 0, 0 },
- { "xsr.dtlbcfg", 303 /* xt_iclass_xsr.dtlbcfg */,
- 0,
- Opcode_xsr_dtlbcfg_encode_fns, 0, 0 },
- { "idtlb", 304 /* xt_iclass_idtlb */,
- 0,
- Opcode_idtlb_encode_fns, 0, 0 },
- { "pdtlb", 305 /* xt_iclass_rdtlb */,
- 0,
- Opcode_pdtlb_encode_fns, 0, 0 },
- { "rdtlb0", 305 /* xt_iclass_rdtlb */,
- 0,
- Opcode_rdtlb0_encode_fns, 0, 0 },
- { "rdtlb1", 305 /* xt_iclass_rdtlb */,
- 0,
- Opcode_rdtlb1_encode_fns, 0, 0 },
- { "wdtlb", 306 /* xt_iclass_wdtlb */,
- 0,
- Opcode_wdtlb_encode_fns, 0, 0 },
- { "iitlb", 307 /* xt_iclass_iitlb */,
- 0,
- Opcode_iitlb_encode_fns, 0, 0 },
- { "pitlb", 308 /* xt_iclass_ritlb */,
- 0,
- Opcode_pitlb_encode_fns, 0, 0 },
- { "ritlb0", 308 /* xt_iclass_ritlb */,
- 0,
- Opcode_ritlb0_encode_fns, 0, 0 },
- { "ritlb1", 308 /* xt_iclass_ritlb */,
- 0,
- Opcode_ritlb1_encode_fns, 0, 0 },
- { "witlb", 309 /* xt_iclass_witlb */,
- 0,
- Opcode_witlb_encode_fns, 0, 0 },
- { "ldpte", 310 /* xt_iclass_ldpte */,
- 0,
- Opcode_ldpte_encode_fns, 0, 0 },
- { "hwwitlba", 311 /* xt_iclass_hwwitlba */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_hwwitlba_encode_fns, 0, 0 },
- { "hwwdtlba", 312 /* xt_iclass_hwwdtlba */,
- 0,
- Opcode_hwwdtlba_encode_fns, 0, 0 },
- { "rsr.cpenable", 313 /* xt_iclass_rsr.cpenable */,
- 0,
- Opcode_rsr_cpenable_encode_fns, 0, 0 },
- { "wsr.cpenable", 314 /* xt_iclass_wsr.cpenable */,
- 0,
- Opcode_wsr_cpenable_encode_fns, 0, 0 },
- { "xsr.cpenable", 315 /* xt_iclass_xsr.cpenable */,
- 0,
- Opcode_xsr_cpenable_encode_fns, 0, 0 },
- { "clamps", 316 /* xt_iclass_clamp */,
- 0,
- Opcode_clamps_encode_fns, 0, 0 },
- { "min", 317 /* xt_iclass_minmax */,
- 0,
- Opcode_min_encode_fns, 0, 0 },
- { "max", 317 /* xt_iclass_minmax */,
- 0,
- Opcode_max_encode_fns, 0, 0 },
- { "minu", 317 /* xt_iclass_minmax */,
- 0,
- Opcode_minu_encode_fns, 0, 0 },
- { "maxu", 317 /* xt_iclass_minmax */,
- 0,
- Opcode_maxu_encode_fns, 0, 0 },
- { "nsa", 318 /* xt_iclass_nsa */,
- 0,
- Opcode_nsa_encode_fns, 0, 0 },
- { "nsau", 318 /* xt_iclass_nsa */,
- 0,
- Opcode_nsau_encode_fns, 0, 0 },
- { "sext", 319 /* xt_iclass_sx */,
- 0,
- Opcode_sext_encode_fns, 0, 0 },
- { "l32ai", 320 /* xt_iclass_l32ai */,
- 0,
- Opcode_l32ai_encode_fns, 0, 0 },
- { "s32ri", 321 /* xt_iclass_s32ri */,
- 0,
- Opcode_s32ri_encode_fns, 0, 0 },
- { "s32c1i", 322 /* xt_iclass_s32c1i */,
- 0,
- Opcode_s32c1i_encode_fns, 0, 0 },
- { "rsr.scompare1", 323 /* xt_iclass_rsr.scompare1 */,
- 0,
- Opcode_rsr_scompare1_encode_fns, 0, 0 },
- { "wsr.scompare1", 324 /* xt_iclass_wsr.scompare1 */,
- 0,
- Opcode_wsr_scompare1_encode_fns, 0, 0 },
- { "xsr.scompare1", 325 /* xt_iclass_xsr.scompare1 */,
- 0,
- Opcode_xsr_scompare1_encode_fns, 0, 0 },
- { "quou", 326 /* xt_iclass_div */,
- 0,
- Opcode_quou_encode_fns, 0, 0 },
- { "quos", 326 /* xt_iclass_div */,
- 0,
- Opcode_quos_encode_fns, 0, 0 },
- { "remu", 326 /* xt_iclass_div */,
- 0,
- Opcode_remu_encode_fns, 0, 0 },
- { "rems", 326 /* xt_iclass_div */,
- 0,
- Opcode_rems_encode_fns, 0, 0 },
- { "mull", 327 /* xt_mul32 */,
- 0,
- Opcode_mull_encode_fns, 0, 0 },
- { "muluh", 327 /* xt_mul32 */,
- 0,
- Opcode_muluh_encode_fns, 0, 0 },
- { "mulsh", 327 /* xt_mul32 */,
- 0,
- Opcode_mulsh_encode_fns, 0, 0 },
- { "rur.fcr", 328 /* rur_fcr */,
- 0,
- Opcode_rur_fcr_encode_fns, 0, 0 },
- { "wur.fcr", 329 /* wur_fcr */,
- 0,
- Opcode_wur_fcr_encode_fns, 0, 0 },
- { "rur.fsr", 330 /* rur_fsr */,
- 0,
- Opcode_rur_fsr_encode_fns, 0, 0 },
- { "wur.fsr", 331 /* wur_fsr */,
- 0,
- Opcode_wur_fsr_encode_fns, 0, 0 },
- { "add.s", 332 /* fp */,
- 0,
- Opcode_add_s_encode_fns, 0, 0 },
- { "sub.s", 332 /* fp */,
- 0,
- Opcode_sub_s_encode_fns, 0, 0 },
- { "mul.s", 332 /* fp */,
- 0,
- Opcode_mul_s_encode_fns, 0, 0 },
- { "madd.s", 333 /* fp_mac */,
- 0,
- Opcode_madd_s_encode_fns, 0, 0 },
- { "msub.s", 333 /* fp_mac */,
- 0,
- Opcode_msub_s_encode_fns, 0, 0 },
- { "movf.s", 334 /* fp_cmov */,
- 0,
- Opcode_movf_s_encode_fns, 0, 0 },
- { "movt.s", 334 /* fp_cmov */,
- 0,
- Opcode_movt_s_encode_fns, 0, 0 },
- { "moveqz.s", 335 /* fp_mov */,
- 0,
- Opcode_moveqz_s_encode_fns, 0, 0 },
- { "movnez.s", 335 /* fp_mov */,
- 0,
- Opcode_movnez_s_encode_fns, 0, 0 },
- { "movltz.s", 335 /* fp_mov */,
- 0,
- Opcode_movltz_s_encode_fns, 0, 0 },
- { "movgez.s", 335 /* fp_mov */,
- 0,
- Opcode_movgez_s_encode_fns, 0, 0 },
- { "abs.s", 336 /* fp_mov2 */,
- 0,
- Opcode_abs_s_encode_fns, 0, 0 },
- { "mov.s", 336 /* fp_mov2 */,
- 0,
- Opcode_mov_s_encode_fns, 0, 0 },
- { "neg.s", 336 /* fp_mov2 */,
- 0,
- Opcode_neg_s_encode_fns, 0, 0 },
- { "un.s", 337 /* fp_cmp */,
- 0,
- Opcode_un_s_encode_fns, 0, 0 },
- { "oeq.s", 337 /* fp_cmp */,
- 0,
- Opcode_oeq_s_encode_fns, 0, 0 },
- { "ueq.s", 337 /* fp_cmp */,
- 0,
- Opcode_ueq_s_encode_fns, 0, 0 },
- { "olt.s", 337 /* fp_cmp */,
- 0,
- Opcode_olt_s_encode_fns, 0, 0 },
- { "ult.s", 337 /* fp_cmp */,
- 0,
- Opcode_ult_s_encode_fns, 0, 0 },
- { "ole.s", 337 /* fp_cmp */,
- 0,
- Opcode_ole_s_encode_fns, 0, 0 },
- { "ule.s", 337 /* fp_cmp */,
- 0,
- Opcode_ule_s_encode_fns, 0, 0 },
- { "float.s", 338 /* fp_float */,
- 0,
- Opcode_float_s_encode_fns, 0, 0 },
- { "ufloat.s", 338 /* fp_float */,
- 0,
- Opcode_ufloat_s_encode_fns, 0, 0 },
- { "round.s", 339 /* fp_int */,
- 0,
- Opcode_round_s_encode_fns, 0, 0 },
- { "ceil.s", 339 /* fp_int */,
- 0,
- Opcode_ceil_s_encode_fns, 0, 0 },
- { "floor.s", 339 /* fp_int */,
- 0,
- Opcode_floor_s_encode_fns, 0, 0 },
- { "trunc.s", 339 /* fp_int */,
- 0,
- Opcode_trunc_s_encode_fns, 0, 0 },
- { "utrunc.s", 339 /* fp_int */,
- 0,
- Opcode_utrunc_s_encode_fns, 0, 0 },
- { "rfr", 340 /* fp_rfr */,
- 0,
- Opcode_rfr_encode_fns, 0, 0 },
- { "wfr", 341 /* fp_wfr */,
- 0,
- Opcode_wfr_encode_fns, 0, 0 },
- { "lsi", 342 /* fp_lsi */,
- 0,
- Opcode_lsi_encode_fns, 0, 0 },
- { "lsiu", 343 /* fp_lsiu */,
- 0,
- Opcode_lsiu_encode_fns, 0, 0 },
- { "lsx", 344 /* fp_lsx */,
- 0,
- Opcode_lsx_encode_fns, 0, 0 },
- { "lsxu", 345 /* fp_lsxu */,
- 0,
- Opcode_lsxu_encode_fns, 0, 0 },
- { "ssi", 346 /* fp_ssi */,
- 0,
- Opcode_ssi_encode_fns, 0, 0 },
- { "ssiu", 347 /* fp_ssiu */,
- 0,
- Opcode_ssiu_encode_fns, 0, 0 },
- { "ssx", 348 /* fp_ssx */,
- 0,
- Opcode_ssx_encode_fns, 0, 0 },
- { "ssxu", 349 /* fp_ssxu */,
- 0,
- Opcode_ssxu_encode_fns, 0, 0 },
- { "beqz.w18", 350 /* xt_iclass_wb18_0 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqz_w18_encode_fns, 0, 0 },
- { "bnez.w18", 350 /* xt_iclass_wb18_0 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnez_w18_encode_fns, 0, 0 },
- { "bgez.w18", 350 /* xt_iclass_wb18_0 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgez_w18_encode_fns, 0, 0 },
- { "bltz.w18", 350 /* xt_iclass_wb18_0 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltz_w18_encode_fns, 0, 0 },
- { "beqi.w18", 351 /* xt_iclass_wb18_1 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beqi_w18_encode_fns, 0, 0 },
- { "bnei.w18", 351 /* xt_iclass_wb18_1 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnei_w18_encode_fns, 0, 0 },
- { "bgei.w18", 351 /* xt_iclass_wb18_1 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgei_w18_encode_fns, 0, 0 },
- { "blti.w18", 351 /* xt_iclass_wb18_1 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blti_w18_encode_fns, 0, 0 },
- { "bgeui.w18", 352 /* xt_iclass_wb18_2 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeui_w18_encode_fns, 0, 0 },
- { "bltui.w18", 352 /* xt_iclass_wb18_2 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltui_w18_encode_fns, 0, 0 },
- { "bbci.w18", 353 /* xt_iclass_wb18_3 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbci_w18_encode_fns, 0, 0 },
- { "bbsi.w18", 353 /* xt_iclass_wb18_3 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbsi_w18_encode_fns, 0, 0 },
- { "beq.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_beq_w18_encode_fns, 0, 0 },
- { "bne.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bne_w18_encode_fns, 0, 0 },
- { "bge.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bge_w18_encode_fns, 0, 0 },
- { "blt.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_blt_w18_encode_fns, 0, 0 },
- { "bgeu.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bgeu_w18_encode_fns, 0, 0 },
- { "bltu.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bltu_w18_encode_fns, 0, 0 },
- { "bany.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bany_w18_encode_fns, 0, 0 },
- { "bnone.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnone_w18_encode_fns, 0, 0 },
- { "ball.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_ball_w18_encode_fns, 0, 0 },
- { "bnall.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bnall_w18_encode_fns, 0, 0 },
- { "bbc.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbc_w18_encode_fns, 0, 0 },
- { "bbs.w18", 354 /* xt_iclass_wb18_4 */,
- XTENSA_OPCODE_IS_BRANCH,
- Opcode_bbs_w18_encode_fns, 0, 0 }
- };
- /* Slot-specific opcode decode functions. */
- static int
- Slot_inst_decode (const xtensa_insnbuf insn)
- {
- switch (Field_op0_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_n_Slot_inst_get (insn) == 0)
- return 79; /* ill */
- break;
- case 2:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 98; /* ret */
- case 1:
- return 14; /* retw */
- case 2:
- return 81; /* jx */
- }
- break;
- case 3:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 77; /* callx0 */
- case 1:
- return 10; /* callx4 */
- case 2:
- return 9; /* callx8 */
- case 3:
- return 8; /* callx12 */
- }
- break;
- }
- break;
- case 1:
- return 12; /* movsp */
- case 2:
- if (Field_s_Slot_inst_get (insn) == 0)
- {
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return 116; /* isync */
- case 1:
- return 117; /* rsync */
- case 2:
- return 118; /* esync */
- case 3:
- return 119; /* dsync */
- case 8:
- return 0; /* excw */
- case 12:
- return 114; /* memw */
- case 13:
- return 115; /* extw */
- case 15:
- return 97; /* nop */
- }
- }
- break;
- case 3:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- return 1; /* rfe */
- case 2:
- return 2; /* rfde */
- case 4:
- return 16; /* rfwo */
- case 5:
- return 17; /* rfwu */
- }
- break;
- case 1:
- return 316; /* rfi */
- }
- break;
- case 4:
- return 324; /* break */
- case 5:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 3; /* syscall */
- break;
- case 1:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 4; /* simcall */
- break;
- }
- break;
- case 6:
- return 120; /* rsil */
- case 7:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 317; /* waiti */
- break;
- case 8:
- return 367; /* any4 */
- case 9:
- return 368; /* all4 */
- case 10:
- return 369; /* any8 */
- case 11:
- return 370; /* all8 */
- }
- break;
- case 1:
- return 49; /* and */
- case 2:
- return 50; /* or */
- case 3:
- return 51; /* xor */
- case 4:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 102; /* ssr */
- break;
- case 1:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 103; /* ssl */
- break;
- case 2:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 104; /* ssa8l */
- break;
- case 3:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 105; /* ssa8b */
- break;
- case 4:
- if (Field_thi3_Slot_inst_get (insn) == 0)
- return 106; /* ssai */
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 13; /* rotw */
- break;
- case 14:
- return 448; /* nsa */
- case 15:
- return 449; /* nsau */
- }
- break;
- case 5:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 1:
- return 438; /* hwwitlba */
- case 3:
- return 434; /* ritlb0 */
- case 4:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 432; /* iitlb */
- break;
- case 5:
- return 433; /* pitlb */
- case 6:
- return 436; /* witlb */
- case 7:
- return 435; /* ritlb1 */
- case 9:
- return 439; /* hwwdtlba */
- case 11:
- return 429; /* rdtlb0 */
- case 12:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 427; /* idtlb */
- break;
- case 13:
- return 428; /* pdtlb */
- case 14:
- return 431; /* wdtlb */
- case 15:
- return 430; /* rdtlb1 */
- }
- break;
- case 6:
- switch (Field_s_Slot_inst_get (insn))
- {
- case 0:
- return 95; /* neg */
- case 1:
- return 96; /* abs */
- }
- break;
- case 8:
- return 41; /* add */
- case 9:
- return 43; /* addx2 */
- case 10:
- return 44; /* addx4 */
- case 11:
- return 45; /* addx8 */
- case 12:
- return 42; /* sub */
- case 13:
- return 46; /* subx2 */
- case 14:
- return 47; /* subx4 */
- case 15:
- return 48; /* subx8 */
- }
- break;
- case 1:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- case 1:
- return 111; /* slli */
- case 2:
- case 3:
- return 112; /* srai */
- case 4:
- return 113; /* srli */
- case 6:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 129; /* xsr.lbeg */
- case 1:
- return 123; /* xsr.lend */
- case 2:
- return 126; /* xsr.lcount */
- case 3:
- return 132; /* xsr.sar */
- case 4:
- return 377; /* xsr.br */
- case 5:
- return 135; /* xsr.litbase */
- case 12:
- return 456; /* xsr.scompare1 */
- case 16:
- return 312; /* xsr.acclo */
- case 17:
- return 315; /* xsr.acchi */
- case 32:
- return 300; /* xsr.m0 */
- case 33:
- return 303; /* xsr.m1 */
- case 34:
- return 306; /* xsr.m2 */
- case 35:
- return 309; /* xsr.m3 */
- case 72:
- return 22; /* xsr.windowbase */
- case 73:
- return 25; /* xsr.windowstart */
- case 83:
- return 417; /* xsr.ptevaddr */
- case 90:
- return 420; /* xsr.rasid */
- case 91:
- return 423; /* xsr.itlbcfg */
- case 92:
- return 426; /* xsr.dtlbcfg */
- case 96:
- return 346; /* xsr.ibreakenable */
- case 104:
- return 358; /* xsr.ddr */
- case 128:
- return 340; /* xsr.ibreaka0 */
- case 129:
- return 343; /* xsr.ibreaka1 */
- case 144:
- return 328; /* xsr.dbreaka0 */
- case 145:
- return 334; /* xsr.dbreaka1 */
- case 160:
- return 331; /* xsr.dbreakc0 */
- case 161:
- return 337; /* xsr.dbreakc1 */
- case 177:
- return 143; /* xsr.epc1 */
- case 178:
- return 149; /* xsr.epc2 */
- case 179:
- return 155; /* xsr.epc3 */
- case 180:
- return 161; /* xsr.epc4 */
- case 181:
- return 167; /* xsr.epc5 */
- case 182:
- return 173; /* xsr.epc6 */
- case 183:
- return 179; /* xsr.epc7 */
- case 192:
- return 206; /* xsr.depc */
- case 194:
- return 185; /* xsr.eps2 */
- case 195:
- return 188; /* xsr.eps3 */
- case 196:
- return 191; /* xsr.eps4 */
- case 197:
- return 194; /* xsr.eps5 */
- case 198:
- return 197; /* xsr.eps6 */
- case 199:
- return 200; /* xsr.eps7 */
- case 209:
- return 146; /* xsr.excsave1 */
- case 210:
- return 152; /* xsr.excsave2 */
- case 211:
- return 158; /* xsr.excsave3 */
- case 212:
- return 164; /* xsr.excsave4 */
- case 213:
- return 170; /* xsr.excsave5 */
- case 214:
- return 176; /* xsr.excsave6 */
- case 215:
- return 182; /* xsr.excsave7 */
- case 224:
- return 442; /* xsr.cpenable */
- case 228:
- return 323; /* xsr.intenable */
- case 230:
- return 140; /* xsr.ps */
- case 231:
- return 225; /* xsr.vecbase */
- case 232:
- return 209; /* xsr.exccause */
- case 233:
- return 349; /* xsr.debugcause */
- case 234:
- return 380; /* xsr.ccount */
- case 236:
- return 352; /* xsr.icount */
- case 237:
- return 355; /* xsr.icountlevel */
- case 238:
- return 203; /* xsr.excvaddr */
- case 240:
- return 383; /* xsr.ccompare0 */
- case 241:
- return 386; /* xsr.ccompare1 */
- case 242:
- return 389; /* xsr.ccompare2 */
- case 244:
- return 212; /* xsr.misc0 */
- case 245:
- return 215; /* xsr.misc1 */
- case 246:
- return 218; /* xsr.misc2 */
- case 247:
- return 221; /* xsr.misc3 */
- }
- break;
- case 8:
- return 108; /* src */
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 109; /* srl */
- break;
- case 10:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 107; /* sll */
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0)
- return 110; /* sra */
- break;
- case 12:
- return 296; /* mul16u */
- case 13:
- return 297; /* mul16s */
- case 15:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 396; /* lict */
- case 1:
- return 398; /* sict */
- case 2:
- return 397; /* licw */
- case 3:
- return 399; /* sicw */
- case 8:
- return 414; /* ldct */
- case 9:
- return 413; /* sdct */
- case 14:
- if (Field_t_Slot_inst_get (insn) == 0)
- return 359; /* rfdo */
- if (Field_t_Slot_inst_get (insn) == 1)
- return 360; /* rfdd */
- break;
- case 15:
- return 437; /* ldpte */
- }
- break;
- }
- break;
- case 2:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- return 362; /* andb */
- case 1:
- return 363; /* andbc */
- case 2:
- return 364; /* orb */
- case 3:
- return 365; /* orbc */
- case 4:
- return 366; /* xorb */
- case 8:
- return 461; /* mull */
- case 10:
- return 462; /* muluh */
- case 11:
- return 463; /* mulsh */
- case 12:
- return 457; /* quou */
- case 13:
- return 458; /* quos */
- case 14:
- return 459; /* remu */
- case 15:
- return 460; /* rems */
- }
- break;
- case 3:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 127; /* rsr.lbeg */
- case 1:
- return 121; /* rsr.lend */
- case 2:
- return 124; /* rsr.lcount */
- case 3:
- return 130; /* rsr.sar */
- case 4:
- return 375; /* rsr.br */
- case 5:
- return 133; /* rsr.litbase */
- case 12:
- return 454; /* rsr.scompare1 */
- case 16:
- return 310; /* rsr.acclo */
- case 17:
- return 313; /* rsr.acchi */
- case 32:
- return 298; /* rsr.m0 */
- case 33:
- return 301; /* rsr.m1 */
- case 34:
- return 304; /* rsr.m2 */
- case 35:
- return 307; /* rsr.m3 */
- case 72:
- return 20; /* rsr.windowbase */
- case 73:
- return 23; /* rsr.windowstart */
- case 83:
- return 416; /* rsr.ptevaddr */
- case 90:
- return 418; /* rsr.rasid */
- case 91:
- return 421; /* rsr.itlbcfg */
- case 92:
- return 424; /* rsr.dtlbcfg */
- case 96:
- return 344; /* rsr.ibreakenable */
- case 104:
- return 356; /* rsr.ddr */
- case 128:
- return 338; /* rsr.ibreaka0 */
- case 129:
- return 341; /* rsr.ibreaka1 */
- case 144:
- return 326; /* rsr.dbreaka0 */
- case 145:
- return 332; /* rsr.dbreaka1 */
- case 160:
- return 329; /* rsr.dbreakc0 */
- case 161:
- return 335; /* rsr.dbreakc1 */
- case 176:
- return 136; /* rsr.176 */
- case 177:
- return 141; /* rsr.epc1 */
- case 178:
- return 147; /* rsr.epc2 */
- case 179:
- return 153; /* rsr.epc3 */
- case 180:
- return 159; /* rsr.epc4 */
- case 181:
- return 165; /* rsr.epc5 */
- case 182:
- return 171; /* rsr.epc6 */
- case 183:
- return 177; /* rsr.epc7 */
- case 192:
- return 204; /* rsr.depc */
- case 194:
- return 183; /* rsr.eps2 */
- case 195:
- return 186; /* rsr.eps3 */
- case 196:
- return 189; /* rsr.eps4 */
- case 197:
- return 192; /* rsr.eps5 */
- case 198:
- return 195; /* rsr.eps6 */
- case 199:
- return 198; /* rsr.eps7 */
- case 208:
- return 137; /* rsr.208 */
- case 209:
- return 144; /* rsr.excsave1 */
- case 210:
- return 150; /* rsr.excsave2 */
- case 211:
- return 156; /* rsr.excsave3 */
- case 212:
- return 162; /* rsr.excsave4 */
- case 213:
- return 168; /* rsr.excsave5 */
- case 214:
- return 174; /* rsr.excsave6 */
- case 215:
- return 180; /* rsr.excsave7 */
- case 224:
- return 440; /* rsr.cpenable */
- case 226:
- return 318; /* rsr.interrupt */
- case 228:
- return 321; /* rsr.intenable */
- case 230:
- return 138; /* rsr.ps */
- case 231:
- return 223; /* rsr.vecbase */
- case 232:
- return 207; /* rsr.exccause */
- case 233:
- return 347; /* rsr.debugcause */
- case 234:
- return 378; /* rsr.ccount */
- case 235:
- return 222; /* rsr.prid */
- case 236:
- return 350; /* rsr.icount */
- case 237:
- return 353; /* rsr.icountlevel */
- case 238:
- return 201; /* rsr.excvaddr */
- case 240:
- return 381; /* rsr.ccompare0 */
- case 241:
- return 384; /* rsr.ccompare1 */
- case 242:
- return 387; /* rsr.ccompare2 */
- case 244:
- return 210; /* rsr.misc0 */
- case 245:
- return 213; /* rsr.misc1 */
- case 246:
- return 216; /* rsr.misc2 */
- case 247:
- return 219; /* rsr.misc3 */
- }
- break;
- case 1:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 0:
- return 128; /* wsr.lbeg */
- case 1:
- return 122; /* wsr.lend */
- case 2:
- return 125; /* wsr.lcount */
- case 3:
- return 131; /* wsr.sar */
- case 4:
- return 376; /* wsr.br */
- case 5:
- return 134; /* wsr.litbase */
- case 12:
- return 455; /* wsr.scompare1 */
- case 16:
- return 311; /* wsr.acclo */
- case 17:
- return 314; /* wsr.acchi */
- case 32:
- return 299; /* wsr.m0 */
- case 33:
- return 302; /* wsr.m1 */
- case 34:
- return 305; /* wsr.m2 */
- case 35:
- return 308; /* wsr.m3 */
- case 72:
- return 21; /* wsr.windowbase */
- case 73:
- return 24; /* wsr.windowstart */
- case 83:
- return 415; /* wsr.ptevaddr */
- case 89:
- return 361; /* wsr.mmid */
- case 90:
- return 419; /* wsr.rasid */
- case 91:
- return 422; /* wsr.itlbcfg */
- case 92:
- return 425; /* wsr.dtlbcfg */
- case 96:
- return 345; /* wsr.ibreakenable */
- case 104:
- return 357; /* wsr.ddr */
- case 128:
- return 339; /* wsr.ibreaka0 */
- case 129:
- return 342; /* wsr.ibreaka1 */
- case 144:
- return 327; /* wsr.dbreaka0 */
- case 145:
- return 333; /* wsr.dbreaka1 */
- case 160:
- return 330; /* wsr.dbreakc0 */
- case 161:
- return 336; /* wsr.dbreakc1 */
- case 177:
- return 142; /* wsr.epc1 */
- case 178:
- return 148; /* wsr.epc2 */
- case 179:
- return 154; /* wsr.epc3 */
- case 180:
- return 160; /* wsr.epc4 */
- case 181:
- return 166; /* wsr.epc5 */
- case 182:
- return 172; /* wsr.epc6 */
- case 183:
- return 178; /* wsr.epc7 */
- case 192:
- return 205; /* wsr.depc */
- case 194:
- return 184; /* wsr.eps2 */
- case 195:
- return 187; /* wsr.eps3 */
- case 196:
- return 190; /* wsr.eps4 */
- case 197:
- return 193; /* wsr.eps5 */
- case 198:
- return 196; /* wsr.eps6 */
- case 199:
- return 199; /* wsr.eps7 */
- case 209:
- return 145; /* wsr.excsave1 */
- case 210:
- return 151; /* wsr.excsave2 */
- case 211:
- return 157; /* wsr.excsave3 */
- case 212:
- return 163; /* wsr.excsave4 */
- case 213:
- return 169; /* wsr.excsave5 */
- case 214:
- return 175; /* wsr.excsave6 */
- case 215:
- return 181; /* wsr.excsave7 */
- case 224:
- return 441; /* wsr.cpenable */
- case 226:
- return 319; /* wsr.intset */
- case 227:
- return 320; /* wsr.intclear */
- case 228:
- return 322; /* wsr.intenable */
- case 230:
- return 139; /* wsr.ps */
- case 231:
- return 224; /* wsr.vecbase */
- case 232:
- return 208; /* wsr.exccause */
- case 233:
- return 348; /* wsr.debugcause */
- case 234:
- return 379; /* wsr.ccount */
- case 236:
- return 351; /* wsr.icount */
- case 237:
- return 354; /* wsr.icountlevel */
- case 238:
- return 202; /* wsr.excvaddr */
- case 240:
- return 382; /* wsr.ccompare0 */
- case 241:
- return 385; /* wsr.ccompare1 */
- case 242:
- return 388; /* wsr.ccompare2 */
- case 244:
- return 211; /* wsr.misc0 */
- case 245:
- return 214; /* wsr.misc1 */
- case 246:
- return 217; /* wsr.misc2 */
- case 247:
- return 220; /* wsr.misc3 */
- }
- break;
- case 2:
- return 450; /* sext */
- case 3:
- return 443; /* clamps */
- case 4:
- return 444; /* min */
- case 5:
- return 445; /* max */
- case 6:
- return 446; /* minu */
- case 7:
- return 447; /* maxu */
- case 8:
- return 91; /* moveqz */
- case 9:
- return 92; /* movnez */
- case 10:
- return 93; /* movltz */
- case 11:
- return 94; /* movgez */
- case 12:
- return 373; /* movf */
- case 13:
- return 374; /* movt */
- case 14:
- switch (Field_st_Slot_inst_get (insn))
- {
- case 231:
- return 37; /* rur.threadptr */
- case 232:
- return 464; /* rur.fcr */
- case 233:
- return 466; /* rur.fsr */
- }
- break;
- case 15:
- switch (Field_sr_Slot_inst_get (insn))
- {
- case 231:
- return 38; /* wur.threadptr */
- case 232:
- return 465; /* wur.fcr */
- case 233:
- return 467; /* wur.fsr */
- }
- break;
- }
- break;
- case 4:
- case 5:
- return 78; /* extui */
- case 8:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- return 500; /* lsx */
- case 1:
- return 501; /* lsxu */
- case 4:
- return 504; /* ssx */
- case 5:
- return 505; /* ssxu */
- }
- break;
- case 9:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- return 18; /* l32e */
- case 4:
- return 19; /* s32e */
- }
- break;
- case 10:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- return 468; /* add.s */
- case 1:
- return 469; /* sub.s */
- case 2:
- return 470; /* mul.s */
- case 4:
- return 471; /* madd.s */
- case 5:
- return 472; /* msub.s */
- case 8:
- return 491; /* round.s */
- case 9:
- return 494; /* trunc.s */
- case 10:
- return 493; /* floor.s */
- case 11:
- return 492; /* ceil.s */
- case 12:
- return 489; /* float.s */
- case 13:
- return 490; /* ufloat.s */
- case 14:
- return 495; /* utrunc.s */
- case 15:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return 480; /* mov.s */
- case 1:
- return 479; /* abs.s */
- case 4:
- return 496; /* rfr */
- case 5:
- return 497; /* wfr */
- case 6:
- return 481; /* neg.s */
- }
- break;
- }
- break;
- case 11:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 1:
- return 482; /* un.s */
- case 2:
- return 483; /* oeq.s */
- case 3:
- return 484; /* ueq.s */
- case 4:
- return 485; /* olt.s */
- case 5:
- return 486; /* ult.s */
- case 6:
- return 487; /* ole.s */
- case 7:
- return 488; /* ule.s */
- case 8:
- return 475; /* moveqz.s */
- case 9:
- return 476; /* movnez.s */
- case 10:
- return 477; /* movltz.s */
- case 11:
- return 478; /* movgez.s */
- case 12:
- return 473; /* movf.s */
- case 13:
- return 474; /* movt.s */
- }
- break;
- }
- break;
- case 1:
- return 85; /* l32r */
- case 2:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 86; /* l8ui */
- case 1:
- return 82; /* l16ui */
- case 2:
- return 84; /* l32i */
- case 4:
- return 101; /* s8i */
- case 5:
- return 99; /* s16i */
- case 6:
- return 100; /* s32i */
- case 7:
- switch (Field_t_Slot_inst_get (insn))
- {
- case 0:
- return 406; /* dpfr */
- case 1:
- return 407; /* dpfw */
- case 2:
- return 408; /* dpfro */
- case 3:
- return 409; /* dpfwo */
- case 4:
- return 400; /* dhwb */
- case 5:
- return 401; /* dhwbi */
- case 6:
- return 404; /* dhi */
- case 7:
- return 405; /* dii */
- case 8:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- return 410; /* dpfl */
- case 2:
- return 411; /* dhu */
- case 3:
- return 412; /* diu */
- case 4:
- return 402; /* diwb */
- case 5:
- return 403; /* diwbi */
- }
- break;
- case 12:
- return 390; /* ipf */
- case 13:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- return 392; /* ipfl */
- case 2:
- return 393; /* ihu */
- case 3:
- return 394; /* iiu */
- }
- break;
- case 14:
- return 391; /* ihi */
- case 15:
- return 395; /* iii */
- }
- break;
- case 9:
- return 83; /* l16si */
- case 10:
- return 90; /* movi */
- case 11:
- return 451; /* l32ai */
- case 12:
- return 39; /* addi */
- case 13:
- return 40; /* addmi */
- case 14:
- return 453; /* s32c1i */
- case 15:
- return 452; /* s32ri */
- }
- break;
- case 3:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 498; /* lsi */
- case 4:
- return 502; /* ssi */
- case 8:
- return 499; /* lsiu */
- case 12:
- return 503; /* ssiu */
- }
- break;
- case 4:
- switch (Field_op2_Slot_inst_get (insn))
- {
- case 0:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 287; /* mula.dd.ll.ldinc */
- break;
- case 9:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 289; /* mula.dd.hl.ldinc */
- break;
- case 10:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 291; /* mula.dd.lh.ldinc */
- break;
- case 11:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 293; /* mula.dd.hh.ldinc */
- break;
- }
- break;
- case 1:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 286; /* mula.dd.ll.lddec */
- break;
- case 9:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 288; /* mula.dd.hl.lddec */
- break;
- case 10:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 290; /* mula.dd.lh.lddec */
- break;
- case 11:
- if (Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 292; /* mula.dd.hh.lddec */
- break;
- }
- break;
- case 2:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 242; /* mul.dd.ll */
- break;
- case 5:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 243; /* mul.dd.hl */
- break;
- case 6:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 244; /* mul.dd.lh */
- break;
- case 7:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 245; /* mul.dd.hh */
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 270; /* mula.dd.ll */
- break;
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 271; /* mula.dd.hl */
- break;
- case 10:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 272; /* mula.dd.lh */
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 273; /* mula.dd.hh */
- break;
- case 12:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 274; /* muls.dd.ll */
- break;
- case 13:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 275; /* muls.dd.hl */
- break;
- case 14:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 276; /* muls.dd.lh */
- break;
- case 15:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 277; /* muls.dd.hh */
- break;
- }
- break;
- case 3:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 234; /* mul.ad.ll */
- break;
- case 5:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 235; /* mul.ad.hl */
- break;
- case 6:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 236; /* mul.ad.lh */
- break;
- case 7:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 237; /* mul.ad.hh */
- break;
- case 8:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 254; /* mula.ad.ll */
- break;
- case 9:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 255; /* mula.ad.hl */
- break;
- case 10:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 256; /* mula.ad.lh */
- break;
- case 11:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 257; /* mula.ad.hh */
- break;
- case 12:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 258; /* muls.ad.ll */
- break;
- case 13:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 259; /* muls.ad.hl */
- break;
- case 14:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 260; /* muls.ad.lh */
- break;
- case 15:
- if (Field_r_Slot_inst_get (insn) == 0 &&
- Field_t3_Slot_inst_get (insn) == 0 &&
- Field_tlo_Slot_inst_get (insn) == 0)
- return 261; /* muls.ad.hh */
- break;
- }
- break;
- case 4:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 279; /* mula.da.ll.ldinc */
- break;
- case 9:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 281; /* mula.da.hl.ldinc */
- break;
- case 10:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 283; /* mula.da.lh.ldinc */
- break;
- case 11:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 285; /* mula.da.hh.ldinc */
- break;
- }
- break;
- case 5:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 8:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 278; /* mula.da.ll.lddec */
- break;
- case 9:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 280; /* mula.da.hl.lddec */
- break;
- case 10:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 282; /* mula.da.lh.lddec */
- break;
- case 11:
- if (Field_r3_Slot_inst_get (insn) == 0)
- return 284; /* mula.da.hh.lddec */
- break;
- }
- break;
- case 6:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 4:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 238; /* mul.da.ll */
- break;
- case 5:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 239; /* mul.da.hl */
- break;
- case 6:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 240; /* mul.da.lh */
- break;
- case 7:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 241; /* mul.da.hh */
- break;
- case 8:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 262; /* mula.da.ll */
- break;
- case 9:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 263; /* mula.da.hl */
- break;
- case 10:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 264; /* mula.da.lh */
- break;
- case 11:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 265; /* mula.da.hh */
- break;
- case 12:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 266; /* muls.da.ll */
- break;
- case 13:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 267; /* muls.da.hl */
- break;
- case 14:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 268; /* muls.da.lh */
- break;
- case 15:
- if (Field_s_Slot_inst_get (insn) == 0 &&
- Field_w_Slot_inst_get (insn) == 0 &&
- Field_r3_Slot_inst_get (insn) == 0)
- return 269; /* muls.da.hh */
- break;
- }
- break;
- case 7:
- switch (Field_op1_Slot_inst_get (insn))
- {
- case 0:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 230; /* umul.aa.ll */
- break;
- case 1:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 231; /* umul.aa.hl */
- break;
- case 2:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 232; /* umul.aa.lh */
- break;
- case 3:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 233; /* umul.aa.hh */
- break;
- case 4:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 226; /* mul.aa.ll */
- break;
- case 5:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 227; /* mul.aa.hl */
- break;
- case 6:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 228; /* mul.aa.lh */
- break;
- case 7:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 229; /* mul.aa.hh */
- break;
- case 8:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 246; /* mula.aa.ll */
- break;
- case 9:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 247; /* mula.aa.hl */
- break;
- case 10:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 248; /* mula.aa.lh */
- break;
- case 11:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 249; /* mula.aa.hh */
- break;
- case 12:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 250; /* muls.aa.ll */
- break;
- case 13:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 251; /* muls.aa.hl */
- break;
- case 14:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 252; /* muls.aa.lh */
- break;
- case 15:
- if (Field_r_Slot_inst_get (insn) == 0)
- return 253; /* muls.aa.hh */
- break;
- }
- break;
- case 8:
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return 295; /* ldinc */
- break;
- case 9:
- if (Field_op1_Slot_inst_get (insn) == 0 &&
- Field_t_Slot_inst_get (insn) == 0 &&
- Field_rhi_Slot_inst_get (insn) == 0)
- return 294; /* lddec */
- break;
- }
- break;
- case 5:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 76; /* call0 */
- case 1:
- return 7; /* call4 */
- case 2:
- return 6; /* call8 */
- case 3:
- return 5; /* call12 */
- }
- break;
- case 6:
- switch (Field_n_Slot_inst_get (insn))
- {
- case 0:
- return 80; /* j */
- case 1:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 72; /* beqz */
- case 1:
- return 73; /* bnez */
- case 2:
- return 75; /* bltz */
- case 3:
- return 74; /* bgez */
- }
- break;
- case 2:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 52; /* beqi */
- case 1:
- return 53; /* bnei */
- case 2:
- return 55; /* blti */
- case 3:
- return 54; /* bgei */
- }
- break;
- case 3:
- switch (Field_m_Slot_inst_get (insn))
- {
- case 0:
- return 11; /* entry */
- case 1:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 371; /* bf */
- case 1:
- return 372; /* bt */
- case 8:
- return 87; /* loop */
- case 9:
- return 88; /* loopnez */
- case 10:
- return 89; /* loopgtz */
- }
- break;
- case 2:
- return 59; /* bltui */
- case 3:
- return 58; /* bgeui */
- }
- break;
- }
- break;
- case 7:
- switch (Field_r_Slot_inst_get (insn))
- {
- case 0:
- return 67; /* bnone */
- case 1:
- return 60; /* beq */
- case 2:
- return 63; /* blt */
- case 3:
- return 65; /* bltu */
- case 4:
- return 68; /* ball */
- case 5:
- return 70; /* bbc */
- case 6:
- case 7:
- return 56; /* bbci */
- case 8:
- return 66; /* bany */
- case 9:
- return 61; /* bne */
- case 10:
- return 62; /* bge */
- case 11:
- return 64; /* bgeu */
- case 12:
- return 69; /* bnall */
- case 13:
- return 71; /* bbs */
- case 14:
- case 15:
- return 57; /* bbsi */
- }
- break;
- }
- return 0;
- }
- static int
- Slot_inst16b_decode (const xtensa_insnbuf insn)
- {
- switch (Field_op0_Slot_inst16b_get (insn))
- {
- case 12:
- switch (Field_i_Slot_inst16b_get (insn))
- {
- case 0:
- return 33; /* movi.n */
- case 1:
- switch (Field_z_Slot_inst16b_get (insn))
- {
- case 0:
- return 28; /* beqz.n */
- case 1:
- return 29; /* bnez.n */
- }
- break;
- }
- break;
- case 13:
- switch (Field_r_Slot_inst16b_get (insn))
- {
- case 0:
- return 32; /* mov.n */
- case 15:
- switch (Field_t_Slot_inst16b_get (insn))
- {
- case 0:
- return 35; /* ret.n */
- case 1:
- return 15; /* retw.n */
- case 2:
- return 325; /* break.n */
- case 3:
- if (Field_s_Slot_inst16b_get (insn) == 0)
- return 34; /* nop.n */
- break;
- case 6:
- if (Field_s_Slot_inst16b_get (insn) == 0)
- return 30; /* ill.n */
- break;
- }
- break;
- }
- break;
- }
- return 0;
- }
- static int
- Slot_inst16a_decode (const xtensa_insnbuf insn)
- {
- switch (Field_op0_Slot_inst16a_get (insn))
- {
- case 8:
- return 31; /* l32i.n */
- case 9:
- return 36; /* s32i.n */
- case 10:
- return 26; /* add.n */
- case 11:
- return 27; /* addi.n */
- }
- return 0;
- }
- static int
- Slot_xt_flix64_slot2_decode (const xtensa_insnbuf insn)
- {
- switch (Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn))
- {
- case 0:
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
- return 41; /* add */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
- return 42; /* sub */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
- return 43; /* addx2 */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
- return 49; /* and */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
- return 450; /* sext */
- break;
- case 1:
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 1)
- return 27; /* addi.n */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 2)
- return 44; /* addx4 */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 3)
- return 50; /* or */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 5)
- return 51; /* xor */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 4)
- return 113; /* srli */
- break;
- }
- if (Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0 &&
- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6)
- return 33; /* movi.n */
- if (Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 2 &&
- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
- return 32; /* mov.n */
- if (Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
- return 97; /* nop */
- if (Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 8 &&
- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
- return 96; /* abs */
- if (Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 9 &&
- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
- return 95; /* neg */
- if (Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 5 &&
- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
- return 110; /* sra */
- if (Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 3 &&
- Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 6 &&
- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get (insn) == 0)
- return 109; /* srl */
- if (Field_op0_s5_Slot_xt_flix64_slot2_get (insn) == 7)
- return 112; /* srai */
- return 0;
- }
- static int
- Slot_xt_flix64_slot0_decode (const xtensa_insnbuf insn)
- {
- switch (Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn))
- {
- case 0:
- if (Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get (insn) == 2)
- return 78; /* extui */
- switch (Field_op1_Slot_xt_flix64_slot0_get (insn))
- {
- case 0:
- switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
- {
- case 0:
- if (Field_r_Slot_xt_flix64_slot0_get (insn) == 2)
- {
- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
- {
- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 15)
- return 97; /* nop */
- }
- }
- break;
- case 1:
- return 49; /* and */
- case 2:
- return 50; /* or */
- case 3:
- return 51; /* xor */
- case 4:
- switch (Field_r_Slot_xt_flix64_slot0_get (insn))
- {
- case 0:
- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
- return 102; /* ssr */
- break;
- case 1:
- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
- return 103; /* ssl */
- break;
- case 2:
- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
- return 104; /* ssa8l */
- break;
- case 3:
- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
- return 105; /* ssa8b */
- break;
- case 4:
- if (Field_thi3_Slot_xt_flix64_slot0_get (insn) == 0)
- return 106; /* ssai */
- break;
- case 14:
- return 448; /* nsa */
- case 15:
- return 449; /* nsau */
- }
- break;
- case 6:
- switch (Field_s_Slot_xt_flix64_slot0_get (insn))
- {
- case 0:
- return 95; /* neg */
- case 1:
- return 96; /* abs */
- }
- break;
- case 8:
- return 41; /* add */
- case 9:
- return 43; /* addx2 */
- case 10:
- return 44; /* addx4 */
- case 11:
- return 45; /* addx8 */
- case 12:
- return 42; /* sub */
- case 13:
- return 46; /* subx2 */
- case 14:
- return 47; /* subx4 */
- case 15:
- return 48; /* subx8 */
- }
- break;
- case 1:
- if (Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get (insn) == 1)
- return 112; /* srai */
- if (Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get (insn) == 0)
- return 111; /* slli */
- switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
- {
- case 4:
- return 113; /* srli */
- case 8:
- return 108; /* src */
- case 9:
- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
- return 109; /* srl */
- break;
- case 10:
- if (Field_t_Slot_xt_flix64_slot0_get (insn) == 0)
- return 107; /* sll */
- break;
- case 11:
- if (Field_s_Slot_xt_flix64_slot0_get (insn) == 0)
- return 110; /* sra */
- break;
- case 12:
- return 296; /* mul16u */
- case 13:
- return 297; /* mul16s */
- }
- break;
- case 2:
- if (Field_op2_Slot_xt_flix64_slot0_get (insn) == 8)
- return 461; /* mull */
- break;
- case 3:
- switch (Field_op2_Slot_xt_flix64_slot0_get (insn))
- {
- case 2:
- return 450; /* sext */
- case 3:
- return 443; /* clamps */
- case 4:
- return 444; /* min */
- case 5:
- return 445; /* max */
- case 6:
- return 446; /* minu */
- case 7:
- return 447; /* maxu */
- case 8:
- return 91; /* moveqz */
- case 9:
- return 92; /* movnez */
- case 10:
- return 93; /* movltz */
- case 11:
- return 94; /* movgez */
- }
- break;
- }
- break;
- case 2:
- switch (Field_r_Slot_xt_flix64_slot0_get (insn))
- {
- case 0:
- return 86; /* l8ui */
- case 1:
- return 82; /* l16ui */
- case 2:
- return 84; /* l32i */
- case 4:
- return 101; /* s8i */
- case 5:
- return 99; /* s16i */
- case 6:
- return 100; /* s32i */
- case 9:
- return 83; /* l16si */
- case 10:
- return 90; /* movi */
- case 12:
- return 39; /* addi */
- case 13:
- return 40; /* addmi */
- }
- break;
- }
- if (Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 1)
- return 85; /* l32r */
- if (Field_sae4_Slot_xt_flix64_slot0_get (insn) == 0 &&
- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get (insn) == 3 &&
- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get (insn) == 0 &&
- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get (insn) == 0)
- return 32; /* mov.n */
- return 0;
- }
- static int
- Slot_xt_flix64_slot1_decode (const xtensa_insnbuf insn)
- {
- if (Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
- return 78; /* extui */
- switch (Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
- {
- case 0:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 90; /* movi */
- break;
- case 2:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
- return 39; /* addi */
- break;
- case 3:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 1)
- return 40; /* addmi */
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get (insn) == 0)
- return 51; /* xor */
- break;
- }
- switch (Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
- {
- case 8:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 111; /* slli */
- break;
- case 16:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 112; /* srai */
- break;
- case 19:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 107; /* sll */
- break;
- }
- switch (Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn))
- {
- case 18:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 41; /* add */
- break;
- case 19:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 45; /* addx8 */
- break;
- case 20:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 43; /* addx2 */
- break;
- case 21:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 49; /* and */
- break;
- case 22:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 91; /* moveqz */
- break;
- case 23:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 94; /* movgez */
- break;
- case 24:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 44; /* addx4 */
- break;
- case 25:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 93; /* movltz */
- break;
- case 26:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 92; /* movnez */
- break;
- case 27:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 296; /* mul16u */
- break;
- case 28:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 297; /* mul16s */
- break;
- case 29:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 461; /* mull */
- break;
- case 30:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 50; /* or */
- break;
- case 31:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 450; /* sext */
- break;
- case 34:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 108; /* src */
- break;
- case 36:
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2)
- return 113; /* srli */
- break;
- }
- if (Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 280 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 32; /* mov.n */
- if (Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 281 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 81; /* jx */
- if (Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 141 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 103; /* ssl */
- if (Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 71 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 97; /* nop */
- if (Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 148 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 95; /* neg */
- if (Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 149 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 110; /* sra */
- if (Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 75 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 109; /* srl */
- if (Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 5 &&
- Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 2 &&
- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get (insn) == 0)
- return 42; /* sub */
- if (Field_op0_s4_Slot_xt_flix64_slot1_get (insn) == 3)
- return 80; /* j */
- return 0;
- }
- static int
- Slot_xt_flix64_slot3_decode (const xtensa_insnbuf insn)
- {
- switch (Field_op0_s6_Slot_xt_flix64_slot3_get (insn))
- {
- case 1:
- if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
- return 516; /* bbci.w18 */
- break;
- case 2:
- if (Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get (insn) == 0)
- return 517; /* bbsi.w18 */
- break;
- case 3:
- if (Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 526; /* ball.w18 */
- break;
- case 4:
- if (Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 524; /* bany.w18 */
- break;
- case 5:
- if (Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 528; /* bbc.w18 */
- break;
- case 6:
- if (Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 529; /* bbs.w18 */
- break;
- case 7:
- if (Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 518; /* beq.w18 */
- break;
- case 8:
- if (Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 510; /* beqi.w18 */
- break;
- case 9:
- if (Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 520; /* bge.w18 */
- break;
- case 10:
- if (Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 512; /* bgei.w18 */
- break;
- case 11:
- if (Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 522; /* bgeu.w18 */
- break;
- case 12:
- if (Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 514; /* bgeui.w18 */
- break;
- case 13:
- if (Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 521; /* blt.w18 */
- break;
- case 14:
- if (Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 513; /* blti.w18 */
- break;
- case 15:
- if (Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 523; /* bltu.w18 */
- break;
- case 16:
- if (Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 515; /* bltui.w18 */
- break;
- case 17:
- if (Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 527; /* bnall.w18 */
- break;
- case 18:
- if (Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 519; /* bne.w18 */
- break;
- case 19:
- if (Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 511; /* bnei.w18 */
- break;
- case 20:
- if (Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 525; /* bnone.w18 */
- break;
- case 21:
- if (Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 506; /* beqz.w18 */
- break;
- case 22:
- if (Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 508; /* bgez.w18 */
- break;
- case 23:
- if (Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 509; /* bltz.w18 */
- break;
- case 24:
- if (Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 507; /* bnez.w18 */
- break;
- case 25:
- if (Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get (insn) == 0)
- return 97; /* nop */
- break;
- }
- return 0;
- }
- /* Instruction slots. */
- static void
- Slot_x24_Format_inst_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
- {
- slotbuf[1] = 0;
- slotbuf[0] = (insn[0] & 0xffffff);
- }
- static void
- Slot_x24_Format_inst_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
- {
- insn[0] = (insn[0] & ~0xffffff) | (slotbuf[0] & 0xffffff);
- }
- static void
- Slot_x16a_Format_inst16a_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
- {
- slotbuf[1] = 0;
- slotbuf[0] = (insn[0] & 0xffff);
- }
- static void
- Slot_x16a_Format_inst16a_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
- {
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
- }
- static void
- Slot_x16b_Format_inst16b_0_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
- {
- slotbuf[1] = 0;
- slotbuf[0] = (insn[0] & 0xffff);
- }
- static void
- Slot_x16b_Format_inst16b_0_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
- {
- insn[0] = (insn[0] & ~0xffff) | (slotbuf[0] & 0xffff);
- }
- static void
- Slot_xt_format1_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
- {
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
- }
- static void
- Slot_xt_format1_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
- {
- insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
- }
- static void
- Slot_xt_format2_Format_xt_flix64_slot0_4_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
- {
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[0] & 0xffffff0) >> 4);
- }
- static void
- Slot_xt_format2_Format_xt_flix64_slot0_4_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
- {
- insn[0] = (insn[0] & ~0xffffff0) | ((slotbuf[0] & 0xffffff) << 4);
- }
- static void
- Slot_xt_format1_Format_xt_flix64_slot1_28_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
- {
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
- slotbuf[0] = (slotbuf[0] & ~0xffff0) | ((insn[1] & 0xffff) << 4);
- }
- static void
- Slot_xt_format1_Format_xt_flix64_slot1_28_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
- {
- insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
- insn[1] = (insn[1] & ~0xffff) | ((slotbuf[0] & 0xffff0) >> 4);
- }
- static void
- Slot_xt_format1_Format_xt_flix64_slot2_48_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
- {
- slotbuf[1] = 0;
- slotbuf[0] = ((insn[1] & 0xffff0000) >> 16);
- }
- static void
- Slot_xt_format1_Format_xt_flix64_slot2_48_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
- {
- insn[1] = (insn[1] & ~0xffff0000) | ((slotbuf[0] & 0xffff) << 16);
- }
- static void
- Slot_xt_format2_Format_xt_flix64_slot3_28_get (const xtensa_insnbuf insn,
- xtensa_insnbuf slotbuf)
- {
- slotbuf[0] = ((insn[0] & 0xf0000000) >> 28);
- slotbuf[0] = (slotbuf[0] & ~0xfffffff0) | ((insn[1] & 0xfffffff) << 4);
- slotbuf[1] = ((insn[1] & 0x70000000) >> 28);
- }
- static void
- Slot_xt_format2_Format_xt_flix64_slot3_28_set (xtensa_insnbuf insn,
- const xtensa_insnbuf slotbuf)
- {
- insn[0] = (insn[0] & ~0xf0000000) | ((slotbuf[0] & 0xf) << 28);
- insn[1] = (insn[1] & ~0xfffffff) | ((slotbuf[0] & 0xfffffff0) >> 4);
- insn[1] = (insn[1] & ~0x70000000) | ((slotbuf[1] & 0x7) << 28);
- }
- static const xtensa_get_field_fn
- Slot_inst_get_field_fns[] = {
- Field_t_Slot_inst_get,
- Field_bbi4_Slot_inst_get,
- Field_bbi_Slot_inst_get,
- Field_imm12_Slot_inst_get,
- Field_imm8_Slot_inst_get,
- Field_s_Slot_inst_get,
- Field_imm12b_Slot_inst_get,
- Field_imm16_Slot_inst_get,
- Field_m_Slot_inst_get,
- Field_n_Slot_inst_get,
- Field_offset_Slot_inst_get,
- Field_op0_Slot_inst_get,
- Field_op1_Slot_inst_get,
- Field_op2_Slot_inst_get,
- Field_r_Slot_inst_get,
- Field_sa4_Slot_inst_get,
- Field_sae4_Slot_inst_get,
- Field_sae_Slot_inst_get,
- Field_sal_Slot_inst_get,
- Field_sargt_Slot_inst_get,
- Field_sas4_Slot_inst_get,
- Field_sas_Slot_inst_get,
- Field_sr_Slot_inst_get,
- Field_st_Slot_inst_get,
- Field_thi3_Slot_inst_get,
- Field_imm4_Slot_inst_get,
- Field_mn_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_get,
- Field_rbit2_Slot_inst_get,
- Field_rhi_Slot_inst_get,
- Field_t3_Slot_inst_get,
- Field_tbit2_Slot_inst_get,
- Field_tlo_Slot_inst_get,
- Field_w_Slot_inst_get,
- Field_y_Slot_inst_get,
- Field_x_Slot_inst_get,
- Field_t2_Slot_inst_get,
- Field_s2_Slot_inst_get,
- Field_r2_Slot_inst_get,
- Field_t4_Slot_inst_get,
- Field_s4_Slot_inst_get,
- Field_r4_Slot_inst_get,
- Field_t8_Slot_inst_get,
- Field_s8_Slot_inst_get,
- Field_r8_Slot_inst_get,
- Field_xt_wbr15_imm_Slot_inst_get,
- Field_xt_wbr18_imm_Slot_inst_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
- };
- static const xtensa_set_field_fn
- Slot_inst_set_field_fns[] = {
- Field_t_Slot_inst_set,
- Field_bbi4_Slot_inst_set,
- Field_bbi_Slot_inst_set,
- Field_imm12_Slot_inst_set,
- Field_imm8_Slot_inst_set,
- Field_s_Slot_inst_set,
- Field_imm12b_Slot_inst_set,
- Field_imm16_Slot_inst_set,
- Field_m_Slot_inst_set,
- Field_n_Slot_inst_set,
- Field_offset_Slot_inst_set,
- Field_op0_Slot_inst_set,
- Field_op1_Slot_inst_set,
- Field_op2_Slot_inst_set,
- Field_r_Slot_inst_set,
- Field_sa4_Slot_inst_set,
- Field_sae4_Slot_inst_set,
- Field_sae_Slot_inst_set,
- Field_sal_Slot_inst_set,
- Field_sargt_Slot_inst_set,
- Field_sas4_Slot_inst_set,
- Field_sas_Slot_inst_set,
- Field_sr_Slot_inst_set,
- Field_st_Slot_inst_set,
- Field_thi3_Slot_inst_set,
- Field_imm4_Slot_inst_set,
- Field_mn_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r3_Slot_inst_set,
- Field_rbit2_Slot_inst_set,
- Field_rhi_Slot_inst_set,
- Field_t3_Slot_inst_set,
- Field_tbit2_Slot_inst_set,
- Field_tlo_Slot_inst_set,
- Field_w_Slot_inst_set,
- Field_y_Slot_inst_set,
- Field_x_Slot_inst_set,
- Field_t2_Slot_inst_set,
- Field_s2_Slot_inst_set,
- Field_r2_Slot_inst_set,
- Field_t4_Slot_inst_set,
- Field_s4_Slot_inst_set,
- Field_r4_Slot_inst_set,
- Field_t8_Slot_inst_set,
- Field_s8_Slot_inst_set,
- Field_r8_Slot_inst_set,
- Field_xt_wbr15_imm_Slot_inst_set,
- Field_xt_wbr18_imm_Slot_inst_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
- };
- static const xtensa_get_field_fn
- Slot_inst16a_get_field_fns[] = {
- Field_t_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_get,
- 0,
- 0,
- Field_r_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_get,
- Field_st_Slot_inst16a_get,
- 0,
- Field_imm4_Slot_inst16a_get,
- 0,
- Field_i_Slot_inst16a_get,
- Field_imm6lo_Slot_inst16a_get,
- Field_imm6hi_Slot_inst16a_get,
- Field_imm7lo_Slot_inst16a_get,
- Field_imm7hi_Slot_inst16a_get,
- Field_z_Slot_inst16a_get,
- Field_imm6_Slot_inst16a_get,
- Field_imm7_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst16a_get,
- Field_s2_Slot_inst16a_get,
- Field_r2_Slot_inst16a_get,
- Field_t4_Slot_inst16a_get,
- Field_s4_Slot_inst16a_get,
- Field_r4_Slot_inst16a_get,
- Field_t8_Slot_inst16a_get,
- Field_s8_Slot_inst16a_get,
- Field_r8_Slot_inst16a_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
- };
- static const xtensa_set_field_fn
- Slot_inst16a_set_field_fns[] = {
- Field_t_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16a_set,
- 0,
- 0,
- Field_r_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16a_set,
- Field_st_Slot_inst16a_set,
- 0,
- Field_imm4_Slot_inst16a_set,
- 0,
- Field_i_Slot_inst16a_set,
- Field_imm6lo_Slot_inst16a_set,
- Field_imm6hi_Slot_inst16a_set,
- Field_imm7lo_Slot_inst16a_set,
- Field_imm7hi_Slot_inst16a_set,
- Field_z_Slot_inst16a_set,
- Field_imm6_Slot_inst16a_set,
- Field_imm7_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst16a_set,
- Field_s2_Slot_inst16a_set,
- Field_r2_Slot_inst16a_set,
- Field_t4_Slot_inst16a_set,
- Field_s4_Slot_inst16a_set,
- Field_r4_Slot_inst16a_set,
- Field_t8_Slot_inst16a_set,
- Field_s8_Slot_inst16a_set,
- Field_r8_Slot_inst16a_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
- };
- static const xtensa_get_field_fn
- Slot_inst16b_get_field_fns[] = {
- Field_t_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_get,
- 0,
- 0,
- Field_r_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_get,
- Field_st_Slot_inst16b_get,
- 0,
- Field_imm4_Slot_inst16b_get,
- 0,
- Field_i_Slot_inst16b_get,
- Field_imm6lo_Slot_inst16b_get,
- Field_imm6hi_Slot_inst16b_get,
- Field_imm7lo_Slot_inst16b_get,
- Field_imm7hi_Slot_inst16b_get,
- Field_z_Slot_inst16b_get,
- Field_imm6_Slot_inst16b_get,
- Field_imm7_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst16b_get,
- Field_s2_Slot_inst16b_get,
- Field_r2_Slot_inst16b_get,
- Field_t4_Slot_inst16b_get,
- Field_s4_Slot_inst16b_get,
- Field_r4_Slot_inst16b_get,
- Field_t8_Slot_inst16b_get,
- Field_s8_Slot_inst16b_get,
- Field_r8_Slot_inst16b_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
- };
- static const xtensa_set_field_fn
- Slot_inst16b_set_field_fns[] = {
- Field_t_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_Slot_inst16b_set,
- 0,
- 0,
- Field_r_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_sr_Slot_inst16b_set,
- Field_st_Slot_inst16b_set,
- 0,
- Field_imm4_Slot_inst16b_set,
- 0,
- Field_i_Slot_inst16b_set,
- Field_imm6lo_Slot_inst16b_set,
- Field_imm6hi_Slot_inst16b_set,
- Field_imm7lo_Slot_inst16b_set,
- Field_imm7hi_Slot_inst16b_set,
- Field_z_Slot_inst16b_set,
- Field_imm6_Slot_inst16b_set,
- Field_imm7_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_t2_Slot_inst16b_set,
- Field_s2_Slot_inst16b_set,
- Field_r2_Slot_inst16b_set,
- Field_t4_Slot_inst16b_set,
- Field_s4_Slot_inst16b_set,
- Field_r4_Slot_inst16b_set,
- Field_t8_Slot_inst16b_set,
- Field_s8_Slot_inst16b_set,
- Field_r8_Slot_inst16b_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
- };
- static const xtensa_get_field_fn
- Slot_xt_flix64_slot0_get_field_fns[] = {
- Field_t_Slot_xt_flix64_slot0_get,
- 0,
- 0,
- 0,
- Field_imm8_Slot_xt_flix64_slot0_get,
- Field_s_Slot_xt_flix64_slot0_get,
- Field_imm12b_Slot_xt_flix64_slot0_get,
- Field_imm16_Slot_xt_flix64_slot0_get,
- Field_m_Slot_xt_flix64_slot0_get,
- Field_n_Slot_xt_flix64_slot0_get,
- 0,
- 0,
- Field_op1_Slot_xt_flix64_slot0_get,
- Field_op2_Slot_xt_flix64_slot0_get,
- Field_r_Slot_xt_flix64_slot0_get,
- 0,
- Field_sae4_Slot_xt_flix64_slot0_get,
- Field_sae_Slot_xt_flix64_slot0_get,
- Field_sal_Slot_xt_flix64_slot0_get,
- Field_sargt_Slot_xt_flix64_slot0_get,
- 0,
- Field_sas_Slot_xt_flix64_slot0_get,
- 0,
- 0,
- Field_thi3_Slot_xt_flix64_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_get,
- Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_get,
- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_get,
- Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_get,
- Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_get,
- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_get,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
- };
- static const xtensa_set_field_fn
- Slot_xt_flix64_slot0_set_field_fns[] = {
- Field_t_Slot_xt_flix64_slot0_set,
- 0,
- 0,
- 0,
- Field_imm8_Slot_xt_flix64_slot0_set,
- Field_s_Slot_xt_flix64_slot0_set,
- Field_imm12b_Slot_xt_flix64_slot0_set,
- Field_imm16_Slot_xt_flix64_slot0_set,
- Field_m_Slot_xt_flix64_slot0_set,
- Field_n_Slot_xt_flix64_slot0_set,
- 0,
- 0,
- Field_op1_Slot_xt_flix64_slot0_set,
- Field_op2_Slot_xt_flix64_slot0_set,
- Field_r_Slot_xt_flix64_slot0_set,
- 0,
- Field_sae4_Slot_xt_flix64_slot0_set,
- Field_sae_Slot_xt_flix64_slot0_set,
- Field_sal_Slot_xt_flix64_slot0_set,
- Field_sargt_Slot_xt_flix64_slot0_set,
- 0,
- Field_sas_Slot_xt_flix64_slot0_set,
- 0,
- 0,
- Field_thi3_Slot_xt_flix64_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_xt_flix64_slot0_s3_Slot_xt_flix64_slot0_set,
- Field_combined3e2c5767_fld7_Slot_xt_flix64_slot0_set,
- Field_combined3e2c5767_fld8_Slot_xt_flix64_slot0_set,
- Field_combined3e2c5767_fld9_Slot_xt_flix64_slot0_set,
- Field_combined3e2c5767_fld11_Slot_xt_flix64_slot0_set,
- Field_combined3e2c5767_fld49xt_flix64_slot0_Slot_xt_flix64_slot0_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_xt_flix64_slot0_Slot_xt_flix64_slot0_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
- };
- static const xtensa_get_field_fn
- Slot_xt_flix64_slot1_get_field_fns[] = {
- Field_t_Slot_xt_flix64_slot1_get,
- 0,
- 0,
- 0,
- Field_imm8_Slot_xt_flix64_slot1_get,
- Field_s_Slot_xt_flix64_slot1_get,
- Field_imm12b_Slot_xt_flix64_slot1_get,
- 0,
- 0,
- 0,
- Field_offset_Slot_xt_flix64_slot1_get,
- 0,
- 0,
- Field_op2_Slot_xt_flix64_slot1_get,
- Field_r_Slot_xt_flix64_slot1_get,
- 0,
- 0,
- Field_sae_Slot_xt_flix64_slot1_get,
- Field_sal_Slot_xt_flix64_slot1_get,
- Field_sargt_Slot_xt_flix64_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s4_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
- };
- static const xtensa_set_field_fn
- Slot_xt_flix64_slot1_set_field_fns[] = {
- Field_t_Slot_xt_flix64_slot1_set,
- 0,
- 0,
- 0,
- Field_imm8_Slot_xt_flix64_slot1_set,
- Field_s_Slot_xt_flix64_slot1_set,
- Field_imm12b_Slot_xt_flix64_slot1_set,
- 0,
- 0,
- 0,
- Field_offset_Slot_xt_flix64_slot1_set,
- 0,
- 0,
- Field_op2_Slot_xt_flix64_slot1_set,
- Field_r_Slot_xt_flix64_slot1_set,
- 0,
- 0,
- Field_sae_Slot_xt_flix64_slot1_set,
- Field_sal_Slot_xt_flix64_slot1_set,
- Field_sargt_Slot_xt_flix64_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s4_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld16_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld19xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld20xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld21xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld22xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld23xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld25xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld26xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld28xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld30xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld32xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld33xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld35xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld51xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld52xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld53xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld54xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld57xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld58xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld60xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- Field_combined3e2c5767_fld62xt_flix64_slot1_Slot_xt_flix64_slot1_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
- };
- static const xtensa_get_field_fn
- Slot_xt_flix64_slot2_get_field_fns[] = {
- Field_t_Slot_xt_flix64_slot2_get,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_xt_flix64_slot2_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r_Slot_xt_flix64_slot2_get,
- 0,
- 0,
- 0,
- 0,
- Field_sargt_Slot_xt_flix64_slot2_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_imm7_Slot_xt_flix64_slot2_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s5_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
- };
- static const xtensa_set_field_fn
- Slot_xt_flix64_slot2_set_field_fns[] = {
- Field_t_Slot_xt_flix64_slot2_set,
- 0,
- 0,
- 0,
- 0,
- Field_s_Slot_xt_flix64_slot2_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r_Slot_xt_flix64_slot2_set,
- 0,
- 0,
- 0,
- 0,
- Field_sargt_Slot_xt_flix64_slot2_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_imm7_Slot_xt_flix64_slot2_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s5_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld36xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld37xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld39xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld41xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld42xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld44xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld45xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld47xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld63xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld64xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld65xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld66xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- Field_combined3e2c5767_fld68xt_flix64_slot2_Slot_xt_flix64_slot2_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
- };
- static const xtensa_get_field_fn
- Slot_xt_flix64_slot3_get_field_fns[] = {
- Field_t_Slot_xt_flix64_slot3_get,
- 0,
- Field_bbi_Slot_xt_flix64_slot3_get,
- 0,
- 0,
- Field_s_Slot_xt_flix64_slot3_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r_Slot_xt_flix64_slot3_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_xt_wbr18_imm_Slot_xt_flix64_slot3_get,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s6_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_get,
- 0,
- Implicit_Field_ar0_get,
- Implicit_Field_ar4_get,
- Implicit_Field_ar8_get,
- Implicit_Field_ar12_get,
- Implicit_Field_mr0_get,
- Implicit_Field_mr1_get,
- Implicit_Field_mr2_get,
- Implicit_Field_mr3_get,
- Implicit_Field_bt16_get,
- Implicit_Field_bs16_get,
- Implicit_Field_br16_get,
- Implicit_Field_brall_get
- };
- static const xtensa_set_field_fn
- Slot_xt_flix64_slot3_set_field_fns[] = {
- Field_t_Slot_xt_flix64_slot3_set,
- 0,
- Field_bbi_Slot_xt_flix64_slot3_set,
- 0,
- 0,
- Field_s_Slot_xt_flix64_slot3_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_r_Slot_xt_flix64_slot3_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_xt_wbr18_imm_Slot_xt_flix64_slot3_set,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- Field_op0_s6_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld70xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld71_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld72xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld73xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld74xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld75xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld76xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld77xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld78xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld79xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld80xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld81xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld82xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld83xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld84xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld85xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld86xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld87xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld88xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld89xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld90xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld91xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld92xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- Field_combined3e2c5767_fld93xt_flix64_slot3_Slot_xt_flix64_slot3_set,
- 0,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set,
- Implicit_Field_set
- };
- static xtensa_slot_internal slots[] = {
- { "Inst", "x24", 0,
- Slot_x24_Format_inst_0_get, Slot_x24_Format_inst_0_set,
- Slot_inst_get_field_fns, Slot_inst_set_field_fns,
- Slot_inst_decode, "nop" },
- { "Inst16a", "x16a", 0,
- Slot_x16a_Format_inst16a_0_get, Slot_x16a_Format_inst16a_0_set,
- Slot_inst16a_get_field_fns, Slot_inst16a_set_field_fns,
- Slot_inst16a_decode, "" },
- { "Inst16b", "x16b", 0,
- Slot_x16b_Format_inst16b_0_get, Slot_x16b_Format_inst16b_0_set,
- Slot_inst16b_get_field_fns, Slot_inst16b_set_field_fns,
- Slot_inst16b_decode, "nop.n" },
- { "xt_flix64_slot0", "xt_format1", 0,
- Slot_xt_format1_Format_xt_flix64_slot0_4_get, Slot_xt_format1_Format_xt_flix64_slot0_4_set,
- Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
- Slot_xt_flix64_slot0_decode, "nop" },
- { "xt_flix64_slot0", "xt_format2", 0,
- Slot_xt_format2_Format_xt_flix64_slot0_4_get, Slot_xt_format2_Format_xt_flix64_slot0_4_set,
- Slot_xt_flix64_slot0_get_field_fns, Slot_xt_flix64_slot0_set_field_fns,
- Slot_xt_flix64_slot0_decode, "nop" },
- { "xt_flix64_slot1", "xt_format1", 1,
- Slot_xt_format1_Format_xt_flix64_slot1_28_get, Slot_xt_format1_Format_xt_flix64_slot1_28_set,
- Slot_xt_flix64_slot1_get_field_fns, Slot_xt_flix64_slot1_set_field_fns,
- Slot_xt_flix64_slot1_decode, "nop" },
- { "xt_flix64_slot2", "xt_format1", 2,
- Slot_xt_format1_Format_xt_flix64_slot2_48_get, Slot_xt_format1_Format_xt_flix64_slot2_48_set,
- Slot_xt_flix64_slot2_get_field_fns, Slot_xt_flix64_slot2_set_field_fns,
- Slot_xt_flix64_slot2_decode, "nop" },
- { "xt_flix64_slot3", "xt_format2", 1,
- Slot_xt_format2_Format_xt_flix64_slot3_28_get, Slot_xt_format2_Format_xt_flix64_slot3_28_set,
- Slot_xt_flix64_slot3_get_field_fns, Slot_xt_flix64_slot3_set_field_fns,
- Slot_xt_flix64_slot3_decode, "nop" }
- };
- /* Instruction formats. */
- static void
- Format_x24_encode (xtensa_insnbuf insn)
- {
- insn[0] = 0;
- insn[1] = 0;
- }
- static void
- Format_x16a_encode (xtensa_insnbuf insn)
- {
- insn[0] = 0x8;
- insn[1] = 0;
- }
- static void
- Format_x16b_encode (xtensa_insnbuf insn)
- {
- insn[0] = 0xc;
- insn[1] = 0;
- }
- static void
- Format_xt_format1_encode (xtensa_insnbuf insn)
- {
- insn[0] = 0xe;
- insn[1] = 0;
- }
- static void
- Format_xt_format2_encode (xtensa_insnbuf insn)
- {
- insn[0] = 0xf;
- insn[1] = 0;
- }
- static const int Format_x24_slots[] = { 0 };
- static const int Format_x16a_slots[] = { 1 };
- static const int Format_x16b_slots[] = { 2 };
- static const int Format_xt_format1_slots[] = { 3, 5, 6 };
- static const int Format_xt_format2_slots[] = { 4, 7 };
- static xtensa_format_internal formats[] = {
- { "x24", 3, Format_x24_encode, 1, Format_x24_slots },
- { "x16a", 2, Format_x16a_encode, 1, Format_x16a_slots },
- { "x16b", 2, Format_x16b_encode, 1, Format_x16b_slots },
- { "xt_format1", 8, Format_xt_format1_encode, 3, Format_xt_format1_slots },
- { "xt_format2", 8, Format_xt_format2_encode, 2, Format_xt_format2_slots }
- };
- static int
- format_decoder (const xtensa_insnbuf insn)
- {
- if ((insn[0] & 0x8) == 0 && (insn[1] & 0) == 0)
- return 0; /* x24 */
- if ((insn[0] & 0xc) == 0x8 && (insn[1] & 0) == 0)
- return 1; /* x16a */
- if ((insn[0] & 0xe) == 0xc && (insn[1] & 0) == 0)
- return 2; /* x16b */
- if ((insn[0] & 0xf) == 0xe && (insn[1] & 0) == 0)
- return 3; /* xt_format1 */
- if ((insn[0] & 0xf) == 0xf && (insn[1] & 0x80000000) == 0)
- return 4; /* xt_format2 */
- return -1;
- }
- static const int length_table[16] = {
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 3,
- 2,
- 2,
- 2,
- 2,
- 2,
- 2,
- 8,
- 8
- };
- static int
- length_decoder (const unsigned char *insn)
- {
- int op0 = insn[0] & 0xf;
- return length_table[op0];
- }
- /* Top-level ISA structure. */
- xtensa_isa_internal xtensa_modules = {
- 0 /* little-endian */,
- 8 /* insn_size */, 0,
- 5, formats, format_decoder, length_decoder,
- 8, slots,
- 135 /* num_fields */,
- 188, operands,
- 355, iclasses,
- 530, opcodes, 0,
- 8, regfiles,
- NUM_STATES, states, 0,
- NUM_SYSREGS, sysregs, 0,
- { MAX_SPECIAL_REG, MAX_USER_REG }, { 0, 0 },
- 0, interfaces, 0,
- 0, funcUnits, 0
- };
|