tc-cr16.c 65 KB

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  1. /* tc-cr16.c -- Assembler code for the CR16 CPU core.
  2. Copyright (C) 2007-2022 Free Software Foundation, Inc.
  3. Contributed by M R Swami Reddy <MR.Swami.Reddy@nsc.com>
  4. This file is part of GAS, the GNU Assembler.
  5. GAS is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 3, or (at your option)
  8. any later version.
  9. GAS is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with GAS; see the file COPYING. If not, write to the
  15. Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  16. MA 02110-1301, USA. */
  17. #include "as.h"
  18. #include "safe-ctype.h"
  19. #include "dwarf2dbg.h"
  20. #include "opcode/cr16.h"
  21. #include "elf/cr16.h"
  22. #include <limits.h>
  23. #ifndef CHAR_BIT
  24. #define CHAR_BIT 8
  25. #endif
  26. /* Word is considered here as a 16-bit unsigned short int. */
  27. #define WORD_SHIFT 16
  28. /* Register is 2-byte size. */
  29. #define REG_SIZE 2
  30. /* Maximum size of a single instruction (in words). */
  31. #define INSN_MAX_SIZE 3
  32. /* Maximum bits which may be set in a `mask16' operand. */
  33. #define MAX_REGS_IN_MASK16 8
  34. /* Assign a number NUM, shifted by SHIFT bytes, into a location
  35. pointed by index BYTE of array 'output_opcode'. */
  36. #define CR16_PRINT(BYTE, NUM, SHIFT) output_opcode[BYTE] |= (NUM) << (SHIFT)
  37. /* Operand errors. */
  38. typedef enum
  39. {
  40. OP_LEGAL = 0, /* Legal operand. */
  41. OP_OUT_OF_RANGE, /* Operand not within permitted range. */
  42. OP_NOT_EVEN /* Operand is Odd number, should be even. */
  43. }
  44. op_err;
  45. /* Opcode mnemonics hash table. */
  46. static htab_t cr16_inst_hash;
  47. /* CR16 registers hash table. */
  48. static htab_t reg_hash;
  49. /* CR16 register pair hash table. */
  50. static htab_t regp_hash;
  51. /* CR16 processor registers hash table. */
  52. static htab_t preg_hash;
  53. /* CR16 processor registers 32 bit hash table. */
  54. static htab_t pregp_hash;
  55. /* Current instruction we're assembling. */
  56. const inst *instruction;
  57. static int code_label = 0;
  58. /* Global variables. */
  59. /* Array to hold an instruction encoding. */
  60. long output_opcode[2];
  61. /* Nonzero means a relocatable symbol. */
  62. int relocatable;
  63. /* A copy of the original instruction (used in error messages). */
  64. char ins_parse[MAX_INST_LEN];
  65. /* The current processed argument number. */
  66. int cur_arg_num;
  67. /* Generic assembler global variables which must be defined by all targets. */
  68. /* Characters which always start a comment. */
  69. const char comment_chars[] = "#";
  70. /* Characters which start a comment at the beginning of a line. */
  71. const char line_comment_chars[] = "#";
  72. /* This array holds machine specific line separator characters. */
  73. const char line_separator_chars[] = ";";
  74. /* Chars that can be used to separate mant from exp in floating point nums. */
  75. const char EXP_CHARS[] = "eE";
  76. /* Chars that mean this number is a floating point constant as in 0f12.456 */
  77. const char FLT_CHARS[] = "f'";
  78. #ifdef OBJ_ELF
  79. /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
  80. symbolS * GOT_symbol;
  81. #endif
  82. /* Target-specific multicharacter options, not const-declared at usage. */
  83. const char *md_shortopts = "";
  84. struct option md_longopts[] =
  85. {
  86. {NULL, no_argument, NULL, 0}
  87. };
  88. size_t md_longopts_size = sizeof (md_longopts);
  89. static void
  90. l_cons (int nbytes)
  91. {
  92. int c;
  93. expressionS exp;
  94. #ifdef md_flush_pending_output
  95. md_flush_pending_output ();
  96. #endif
  97. if (is_it_end_of_statement ())
  98. {
  99. demand_empty_rest_of_line ();
  100. return;
  101. }
  102. #ifdef TC_ADDRESS_BYTES
  103. if (nbytes == 0)
  104. nbytes = TC_ADDRESS_BYTES ();
  105. #endif
  106. #ifdef md_cons_align
  107. md_cons_align (nbytes);
  108. #endif
  109. c = 0;
  110. do
  111. {
  112. unsigned int bits_available = BITS_PER_CHAR * nbytes;
  113. char *hold = input_line_pointer;
  114. expression (&exp);
  115. if (*input_line_pointer == ':')
  116. {
  117. /* Bitfields. */
  118. long value = 0;
  119. for (;;)
  120. {
  121. unsigned long width;
  122. if (*input_line_pointer != ':')
  123. {
  124. input_line_pointer = hold;
  125. break;
  126. }
  127. if (exp.X_op == O_absent)
  128. {
  129. as_warn (_("using a bit field width of zero"));
  130. exp.X_add_number = 0;
  131. exp.X_op = O_constant;
  132. }
  133. if (exp.X_op != O_constant)
  134. {
  135. *input_line_pointer = '\0';
  136. as_bad (_("field width \"%s\" too complex for a bitfield"),
  137. hold);
  138. *input_line_pointer = ':';
  139. demand_empty_rest_of_line ();
  140. return;
  141. }
  142. if ((width = exp.X_add_number) >
  143. (unsigned int)(BITS_PER_CHAR * nbytes))
  144. {
  145. as_warn (ngettext ("field width %lu too big to fit in %d"
  146. " byte: truncated to %d bits",
  147. "field width %lu too big to fit in %d"
  148. " bytes: truncated to %d bits",
  149. nbytes),
  150. width, nbytes, (BITS_PER_CHAR * nbytes));
  151. width = BITS_PER_CHAR * nbytes;
  152. }
  153. if (width > bits_available)
  154. {
  155. /* FIXME-SOMEDAY: backing up and reparsing is wasteful. */
  156. input_line_pointer = hold;
  157. exp.X_add_number = value;
  158. break;
  159. }
  160. /* Skip ':'. */
  161. hold = ++input_line_pointer;
  162. expression (&exp);
  163. if (exp.X_op != O_constant)
  164. {
  165. char cache = *input_line_pointer;
  166. *input_line_pointer = '\0';
  167. as_bad (_("field value \"%s\" too complex for a bitfield"),
  168. hold);
  169. *input_line_pointer = cache;
  170. demand_empty_rest_of_line ();
  171. return;
  172. }
  173. value |= ((~(-(1 << width)) & exp.X_add_number)
  174. << ((BITS_PER_CHAR * nbytes) - bits_available));
  175. if ((bits_available -= width) == 0
  176. || is_it_end_of_statement ()
  177. || *input_line_pointer != ',')
  178. break;
  179. hold = ++input_line_pointer;
  180. expression (&exp);
  181. }
  182. exp.X_add_number = value;
  183. exp.X_op = O_constant;
  184. exp.X_unsigned = 1;
  185. }
  186. if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
  187. code_label = 1;
  188. emit_expr (&exp, (unsigned int) nbytes);
  189. ++c;
  190. if ((*(input_line_pointer) == '@') && (*(input_line_pointer +1) == 'c'))
  191. {
  192. input_line_pointer +=3;
  193. break;
  194. }
  195. }
  196. while ((*input_line_pointer++ == ','));
  197. /* Put terminator back into stream. */
  198. input_line_pointer--;
  199. demand_empty_rest_of_line ();
  200. }
  201. /* This table describes all the machine specific pseudo-ops
  202. the assembler has to support. The fields are:
  203. *** Pseudo-op name without dot.
  204. *** Function to call to execute this pseudo-op.
  205. *** Integer arg to pass to the function. */
  206. const pseudo_typeS md_pseudo_table[] =
  207. {
  208. /* In CR16 machine, align is in bytes (not a ptwo boundary). */
  209. {"align", s_align_bytes, 0},
  210. {"long", l_cons, 4 },
  211. {"4byte", l_cons, 4 },
  212. {0, 0, 0}
  213. };
  214. /* CR16 relaxation table. */
  215. const relax_typeS md_relax_table[] =
  216. {
  217. /* bCC */
  218. {0x7f, -0x80, 2, 1}, /* 8 */
  219. {0xfffe, -0x10000, 4, 2}, /* 16 */
  220. {0xfffffe, -0x1000000, 6, 0}, /* 24 */
  221. };
  222. /* Return the bit size for a given operand. */
  223. static int
  224. get_opbits (operand_type op)
  225. {
  226. if (op < MAX_OPRD)
  227. return cr16_optab[op].bit_size;
  228. return 0;
  229. }
  230. /* Return the argument type of a given operand. */
  231. static argtype
  232. get_optype (operand_type op)
  233. {
  234. if (op < MAX_OPRD)
  235. return cr16_optab[op].arg_type;
  236. else
  237. return nullargs;
  238. }
  239. /* Return the flags of a given operand. */
  240. static int
  241. get_opflags (operand_type op)
  242. {
  243. if (op < MAX_OPRD)
  244. return cr16_optab[op].flags;
  245. return 0;
  246. }
  247. /* Get the cc code. */
  248. static int
  249. get_cc (char *cc_name)
  250. {
  251. unsigned int i;
  252. for (i = 0; i < cr16_num_cc; i++)
  253. if (strcmp (cc_name, cr16_b_cond_tab[i]) == 0)
  254. return i;
  255. return -1;
  256. }
  257. /* Get the core processor register 'reg_name'. */
  258. static reg
  259. get_register (char *reg_name)
  260. {
  261. const reg_entry *rreg;
  262. rreg = (const reg_entry *) str_hash_find (reg_hash, reg_name);
  263. if (rreg != NULL)
  264. return rreg->value.reg_val;
  265. return nullregister;
  266. }
  267. /* Get the core processor register-pair 'reg_name'. */
  268. static reg
  269. get_register_pair (char *reg_name)
  270. {
  271. const reg_entry *rreg;
  272. char tmp_rp[16]="\0";
  273. /* Add '(' and ')' to the reg pair, if it's not present. */
  274. if (reg_name[0] != '(')
  275. {
  276. tmp_rp[0] = '(';
  277. strcat (tmp_rp, reg_name);
  278. strcat (tmp_rp,")");
  279. rreg = (const reg_entry *) str_hash_find (regp_hash, tmp_rp);
  280. }
  281. else
  282. rreg = (const reg_entry *) str_hash_find (regp_hash, reg_name);
  283. if (rreg != NULL)
  284. return rreg->value.reg_val;
  285. return nullregister;
  286. }
  287. /* Get the index register 'reg_name'. */
  288. static reg
  289. get_index_register (char *reg_name)
  290. {
  291. const reg_entry *rreg;
  292. rreg = (const reg_entry *) str_hash_find (reg_hash, reg_name);
  293. if ((rreg != NULL)
  294. && ((rreg->value.reg_val == 12) || (rreg->value.reg_val == 13)))
  295. return rreg->value.reg_val;
  296. return nullregister;
  297. }
  298. /* Get the core processor index register-pair 'reg_name'. */
  299. static reg
  300. get_index_register_pair (char *reg_name)
  301. {
  302. const reg_entry *rreg;
  303. rreg = (const reg_entry *) str_hash_find (regp_hash, reg_name);
  304. if (rreg != NULL)
  305. {
  306. if ((rreg->value.reg_val != 1) || (rreg->value.reg_val != 7)
  307. || (rreg->value.reg_val != 9) || (rreg->value.reg_val > 10))
  308. return rreg->value.reg_val;
  309. as_bad (_("Unknown register pair - index relative mode: `%d'"), rreg->value.reg_val);
  310. }
  311. return nullregister;
  312. }
  313. /* Get the processor register 'preg_name'. */
  314. static preg
  315. get_pregister (char *preg_name)
  316. {
  317. const reg_entry *prreg;
  318. prreg = (const reg_entry *) str_hash_find (preg_hash, preg_name);
  319. if (prreg != NULL)
  320. return prreg->value.preg_val;
  321. return nullpregister;
  322. }
  323. /* Get the processor register 'preg_name 32 bit'. */
  324. static preg
  325. get_pregisterp (char *preg_name)
  326. {
  327. const reg_entry *prreg;
  328. prreg = (const reg_entry *) str_hash_find (pregp_hash, preg_name);
  329. if (prreg != NULL)
  330. return prreg->value.preg_val;
  331. return nullpregister;
  332. }
  333. /* Round up a section size to the appropriate boundary. */
  334. valueT
  335. md_section_align (segT seg, valueT val)
  336. {
  337. /* Round .text section to a multiple of 2. */
  338. if (seg == text_section)
  339. return (val + 1) & ~1;
  340. return val;
  341. }
  342. /* Parse an operand that is machine-specific (remove '*'). */
  343. void
  344. md_operand (expressionS * exp)
  345. {
  346. char c = *input_line_pointer;
  347. switch (c)
  348. {
  349. case '*':
  350. input_line_pointer++;
  351. expression (exp);
  352. break;
  353. default:
  354. break;
  355. }
  356. }
  357. /* Reset global variables before parsing a new instruction. */
  358. static void
  359. reset_vars (char *op)
  360. {
  361. cur_arg_num = relocatable = 0;
  362. memset (& output_opcode, '\0', sizeof (output_opcode));
  363. /* Save a copy of the original OP (used in error messages). */
  364. strncpy (ins_parse, op, sizeof ins_parse - 1);
  365. ins_parse [sizeof ins_parse - 1] = 0;
  366. }
  367. /* This macro decides whether a particular reloc is an entry in a
  368. switch table. It is used when relaxing, because the linker needs
  369. to know about all such entries so that it can adjust them if
  370. necessary. */
  371. #define SWITCH_TABLE(fix) \
  372. ((fix)->fx_addsy != NULL \
  373. && (fix)->fx_subsy != NULL \
  374. && ((fix)->fx_r_type == BFD_RELOC_CR16_NUM8 \
  375. || (fix)->fx_r_type == BFD_RELOC_CR16_NUM16 \
  376. || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32 \
  377. || (fix)->fx_r_type == BFD_RELOC_CR16_NUM32a) \
  378. && S_GET_SEGMENT ((fix)->fx_addsy) != undefined_section \
  379. && S_GET_SEGMENT ((fix)->fx_addsy) == S_GET_SEGMENT ((fix)->fx_subsy))
  380. /* See whether we need to force a relocation into the output file.
  381. This is used to force out switch and PC relative relocations when
  382. relaxing. */
  383. int
  384. cr16_force_relocation (fixS *fix)
  385. {
  386. if (generic_force_reloc (fix) || SWITCH_TABLE (fix))
  387. return 1;
  388. return 0;
  389. }
  390. /* Record a fixup for a cons expression. */
  391. void
  392. cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp,
  393. bfd_reloc_code_real_type rtype)
  394. {
  395. switch (len)
  396. {
  397. default: rtype = BFD_RELOC_NONE; break;
  398. case 1: rtype = BFD_RELOC_CR16_NUM8 ; break;
  399. case 2: rtype = BFD_RELOC_CR16_NUM16; break;
  400. case 4:
  401. if (code_label)
  402. {
  403. rtype = BFD_RELOC_CR16_NUM32a;
  404. code_label = 0;
  405. }
  406. else
  407. rtype = BFD_RELOC_CR16_NUM32;
  408. break;
  409. }
  410. fix_new_exp (frag, offset, len, exp, 0, rtype);
  411. }
  412. /* Generate a relocation entry for a fixup. */
  413. arelent *
  414. tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS * fixP)
  415. {
  416. arelent * reloc;
  417. /* If symbols are local and resolved, then no relocation needed. */
  418. if ( ((fixP->fx_addsy)
  419. && (S_GET_SEGMENT (fixP->fx_addsy) == absolute_section))
  420. || ((fixP->fx_subsy)
  421. && (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section)))
  422. return NULL;
  423. reloc = XNEW (arelent);
  424. reloc->sym_ptr_ptr = XNEW (asymbol *);
  425. *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
  426. reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
  427. reloc->addend = fixP->fx_offset;
  428. if (fixP->fx_subsy != NULL)
  429. {
  430. if (SWITCH_TABLE (fixP))
  431. {
  432. /* Keep the current difference in the addend. */
  433. reloc->addend = (S_GET_VALUE (fixP->fx_addsy)
  434. - S_GET_VALUE (fixP->fx_subsy) + fixP->fx_offset);
  435. switch (fixP->fx_r_type)
  436. {
  437. case BFD_RELOC_CR16_NUM8:
  438. fixP->fx_r_type = BFD_RELOC_CR16_SWITCH8;
  439. break;
  440. case BFD_RELOC_CR16_NUM16:
  441. fixP->fx_r_type = BFD_RELOC_CR16_SWITCH16;
  442. break;
  443. case BFD_RELOC_CR16_NUM32:
  444. fixP->fx_r_type = BFD_RELOC_CR16_SWITCH32;
  445. break;
  446. case BFD_RELOC_CR16_NUM32a:
  447. fixP->fx_r_type = BFD_RELOC_CR16_NUM32a;
  448. break;
  449. default:
  450. abort ();
  451. break;
  452. }
  453. }
  454. else
  455. {
  456. /* We only resolve difference expressions in the same section. */
  457. as_bad_subtract (fixP);
  458. free (reloc->sym_ptr_ptr);
  459. free (reloc);
  460. return NULL;
  461. }
  462. }
  463. #ifdef OBJ_ELF
  464. if ((fixP->fx_r_type == BFD_RELOC_CR16_GOT_REGREL20)
  465. && GOT_symbol
  466. && fixP->fx_addsy == GOT_symbol)
  467. {
  468. reloc->addend = fixP->fx_offset = reloc->address;
  469. }
  470. else if ((fixP->fx_r_type == BFD_RELOC_CR16_GOTC_REGREL20)
  471. && GOT_symbol
  472. && fixP->fx_addsy == GOT_symbol)
  473. {
  474. reloc->addend = fixP->fx_offset = reloc->address;
  475. }
  476. #endif
  477. gas_assert ((int) fixP->fx_r_type > 0);
  478. reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
  479. if (reloc->howto == NULL)
  480. {
  481. as_bad_where (fixP->fx_file, fixP->fx_line,
  482. _("internal error: reloc %d (`%s') not supported by object file format"),
  483. fixP->fx_r_type,
  484. bfd_get_reloc_code_name (fixP->fx_r_type));
  485. return NULL;
  486. }
  487. gas_assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
  488. return reloc;
  489. }
  490. /* Prepare machine-dependent frags for relaxation. */
  491. int
  492. md_estimate_size_before_relax (fragS *fragp, asection *seg)
  493. {
  494. /* If symbol is undefined or located in a different section,
  495. select the largest supported relocation. */
  496. relax_substateT subtype;
  497. relax_substateT rlx_state[] = {0, 2};
  498. for (subtype = 0; subtype < ARRAY_SIZE (rlx_state); subtype += 2)
  499. {
  500. if (fragp->fr_subtype == rlx_state[subtype]
  501. && (!S_IS_DEFINED (fragp->fr_symbol)
  502. || seg != S_GET_SEGMENT (fragp->fr_symbol)))
  503. {
  504. fragp->fr_subtype = rlx_state[subtype + 1];
  505. break;
  506. }
  507. }
  508. if (fragp->fr_subtype >= ARRAY_SIZE (md_relax_table))
  509. abort ();
  510. return md_relax_table[fragp->fr_subtype].rlx_length;
  511. }
  512. void
  513. md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, asection *sec, fragS *fragP)
  514. {
  515. /* 'opcode' points to the start of the instruction, whether
  516. we need to change the instruction's fixed encoding. */
  517. char *opcode = &fragP->fr_literal[0] + fragP->fr_fix;
  518. bfd_reloc_code_real_type reloc;
  519. subseg_change (sec, 0);
  520. switch (fragP->fr_subtype)
  521. {
  522. case 0:
  523. reloc = BFD_RELOC_CR16_DISP8;
  524. break;
  525. case 1:
  526. /* If the subtype is not changed due to :m operand qualifier,
  527. then no need to update the opcode value. */
  528. if ((int)opcode[1] != 0x18)
  529. {
  530. opcode[0] = (opcode[0] & 0xf0);
  531. opcode[1] = 0x18;
  532. }
  533. reloc = BFD_RELOC_CR16_DISP16;
  534. break;
  535. case 2:
  536. /* If the subtype is not changed due to :l operand qualifier,
  537. then no need to update the opcode value. */
  538. if ((int)opcode[1] != 0)
  539. {
  540. opcode[2] = opcode[0];
  541. opcode[0] = opcode[1];
  542. opcode[1] = 0x0;
  543. }
  544. reloc = BFD_RELOC_CR16_DISP24;
  545. break;
  546. default:
  547. abort();
  548. }
  549. fix_new (fragP, fragP->fr_fix,
  550. bfd_get_reloc_size (bfd_reloc_type_lookup (stdoutput, reloc)),
  551. fragP->fr_symbol, fragP->fr_offset, 1, reloc);
  552. fragP->fr_var = 0;
  553. fragP->fr_fix += md_relax_table[fragP->fr_subtype].rlx_length;
  554. }
  555. symbolS *
  556. md_undefined_symbol (char *name)
  557. {
  558. if (*name == '_' && *(name + 1) == 'G'
  559. && strcmp (name, "_GLOBAL_OFFSET_TABLE_") == 0)
  560. {
  561. if (!GOT_symbol)
  562. {
  563. if (symbol_find (name))
  564. as_bad (_("GOT already in symbol table"));
  565. GOT_symbol = symbol_new (name, undefined_section,
  566. &zero_address_frag, 0);
  567. }
  568. return GOT_symbol;
  569. }
  570. return 0;
  571. }
  572. /* Process machine-dependent command line options. Called once for
  573. each option on the command line that the machine-independent part of
  574. GAS does not understand. */
  575. int
  576. md_parse_option (int c ATTRIBUTE_UNUSED, const char *arg ATTRIBUTE_UNUSED)
  577. {
  578. return 0;
  579. }
  580. /* Machine-dependent usage-output. */
  581. void
  582. md_show_usage (FILE *stream ATTRIBUTE_UNUSED)
  583. {
  584. return;
  585. }
  586. const char *
  587. md_atof (int type, char *litP, int *sizeP)
  588. {
  589. return ieee_md_atof (type, litP, sizeP, target_big_endian);
  590. }
  591. /* Apply a fixS (fixup of an instruction or data that we didn't have
  592. enough info to complete immediately) to the data in a frag.
  593. Since linkrelax is nonzero and TC_LINKRELAX_FIXUP is defined to disable
  594. relaxation of debug sections, this function is called only when
  595. fixuping relocations of debug sections. */
  596. void
  597. md_apply_fix (fixS *fixP, valueT *valP, segT seg)
  598. {
  599. valueT val = * valP;
  600. if (fixP->fx_addsy == NULL
  601. && fixP->fx_pcrel == 0)
  602. fixP->fx_done = 1;
  603. else if (fixP->fx_pcrel == 1
  604. && fixP->fx_addsy != NULL
  605. && S_GET_SEGMENT (fixP->fx_addsy) == seg)
  606. fixP->fx_done = 1;
  607. else
  608. fixP->fx_done = 0;
  609. if (fixP->fx_addsy != NULL && !fixP->fx_pcrel)
  610. {
  611. val = fixP->fx_offset;
  612. fixP->fx_done = 1;
  613. }
  614. if (fixP->fx_done)
  615. {
  616. char *buf = fixP->fx_frag->fr_literal + fixP->fx_where;
  617. fixP->fx_offset = 0;
  618. switch (fixP->fx_r_type)
  619. {
  620. case BFD_RELOC_CR16_NUM8:
  621. bfd_put_8 (stdoutput, (unsigned char) val, buf);
  622. break;
  623. case BFD_RELOC_CR16_NUM16:
  624. bfd_put_16 (stdoutput, val, buf);
  625. break;
  626. case BFD_RELOC_CR16_NUM32:
  627. bfd_put_32 (stdoutput, val, buf);
  628. break;
  629. case BFD_RELOC_CR16_NUM32a:
  630. bfd_put_32 (stdoutput, val, buf);
  631. break;
  632. default:
  633. /* We shouldn't ever get here because linkrelax is nonzero. */
  634. abort ();
  635. break;
  636. }
  637. fixP->fx_done = 0;
  638. }
  639. else
  640. fixP->fx_offset = * valP;
  641. }
  642. /* The location from which a PC relative jump should be calculated,
  643. given a PC relative reloc. */
  644. long
  645. md_pcrel_from (fixS *fixp)
  646. {
  647. return fixp->fx_frag->fr_address + fixp->fx_where;
  648. }
  649. static void
  650. initialise_reg_hash_table (htab_t *hash_table,
  651. const reg_entry *register_table,
  652. const unsigned int num_entries)
  653. {
  654. const reg_entry *rreg;
  655. *hash_table = str_htab_create ();
  656. for (rreg = register_table;
  657. rreg < (register_table + num_entries);
  658. rreg++)
  659. if (str_hash_insert (*hash_table, rreg->name, rreg, 0) != NULL)
  660. as_fatal (_("duplicate %s"), rreg->name);
  661. }
  662. /* This function is called once, at assembler startup time. This should
  663. set up all the tables, etc that the MD part of the assembler needs. */
  664. void
  665. md_begin (void)
  666. {
  667. int i = 0;
  668. /* Set up a hash table for the instructions. */
  669. cr16_inst_hash = str_htab_create ();
  670. while (cr16_instruction[i].mnemonic != NULL)
  671. {
  672. const char *mnemonic = cr16_instruction[i].mnemonic;
  673. if (str_hash_insert (cr16_inst_hash, mnemonic, cr16_instruction + i, 0))
  674. as_fatal (_("duplicate %s"), mnemonic);
  675. /* Insert unique names into hash table. The CR16 instruction set
  676. has many identical opcode names that have different opcodes based
  677. on the operands. This hash table then provides a quick index to
  678. the first opcode with a particular name in the opcode table. */
  679. do
  680. {
  681. ++i;
  682. }
  683. while (cr16_instruction[i].mnemonic != NULL
  684. && streq (cr16_instruction[i].mnemonic, mnemonic));
  685. }
  686. /* Initialize reg_hash hash table. */
  687. initialise_reg_hash_table (& reg_hash, cr16_regtab, NUMREGS);
  688. /* Initialize regp_hash hash table. */
  689. initialise_reg_hash_table (& regp_hash, cr16_regptab, NUMREGPS);
  690. /* Initialize preg_hash hash table. */
  691. initialise_reg_hash_table (& preg_hash, cr16_pregtab, NUMPREGS);
  692. /* Initialize pregp_hash hash table. */
  693. initialise_reg_hash_table (& pregp_hash, cr16_pregptab, NUMPREGPS);
  694. /* Set linkrelax here to avoid fixups in most sections. */
  695. linkrelax = 1;
  696. }
  697. /* Process constants (immediate/absolute)
  698. and labels (jump targets/Memory locations). */
  699. static void
  700. process_label_constant (char *str, ins * cr16_ins)
  701. {
  702. char *saved_input_line_pointer;
  703. int symbol_with_at = 0;
  704. int symbol_with_s = 0;
  705. int symbol_with_m = 0;
  706. int symbol_with_l = 0;
  707. int symbol_with_at_got = 0;
  708. int symbol_with_at_gotc = 0;
  709. argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */
  710. saved_input_line_pointer = input_line_pointer;
  711. input_line_pointer = str;
  712. expression (&cr16_ins->exp);
  713. switch (cr16_ins->exp.X_op)
  714. {
  715. case O_big:
  716. case O_absent:
  717. /* Missing or bad expr becomes absolute 0. */
  718. as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
  719. str);
  720. cr16_ins->exp.X_op = O_constant;
  721. cr16_ins->exp.X_add_number = 0;
  722. cr16_ins->exp.X_add_symbol = NULL;
  723. cr16_ins->exp.X_op_symbol = NULL;
  724. /* Fall through. */
  725. case O_constant:
  726. cur_arg->X_op = O_constant;
  727. cur_arg->constant = cr16_ins->exp.X_add_number;
  728. break;
  729. case O_symbol:
  730. case O_subtract:
  731. case O_add:
  732. cur_arg->X_op = O_symbol;
  733. cur_arg->constant = cr16_ins->exp.X_add_number;
  734. cr16_ins->exp.X_add_number = 0;
  735. cr16_ins->rtype = BFD_RELOC_NONE;
  736. relocatable = 1;
  737. if (startswith (input_line_pointer, "@c"))
  738. symbol_with_at = 1;
  739. if (startswith (input_line_pointer, "@l")
  740. || startswith (input_line_pointer, ":l"))
  741. symbol_with_l = 1;
  742. if (startswith (input_line_pointer, "@m")
  743. || startswith (input_line_pointer, ":m"))
  744. symbol_with_m = 1;
  745. if (startswith (input_line_pointer, "@s")
  746. || startswith (input_line_pointer, ":s"))
  747. symbol_with_s = 1;
  748. if (startswith (input_line_pointer, "@cGOT")
  749. || startswith (input_line_pointer, "@cgot"))
  750. {
  751. if (GOT_symbol == NULL)
  752. GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
  753. symbol_with_at_gotc = 1;
  754. }
  755. else if (startswith (input_line_pointer, "@GOT")
  756. || startswith (input_line_pointer, "@got"))
  757. {
  758. if ((startswith (input_line_pointer, "+"))
  759. || (startswith (input_line_pointer, "-")))
  760. as_warn (_("GOT bad expression with %s."), input_line_pointer);
  761. if (GOT_symbol == NULL)
  762. GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
  763. symbol_with_at_got = 1;
  764. }
  765. switch (cur_arg->type)
  766. {
  767. case arg_cr:
  768. if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
  769. {
  770. if (symbol_with_at_got)
  771. cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20;
  772. else if (symbol_with_at_gotc)
  773. cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20;
  774. else if (cur_arg->size == 20)
  775. cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
  776. else
  777. cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
  778. }
  779. break;
  780. case arg_crp:
  781. if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
  782. {
  783. if (symbol_with_at_got)
  784. cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20;
  785. else if (symbol_with_at_gotc)
  786. cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20;
  787. } else {
  788. switch (instruction->size)
  789. {
  790. case 1:
  791. switch (cur_arg->size)
  792. {
  793. case 0:
  794. cr16_ins->rtype = BFD_RELOC_CR16_REGREL0;
  795. break;
  796. case 4:
  797. if (IS_INSN_MNEMONIC ("loadb") || IS_INSN_MNEMONIC ("storb"))
  798. cr16_ins->rtype = BFD_RELOC_CR16_REGREL4;
  799. else
  800. cr16_ins->rtype = BFD_RELOC_CR16_REGREL4a;
  801. break;
  802. default: break;
  803. }
  804. break;
  805. case 2:
  806. cr16_ins->rtype = BFD_RELOC_CR16_REGREL16;
  807. break;
  808. case 3:
  809. if (cur_arg->size == 20)
  810. cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
  811. else
  812. cr16_ins->rtype = BFD_RELOC_CR16_REGREL20a;
  813. break;
  814. default:
  815. break;
  816. }
  817. }
  818. break;
  819. case arg_idxr:
  820. if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
  821. {
  822. if (symbol_with_at_got)
  823. cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20;
  824. else if (symbol_with_at_gotc)
  825. cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20;
  826. else
  827. cr16_ins->rtype = BFD_RELOC_CR16_REGREL20;
  828. }
  829. break;
  830. case arg_idxrp:
  831. if (IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
  832. {
  833. if (symbol_with_at_got)
  834. cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20;
  835. else if (symbol_with_at_gotc)
  836. cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20;
  837. else {
  838. switch (instruction->size)
  839. {
  840. case 1: cr16_ins->rtype = BFD_RELOC_CR16_REGREL0; break;
  841. case 2: cr16_ins->rtype = BFD_RELOC_CR16_REGREL14; break;
  842. case 3: cr16_ins->rtype = BFD_RELOC_CR16_REGREL20; break;
  843. default: break;
  844. }
  845. }
  846. }
  847. break;
  848. case arg_c:
  849. if (IS_INSN_MNEMONIC ("bal"))
  850. cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
  851. else if (IS_INSN_TYPE (BRANCH_INS))
  852. {
  853. if (symbol_with_l)
  854. cr16_ins->rtype = BFD_RELOC_CR16_DISP24;
  855. else if (symbol_with_m)
  856. cr16_ins->rtype = BFD_RELOC_CR16_DISP16;
  857. else
  858. cr16_ins->rtype = BFD_RELOC_CR16_DISP8;
  859. }
  860. else if (IS_INSN_TYPE (STOR_IMM_INS) || IS_INSN_TYPE (LD_STOR_INS)
  861. || IS_INSN_TYPE (CSTBIT_INS))
  862. {
  863. if (symbol_with_s)
  864. as_bad (_("operand %d: illegal use expression: `%s`"), cur_arg_num + 1, str);
  865. if (symbol_with_at_got)
  866. cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20;
  867. else if (symbol_with_at_gotc)
  868. cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20;
  869. else if (symbol_with_m)
  870. cr16_ins->rtype = BFD_RELOC_CR16_ABS20;
  871. else /* Default to (symbol_with_l) */
  872. cr16_ins->rtype = BFD_RELOC_CR16_ABS24;
  873. }
  874. else if (IS_INSN_TYPE (BRANCH_NEQ_INS))
  875. cr16_ins->rtype = BFD_RELOC_CR16_DISP4;
  876. break;
  877. case arg_ic:
  878. if (IS_INSN_TYPE (ARITH_INS))
  879. {
  880. if (symbol_with_at_got)
  881. cr16_ins->rtype = BFD_RELOC_CR16_GOT_REGREL20;
  882. else if (symbol_with_at_gotc)
  883. cr16_ins->rtype = BFD_RELOC_CR16_GOTC_REGREL20;
  884. else if (symbol_with_s)
  885. cr16_ins->rtype = BFD_RELOC_CR16_IMM4;
  886. else if (symbol_with_m)
  887. cr16_ins->rtype = BFD_RELOC_CR16_IMM20;
  888. else if (symbol_with_at)
  889. cr16_ins->rtype = BFD_RELOC_CR16_IMM32a;
  890. else /* Default to (symbol_with_l) */
  891. cr16_ins->rtype = BFD_RELOC_CR16_IMM32;
  892. }
  893. else if (IS_INSN_TYPE (ARITH_BYTE_INS))
  894. {
  895. cr16_ins->rtype = BFD_RELOC_CR16_IMM16;
  896. }
  897. break;
  898. default:
  899. break;
  900. }
  901. break;
  902. default:
  903. cur_arg->X_op = cr16_ins->exp.X_op;
  904. break;
  905. }
  906. input_line_pointer = saved_input_line_pointer;
  907. return;
  908. }
  909. /* Retrieve the opcode image of a given register.
  910. If the register is illegal for the current instruction,
  911. issue an error. */
  912. static int
  913. getreg_image (reg r)
  914. {
  915. const reg_entry *rreg;
  916. char *reg_name;
  917. int is_procreg = 0; /* Nonzero means argument should be processor reg. */
  918. /* Check whether the register is in registers table. */
  919. if (r < MAX_REG)
  920. rreg = cr16_regtab + r;
  921. else /* Register not found. */
  922. {
  923. as_bad (_("Unknown register: `%d'"), r);
  924. return 0;
  925. }
  926. reg_name = rreg->name;
  927. /* Issue a error message when register is illegal. */
  928. #define IMAGE_ERR \
  929. as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
  930. reg_name, ins_parse);
  931. switch (rreg->type)
  932. {
  933. case CR16_R_REGTYPE:
  934. if (! is_procreg)
  935. return rreg->image;
  936. else
  937. IMAGE_ERR;
  938. break;
  939. case CR16_P_REGTYPE:
  940. return rreg->image;
  941. break;
  942. default:
  943. IMAGE_ERR;
  944. break;
  945. }
  946. return 0;
  947. }
  948. /* Parsing different types of operands
  949. -> constants Immediate/Absolute/Relative numbers
  950. -> Labels Relocatable symbols
  951. -> (reg pair base) Register pair base
  952. -> (rbase) Register base
  953. -> disp(rbase) Register relative
  954. -> [rinx]disp(reg pair) Register index with reg pair mode
  955. -> disp(rbase,ridx,scl) Register index mode. */
  956. static void
  957. set_operand (char *operand, ins * cr16_ins)
  958. {
  959. char *operandS; /* Pointer to start of sub-operand. */
  960. char *operandE; /* Pointer to end of sub-operand. */
  961. argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument. */
  962. /* Initialize pointers. */
  963. operandS = operandE = operand;
  964. switch (cur_arg->type)
  965. {
  966. case arg_ic: /* Case $0x18. */
  967. operandS++;
  968. /* Fall through. */
  969. case arg_c: /* Case 0x18. */
  970. /* Set constant. */
  971. process_label_constant (operandS, cr16_ins);
  972. if (cur_arg->type != arg_ic)
  973. cur_arg->type = arg_c;
  974. break;
  975. case arg_icr: /* Case $0x18(r1). */
  976. operandS++;
  977. case arg_cr: /* Case 0x18(r1). */
  978. /* Set displacement constant. */
  979. while (*operandE != '(')
  980. operandE++;
  981. *operandE = '\0';
  982. process_label_constant (operandS, cr16_ins);
  983. operandS = operandE;
  984. /* Fall through. */
  985. case arg_rbase: /* Case (r1) or (r1,r0). */
  986. operandS++;
  987. /* Set register base. */
  988. while (*operandE != ')')
  989. operandE++;
  990. *operandE = '\0';
  991. if ((cur_arg->r = get_register (operandS)) == nullregister)
  992. as_bad (_("Illegal register `%s' in Instruction `%s'"),
  993. operandS, ins_parse);
  994. /* set the arg->rp, if reg is "r12" or "r13" or "14" or "15" */
  995. if ((cur_arg->type != arg_rbase)
  996. && ((getreg_image (cur_arg->r) == 12)
  997. || (getreg_image (cur_arg->r) == 13)
  998. || (getreg_image (cur_arg->r) == 14)
  999. || (getreg_image (cur_arg->r) == 15)))
  1000. {
  1001. cur_arg->type = arg_crp;
  1002. cur_arg->rp = cur_arg->r;
  1003. }
  1004. break;
  1005. case arg_crp: /* Case 0x18(r1,r0). */
  1006. /* Set displacement constant. */
  1007. while (*operandE != '(')
  1008. operandE++;
  1009. *operandE = '\0';
  1010. process_label_constant (operandS, cr16_ins);
  1011. operandS = operandE;
  1012. operandS++;
  1013. /* Set register pair base. */
  1014. while (*operandE != ')')
  1015. operandE++;
  1016. *operandE = '\0';
  1017. if ((cur_arg->rp = get_register_pair (operandS)) == nullregister)
  1018. as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
  1019. operandS, ins_parse);
  1020. break;
  1021. case arg_idxr:
  1022. /* Set register pair base. */
  1023. if ((strchr (operandS,'(') != NULL))
  1024. {
  1025. while ((*operandE != '(') && (! ISSPACE (*operandE)))
  1026. operandE++;
  1027. if ((cur_arg->rp = get_index_register_pair (operandE)) == nullregister)
  1028. as_bad (_("Illegal register pair `%s' in Instruction `%s'"),
  1029. operandS, ins_parse);
  1030. *operandE++ = '\0';
  1031. cur_arg->type = arg_idxrp;
  1032. }
  1033. else
  1034. cur_arg->rp = -1;
  1035. operandE = operandS;
  1036. /* Set displacement constant. */
  1037. while (*operandE != ']')
  1038. operandE++;
  1039. process_label_constant (++operandE, cr16_ins);
  1040. *operandE++ = '\0';
  1041. operandE = operandS;
  1042. /* Set index register . */
  1043. operandS = strchr (operandE,'[');
  1044. if (operandS != NULL)
  1045. { /* Eliminate '[', detach from rest of operand. */
  1046. *operandS++ = '\0';
  1047. operandE = strchr (operandS, ']');
  1048. if (operandE == NULL)
  1049. as_bad (_("unmatched '['"));
  1050. else
  1051. { /* Eliminate ']' and make sure it was the last thing
  1052. in the string. */
  1053. *operandE = '\0';
  1054. if (*(operandE + 1) != '\0')
  1055. as_bad (_("garbage after index spec ignored"));
  1056. }
  1057. }
  1058. if ((cur_arg->i_r = get_index_register (operandS)) == nullregister)
  1059. as_bad (_("Illegal register `%s' in Instruction `%s'"),
  1060. operandS, ins_parse);
  1061. *operandE = '\0';
  1062. *operandS = '\0';
  1063. break;
  1064. default:
  1065. break;
  1066. }
  1067. }
  1068. /* Parse a single operand.
  1069. operand - Current operand to parse.
  1070. cr16_ins - Current assembled instruction. */
  1071. static void
  1072. parse_operand (char *operand, ins * cr16_ins)
  1073. {
  1074. int ret_val;
  1075. argument *cur_arg = cr16_ins->arg + cur_arg_num; /* Current argument. */
  1076. /* Initialize the type to NULL before parsing. */
  1077. cur_arg->type = nullargs;
  1078. /* Check whether this is a condition code . */
  1079. if ((IS_INSN_MNEMONIC ("b")) && ((ret_val = get_cc (operand)) != -1))
  1080. {
  1081. cur_arg->type = arg_cc;
  1082. cur_arg->cc = ret_val;
  1083. cur_arg->X_op = O_register;
  1084. return;
  1085. }
  1086. /* Check whether this is a general processor register. */
  1087. if ((ret_val = get_register (operand)) != nullregister)
  1088. {
  1089. cur_arg->type = arg_r;
  1090. cur_arg->r = ret_val;
  1091. cur_arg->X_op = 0;
  1092. return;
  1093. }
  1094. /* Check whether this is a general processor register pair. */
  1095. if ((operand[0] == '(')
  1096. && ((ret_val = get_register_pair (operand)) != nullregister))
  1097. {
  1098. cur_arg->type = arg_rp;
  1099. cur_arg->rp = ret_val;
  1100. cur_arg->X_op = O_register;
  1101. return;
  1102. }
  1103. /* Check whether the operand is a processor register.
  1104. For "lprd" and "sprd" instruction, only 32 bit
  1105. processor registers used. */
  1106. if (!(IS_INSN_MNEMONIC ("lprd") || (IS_INSN_MNEMONIC ("sprd")))
  1107. && ((ret_val = get_pregister (operand)) != nullpregister))
  1108. {
  1109. cur_arg->type = arg_pr;
  1110. cur_arg->pr = ret_val;
  1111. cur_arg->X_op = O_register;
  1112. return;
  1113. }
  1114. /* Check whether this is a processor register - 32 bit. */
  1115. if ((ret_val = get_pregisterp (operand)) != nullpregister)
  1116. {
  1117. cur_arg->type = arg_prp;
  1118. cur_arg->prp = ret_val;
  1119. cur_arg->X_op = O_register;
  1120. return;
  1121. }
  1122. /* Deal with special characters. */
  1123. switch (operand[0])
  1124. {
  1125. case '$':
  1126. if (strchr (operand, '(') != NULL)
  1127. cur_arg->type = arg_icr;
  1128. else
  1129. cur_arg->type = arg_ic;
  1130. goto set_params;
  1131. break;
  1132. case '(':
  1133. cur_arg->type = arg_rbase;
  1134. goto set_params;
  1135. break;
  1136. case '[':
  1137. cur_arg->type = arg_idxr;
  1138. goto set_params;
  1139. break;
  1140. default:
  1141. break;
  1142. }
  1143. if (strchr (operand, '(') != NULL)
  1144. {
  1145. if (strchr (operand, ',') != NULL
  1146. && (strchr (operand, ',') > strchr (operand, '(')))
  1147. cur_arg->type = arg_crp;
  1148. else
  1149. cur_arg->type = arg_cr;
  1150. }
  1151. else
  1152. cur_arg->type = arg_c;
  1153. /* Parse an operand according to its type. */
  1154. set_params:
  1155. cur_arg->constant = 0;
  1156. set_operand (operand, cr16_ins);
  1157. }
  1158. /* Parse the various operands. Each operand is then analyzed to fillup
  1159. the fields in the cr16_ins data structure. */
  1160. static void
  1161. parse_operands (ins * cr16_ins, char *operands)
  1162. {
  1163. char *operandS; /* Operands string. */
  1164. char *operandH, *operandT; /* Single operand head/tail pointers. */
  1165. int allocated = 0; /* Indicates a new operands string was allocated.*/
  1166. char *operand[MAX_OPERANDS];/* Separating the operands. */
  1167. int op_num = 0; /* Current operand number we are parsing. */
  1168. int bracket_flag = 0; /* Indicates a bracket '(' was found. */
  1169. int sq_bracket_flag = 0; /* Indicates a square bracket '[' was found. */
  1170. /* Preprocess the list of registers, if necessary. */
  1171. operandS = operandH = operandT = operands;
  1172. while (*operandT != '\0')
  1173. {
  1174. if (*operandT == ',' && bracket_flag != 1 && sq_bracket_flag != 1)
  1175. {
  1176. *operandT++ = '\0';
  1177. operand[op_num++] = strdup (operandH);
  1178. operandH = operandT;
  1179. continue;
  1180. }
  1181. if (*operandT == ' ')
  1182. as_bad (_("Illegal operands (whitespace): `%s'"), ins_parse);
  1183. if (*operandT == '(')
  1184. bracket_flag = 1;
  1185. else if (*operandT == '[')
  1186. sq_bracket_flag = 1;
  1187. if (*operandT == ')')
  1188. {
  1189. if (bracket_flag)
  1190. bracket_flag = 0;
  1191. else
  1192. as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
  1193. }
  1194. else if (*operandT == ']')
  1195. {
  1196. if (sq_bracket_flag)
  1197. sq_bracket_flag = 0;
  1198. else
  1199. as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
  1200. }
  1201. if (bracket_flag == 1 && *operandT == ')')
  1202. bracket_flag = 0;
  1203. else if (sq_bracket_flag == 1 && *operandT == ']')
  1204. sq_bracket_flag = 0;
  1205. operandT++;
  1206. }
  1207. /* Adding the last operand. */
  1208. operand[op_num++] = strdup (operandH);
  1209. cr16_ins->nargs = op_num;
  1210. /* Verifying correct syntax of operands (all brackets should be closed). */
  1211. if (bracket_flag || sq_bracket_flag)
  1212. as_fatal (_("Missing matching brackets : `%s'"), ins_parse);
  1213. /* Now we parse each operand separately. */
  1214. for (op_num = 0; op_num < cr16_ins->nargs; op_num++)
  1215. {
  1216. cur_arg_num = op_num;
  1217. parse_operand (operand[op_num], cr16_ins);
  1218. free (operand[op_num]);
  1219. }
  1220. if (allocated)
  1221. free (operandS);
  1222. }
  1223. /* Get the trap index in dispatch table, given its name.
  1224. This routine is used by assembling the 'excp' instruction. */
  1225. static int
  1226. gettrap (char *s)
  1227. {
  1228. const trap_entry *trap;
  1229. for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
  1230. if (strcasecmp (trap->name, s) == 0)
  1231. return trap->entry;
  1232. /* To make compatible with CR16 4.1 tools, the below 3-lines of
  1233. * code added. Refer: Development Tracker item #123 */
  1234. for (trap = cr16_traps; trap < (cr16_traps + NUMTRAPS); trap++)
  1235. if (trap->entry == (unsigned int) atoi (s))
  1236. return trap->entry;
  1237. as_bad (_("Unknown exception: `%s'"), s);
  1238. return 0;
  1239. }
  1240. /* Top level module where instruction parsing starts.
  1241. cr16_ins - data structure holds some information.
  1242. operands - holds the operands part of the whole instruction. */
  1243. static void
  1244. parse_insn (ins *insn, char *operands)
  1245. {
  1246. int i;
  1247. /* Handle instructions with no operands. */
  1248. for (i = 0; cr16_no_op_insn[i] != NULL; i++)
  1249. {
  1250. if (streq (cr16_no_op_insn[i], instruction->mnemonic))
  1251. {
  1252. insn->nargs = 0;
  1253. return;
  1254. }
  1255. }
  1256. /* Handle 'excp' instructions. */
  1257. if (IS_INSN_MNEMONIC ("excp"))
  1258. {
  1259. insn->nargs = 1;
  1260. insn->arg[0].type = arg_ic;
  1261. insn->arg[0].constant = gettrap (operands);
  1262. insn->arg[0].X_op = O_constant;
  1263. return;
  1264. }
  1265. if (operands != NULL)
  1266. parse_operands (insn, operands);
  1267. }
  1268. /* bCC instruction requires special handling. */
  1269. static char *
  1270. get_b_cc (char * op)
  1271. {
  1272. unsigned int i;
  1273. if (op[1] == 0 || (op[2] != 0 && op[3] != 0))
  1274. return NULL;
  1275. for (i = 0; i < cr16_num_cc ; i++)
  1276. if (streq (op + 1, cr16_b_cond_tab[i]))
  1277. return (char *) cr16_b_cond_tab[i];
  1278. return NULL;
  1279. }
  1280. /* bCC instruction requires special handling. */
  1281. static int
  1282. is_bcc_insn (char * op)
  1283. {
  1284. if (!(streq (op, "bal") || streq (op, "beq0b") || streq (op, "bnq0b")
  1285. || streq (op, "beq0w") || streq (op, "bnq0w")))
  1286. if ((op[0] == 'b') && (get_b_cc (op) != NULL))
  1287. return 1;
  1288. return 0;
  1289. }
  1290. /* Cinv instruction requires special handling. */
  1291. static void
  1292. check_cinv_options (char * operand)
  1293. {
  1294. char *p = operand;
  1295. while (*++p != ']')
  1296. {
  1297. switch (*p)
  1298. {
  1299. case ',':
  1300. case ' ':
  1301. case 'i':
  1302. case 'u':
  1303. case 'd':
  1304. break;
  1305. default:
  1306. as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
  1307. }
  1308. }
  1309. }
  1310. /* Retrieve the opcode image of a given register pair.
  1311. If the register is illegal for the current instruction,
  1312. issue an error. */
  1313. static int
  1314. getregp_image (reg r)
  1315. {
  1316. const reg_entry *rreg;
  1317. char *reg_name;
  1318. /* Check whether the register is in registers table. */
  1319. if (r < MAX_REG)
  1320. rreg = cr16_regptab + r;
  1321. /* Register not found. */
  1322. else
  1323. {
  1324. as_bad (_("Unknown register pair: `%d'"), r);
  1325. return 0;
  1326. }
  1327. reg_name = rreg->name;
  1328. /* Issue a error message when register pair is illegal. */
  1329. #define RPAIR_IMAGE_ERR \
  1330. as_bad (_("Illegal register pair (`%s') in Instruction: `%s'"), \
  1331. reg_name, ins_parse); \
  1332. break;
  1333. switch (rreg->type)
  1334. {
  1335. case CR16_RP_REGTYPE:
  1336. return rreg->image;
  1337. default:
  1338. RPAIR_IMAGE_ERR;
  1339. }
  1340. return 0;
  1341. }
  1342. /* Retrieve the opcode image of a given index register pair.
  1343. If the register is illegal for the current instruction,
  1344. issue an error. */
  1345. static int
  1346. getidxregp_image (reg r)
  1347. {
  1348. const reg_entry *rreg;
  1349. char *reg_name;
  1350. /* Check whether the register is in registers table. */
  1351. if (r < MAX_REG)
  1352. rreg = cr16_regptab + r;
  1353. /* Register not found. */
  1354. else
  1355. {
  1356. as_bad (_("Unknown register pair: `%d'"), r);
  1357. return 0;
  1358. }
  1359. reg_name = rreg->name;
  1360. /* Issue a error message when register pair is illegal. */
  1361. #define IDX_RPAIR_IMAGE_ERR \
  1362. as_bad (_("Illegal index register pair (`%s') in Instruction: `%s'"), \
  1363. reg_name, ins_parse); \
  1364. if (rreg->type == CR16_RP_REGTYPE)
  1365. {
  1366. switch (rreg->image)
  1367. {
  1368. case 0: return 0; break;
  1369. case 2: return 1; break;
  1370. case 4: return 2; break;
  1371. case 6: return 3; break;
  1372. case 8: return 4; break;
  1373. case 10: return 5; break;
  1374. case 3: return 6; break;
  1375. case 5: return 7; break;
  1376. default:
  1377. break;
  1378. }
  1379. }
  1380. IDX_RPAIR_IMAGE_ERR;
  1381. return 0;
  1382. }
  1383. /* Retrieve the opcode image of a given processor register.
  1384. If the register is illegal for the current instruction,
  1385. issue an error. */
  1386. static int
  1387. getprocreg_image (int r)
  1388. {
  1389. const reg_entry *rreg;
  1390. char *reg_name;
  1391. /* Check whether the register is in registers table. */
  1392. if (r >= MAX_REG && r < MAX_PREG)
  1393. rreg = &cr16_pregtab[r - MAX_REG];
  1394. /* Register not found. */
  1395. else
  1396. {
  1397. as_bad (_("Unknown processor register : `%d'"), r);
  1398. return 0;
  1399. }
  1400. reg_name = rreg->name;
  1401. /* Issue a error message when register pair is illegal. */
  1402. #define PROCREG_IMAGE_ERR \
  1403. as_bad (_("Illegal processor register (`%s') in Instruction: `%s'"), \
  1404. reg_name, ins_parse); \
  1405. break;
  1406. switch (rreg->type)
  1407. {
  1408. case CR16_P_REGTYPE:
  1409. return rreg->image;
  1410. default:
  1411. PROCREG_IMAGE_ERR;
  1412. }
  1413. return 0;
  1414. }
  1415. /* Retrieve the opcode image of a given processor register.
  1416. If the register is illegal for the current instruction,
  1417. issue an error. */
  1418. static int
  1419. getprocregp_image (int r)
  1420. {
  1421. const reg_entry *rreg;
  1422. char *reg_name;
  1423. int pregptab_disp = 0;
  1424. /* Check whether the register is in registers table. */
  1425. if (r >= MAX_REG && r < MAX_PREG)
  1426. {
  1427. r = r - MAX_REG;
  1428. switch (r)
  1429. {
  1430. case 4: pregptab_disp = 1; break;
  1431. case 6: pregptab_disp = 2; break;
  1432. case 8:
  1433. case 9:
  1434. case 10:
  1435. pregptab_disp = 3; break;
  1436. case 12:
  1437. pregptab_disp = 4; break;
  1438. case 14:
  1439. pregptab_disp = 5; break;
  1440. default: break;
  1441. }
  1442. rreg = &cr16_pregptab[r - pregptab_disp];
  1443. }
  1444. /* Register not found. */
  1445. else
  1446. {
  1447. as_bad (_("Unknown processor register (32 bit) : `%d'"), r);
  1448. return 0;
  1449. }
  1450. reg_name = rreg->name;
  1451. /* Issue a error message when register pair is illegal. */
  1452. #define PROCREGP_IMAGE_ERR \
  1453. as_bad (_("Illegal 32 bit - processor register (`%s') in Instruction: `%s'"), \
  1454. reg_name, ins_parse); \
  1455. break;
  1456. switch (rreg->type)
  1457. {
  1458. case CR16_P_REGTYPE:
  1459. return rreg->image;
  1460. default:
  1461. PROCREGP_IMAGE_ERR;
  1462. }
  1463. return 0;
  1464. }
  1465. /* Routine used to represent integer X using NBITS bits. */
  1466. static long
  1467. getconstant (long x, int nbits)
  1468. {
  1469. if ((unsigned) nbits >= sizeof (x) * CHAR_BIT)
  1470. return x;
  1471. return x & ((1UL << nbits) - 1);
  1472. }
  1473. /* Print a constant value to 'output_opcode':
  1474. ARG holds the operand's type and value.
  1475. SHIFT represents the location of the operand to be print into.
  1476. NBITS determines the size (in bits) of the constant. */
  1477. static void
  1478. print_constant (int nbits, int shift, argument *arg)
  1479. {
  1480. unsigned long mask = 0;
  1481. unsigned long constant = getconstant (arg->constant, nbits);
  1482. switch (nbits)
  1483. {
  1484. case 32:
  1485. case 28:
  1486. /* mask the upper part of the constant, that is, the bits
  1487. going to the lowest byte of output_opcode[0].
  1488. The upper part of output_opcode[1] is always filled,
  1489. therefore it is always masked with 0xFFFF. */
  1490. mask = (1 << (nbits - 16)) - 1;
  1491. /* Divide the constant between two consecutive words :
  1492. 0 1 2 3
  1493. +---------+---------+---------+---------+
  1494. | | X X X X | x X x X | |
  1495. +---------+---------+---------+---------+
  1496. output_opcode[0] output_opcode[1] */
  1497. CR16_PRINT (0, (constant >> WORD_SHIFT) & mask, 0);
  1498. CR16_PRINT (1, constant & 0xFFFF, WORD_SHIFT);
  1499. break;
  1500. case 21:
  1501. if ((nbits == 21) && (IS_INSN_TYPE (LD_STOR_INS)))
  1502. nbits = 20;
  1503. /* Fall through. */
  1504. case 24:
  1505. case 22:
  1506. case 20:
  1507. /* mask the upper part of the constant, that is, the bits
  1508. going to the lowest byte of output_opcode[0].
  1509. The upper part of output_opcode[1] is always filled,
  1510. therefore it is always masked with 0xFFFF. */
  1511. mask = (1 << (nbits - 16)) - 1;
  1512. /* Divide the constant between two consecutive words :
  1513. 0 1 2 3
  1514. +---------+---------+---------+---------+
  1515. | | X X X X | - X - X | |
  1516. +---------+---------+---------+---------+
  1517. output_opcode[0] output_opcode[1] */
  1518. if (instruction->size > 2 && shift == WORD_SHIFT)
  1519. {
  1520. if (arg->type == arg_idxrp)
  1521. {
  1522. CR16_PRINT (0, ((constant >> WORD_SHIFT) & mask) << 8, 0);
  1523. CR16_PRINT (1, constant & 0xFFFF, WORD_SHIFT);
  1524. }
  1525. else
  1526. {
  1527. CR16_PRINT (0,
  1528. ((((constant >> WORD_SHIFT) & mask & 0xf) << 8)
  1529. | (((constant >> WORD_SHIFT) & mask & 0xf0) >> 4)),
  1530. 0);
  1531. CR16_PRINT (1, constant & 0xFFFF, WORD_SHIFT);
  1532. }
  1533. }
  1534. else
  1535. CR16_PRINT (0, constant, shift);
  1536. break;
  1537. case 14:
  1538. if (arg->type == arg_idxrp)
  1539. {
  1540. if (instruction->size == 2)
  1541. {
  1542. CR16_PRINT (0, (constant) & 0xf, shift); /* 0-3 bits. */
  1543. CR16_PRINT (0, (constant >> 4) & 0x3, shift + 20); /* 4-5 bits. */
  1544. CR16_PRINT (0, (constant >> 6) & 0x3, shift + 14); /* 6-7 bits. */
  1545. CR16_PRINT (0, (constant >> 8) & 0x3f, shift + 8); /* 8-13 bits. */
  1546. }
  1547. else
  1548. CR16_PRINT (0, constant, shift);
  1549. }
  1550. break;
  1551. case 16:
  1552. case 12:
  1553. /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
  1554. always filling the upper part of output_opcode[1]. If we mistakenly
  1555. write it to output_opcode[0], the constant prefix (that is, 'match')
  1556. will be overridden.
  1557. 0 1 2 3
  1558. +---------+---------+---------+---------+
  1559. | 'match' | | X X X X | |
  1560. +---------+---------+---------+---------+
  1561. output_opcode[0] output_opcode[1] */
  1562. if (instruction->size > 2 && shift == WORD_SHIFT)
  1563. CR16_PRINT (1, constant, WORD_SHIFT);
  1564. else
  1565. CR16_PRINT (0, constant, shift);
  1566. break;
  1567. case 8:
  1568. CR16_PRINT (0, (constant / 2) & 0xf, shift);
  1569. CR16_PRINT (0, (constant / 2) >> 4, shift + 8);
  1570. break;
  1571. default:
  1572. CR16_PRINT (0, constant, shift);
  1573. break;
  1574. }
  1575. }
  1576. /* Print an operand to 'output_opcode', which later on will be
  1577. printed to the object file:
  1578. ARG holds the operand's type, size and value.
  1579. SHIFT represents the printing location of operand.
  1580. NBITS determines the size (in bits) of a constant operand. */
  1581. static void
  1582. print_operand (int nbits, int shift, argument *arg)
  1583. {
  1584. switch (arg->type)
  1585. {
  1586. case arg_cc:
  1587. CR16_PRINT (0, arg->cc, shift);
  1588. break;
  1589. case arg_r:
  1590. CR16_PRINT (0, getreg_image (arg->r), shift);
  1591. break;
  1592. case arg_rp:
  1593. CR16_PRINT (0, getregp_image (arg->rp), shift);
  1594. break;
  1595. case arg_pr:
  1596. CR16_PRINT (0, getprocreg_image (arg->pr), shift);
  1597. break;
  1598. case arg_prp:
  1599. CR16_PRINT (0, getprocregp_image (arg->prp), shift);
  1600. break;
  1601. case arg_idxrp:
  1602. /* 16 12 8 6 0
  1603. +-----------------------------+
  1604. | r_index | disp | rp_base |
  1605. +-----------------------------+ */
  1606. if (instruction->size == 3)
  1607. {
  1608. CR16_PRINT (0, getidxregp_image (arg->rp), 0);
  1609. CR16_PRINT (0, getreg_image (arg->i_r) & 1, 3);
  1610. }
  1611. else
  1612. {
  1613. CR16_PRINT (0, getidxregp_image (arg->rp), 16);
  1614. CR16_PRINT (0, getreg_image (arg->i_r) & 1, 19);
  1615. }
  1616. print_constant (nbits, shift, arg);
  1617. break;
  1618. case arg_idxr:
  1619. CR16_PRINT (0, getreg_image (arg->i_r) & 1,
  1620. (IS_INSN_TYPE (CSTBIT_INS)
  1621. && instruction->mnemonic[4] == 'b') ? 23 : 24);
  1622. print_constant (nbits, shift, arg);
  1623. break;
  1624. case arg_ic:
  1625. case arg_c:
  1626. print_constant (nbits, shift, arg);
  1627. break;
  1628. case arg_rbase:
  1629. CR16_PRINT (0, getreg_image (arg->r), shift);
  1630. break;
  1631. case arg_cr:
  1632. print_constant (nbits, shift, arg);
  1633. /* Add the register argument to the output_opcode. */
  1634. CR16_PRINT (0, getreg_image (arg->r), shift - 16);
  1635. break;
  1636. case arg_crp:
  1637. print_constant (nbits, shift, arg);
  1638. if ((IS_INSN_TYPE (LD_STOR_INS) || IS_INSN_TYPE (CSTBIT_INS))
  1639. && instruction->size == 1)
  1640. CR16_PRINT (0, getregp_image (arg->rp), 16);
  1641. else if (instruction->size > 1)
  1642. CR16_PRINT (0, getregp_image (arg->rp), (shift + 16) & 31);
  1643. else
  1644. CR16_PRINT (0, getregp_image (arg->rp), shift);
  1645. break;
  1646. default:
  1647. break;
  1648. }
  1649. }
  1650. /* Retrieve the number of operands for the current assembled instruction. */
  1651. static int
  1652. get_number_of_operands (void)
  1653. {
  1654. int i;
  1655. for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++)
  1656. ;
  1657. return i;
  1658. }
  1659. /* Verify that the number NUM can be represented in BITS bits (that is,
  1660. within its permitted range), based on the instruction's FLAGS.
  1661. If UPDATE is nonzero, update the value of NUM if necessary.
  1662. Return OP_LEGAL upon success, actual error type upon failure. */
  1663. static op_err
  1664. check_range (long *num, int bits, int unsigned flags, int update)
  1665. {
  1666. int32_t min, max;
  1667. op_err retval = OP_LEGAL;
  1668. int32_t value = *num;
  1669. /* Verify operand value is even. */
  1670. if (flags & OP_EVEN)
  1671. {
  1672. if (value % 2)
  1673. return OP_NOT_EVEN;
  1674. }
  1675. if (flags & OP_DEC)
  1676. {
  1677. value -= 1;
  1678. if (update)
  1679. *num = value;
  1680. }
  1681. if (flags & OP_SHIFT)
  1682. {
  1683. value >>= 1;
  1684. if (update)
  1685. *num = value;
  1686. }
  1687. else if (flags & OP_SHIFT_DEC)
  1688. {
  1689. value = (value >> 1) - 1;
  1690. if (update)
  1691. *num = value;
  1692. }
  1693. if (flags & OP_ABS20)
  1694. {
  1695. if (value > 0xEFFFF)
  1696. return OP_OUT_OF_RANGE;
  1697. }
  1698. if (flags & OP_ESC)
  1699. {
  1700. if (value == 0xB || value == 0x9)
  1701. return OP_OUT_OF_RANGE;
  1702. else if (value == -1)
  1703. {
  1704. if (update)
  1705. *num = 9;
  1706. return retval;
  1707. }
  1708. }
  1709. if (flags & OP_ESC1)
  1710. {
  1711. if (value > 13)
  1712. return OP_OUT_OF_RANGE;
  1713. }
  1714. if (bits == 0)
  1715. {
  1716. if (value != 0)
  1717. retval = OP_OUT_OF_RANGE;
  1718. return retval;
  1719. }
  1720. if (flags & OP_SIGNED)
  1721. {
  1722. max = (1U << (bits - 1)) - 1;
  1723. min = - (1U << (bits - 1));
  1724. if (value > max || value < min)
  1725. retval = OP_OUT_OF_RANGE;
  1726. }
  1727. else if (flags & OP_UNSIGNED)
  1728. {
  1729. max = (1U << (bits - 1) << 1) - 1;
  1730. if ((uint32_t) value > (uint32_t) max)
  1731. retval = OP_OUT_OF_RANGE;
  1732. }
  1733. else if (flags & OP_NEG)
  1734. {
  1735. min = - ((1U << (bits - 1)) - 1);
  1736. if (value < min)
  1737. retval = OP_OUT_OF_RANGE;
  1738. }
  1739. return retval;
  1740. }
  1741. /* Bunch of error checking.
  1742. The checks are made after a matching instruction was found. */
  1743. static void
  1744. warn_if_needed (ins *insn)
  1745. {
  1746. /* If the post-increment address mode is used and the load/store
  1747. source register is the same as rbase, the result of the
  1748. instruction is undefined. */
  1749. if (IS_INSN_TYPE (LD_STOR_INS_INC))
  1750. {
  1751. /* Enough to verify that one of the arguments is a simple reg. */
  1752. if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
  1753. if (insn->arg[0].r == insn->arg[1].r)
  1754. as_bad (_("Same src/dest register is used (`r%d'), "
  1755. "result is undefined"), insn->arg[0].r);
  1756. }
  1757. if (IS_INSN_MNEMONIC ("pop")
  1758. || IS_INSN_MNEMONIC ("push")
  1759. || IS_INSN_MNEMONIC ("popret"))
  1760. {
  1761. unsigned int count = insn->arg[0].constant, reg_val;
  1762. /* Check if count operand caused to save/retrieve the RA twice
  1763. to generate warning message. */
  1764. if (insn->nargs > 2)
  1765. {
  1766. reg_val = getreg_image (insn->arg[1].r);
  1767. if ( ((reg_val == 9) && (count > 7))
  1768. || ((reg_val == 10) && (count > 6))
  1769. || ((reg_val == 11) && (count > 5))
  1770. || ((reg_val == 12) && (count > 4))
  1771. || ((reg_val == 13) && (count > 2))
  1772. || ((reg_val == 14) && (count > 0)))
  1773. as_warn (_("RA register is saved twice."));
  1774. /* Check if the third operand is "RA" or "ra" */
  1775. if (!(((insn->arg[2].r) == ra) || ((insn->arg[2].r) == RA)))
  1776. as_bad (_("`%s' Illegal use of registers."), ins_parse);
  1777. }
  1778. if (insn->nargs > 1)
  1779. {
  1780. reg_val = getreg_image (insn->arg[1].r);
  1781. /* If register is a register pair ie r12/r13/r14 in operand1, then
  1782. the count constant should be validated. */
  1783. if (((reg_val == 11) && (count > 7))
  1784. || ((reg_val == 12) && (count > 6))
  1785. || ((reg_val == 13) && (count > 4))
  1786. || ((reg_val == 14) && (count > 2))
  1787. || ((reg_val == 15) && (count > 0)))
  1788. as_bad (_("`%s' Illegal count-register combination."), ins_parse);
  1789. }
  1790. else
  1791. {
  1792. /* Check if the operand is "RA" or "ra" */
  1793. if (!(((insn->arg[0].r) == ra) || ((insn->arg[0].r) == RA)))
  1794. as_bad (_("`%s' Illegal use of register."), ins_parse);
  1795. }
  1796. }
  1797. /* Some instruction assume the stack pointer as rptr operand.
  1798. Issue an error when the register to be loaded is also SP. */
  1799. if (instruction->flags & NO_SP)
  1800. {
  1801. if (getreg_image (insn->arg[1].r) == getreg_image (sp))
  1802. as_bad (_("`%s' has undefined result"), ins_parse);
  1803. }
  1804. /* If the rptr register is specified as one of the registers to be loaded,
  1805. the final contents of rptr are undefined. Thus, we issue an error. */
  1806. if (instruction->flags & NO_RPTR)
  1807. {
  1808. if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
  1809. as_bad (_("Same src/dest register is used (`r%d'),result is undefined"),
  1810. getreg_image (insn->arg[0].r));
  1811. }
  1812. }
  1813. /* In some cases, we need to adjust the instruction pointer although a
  1814. match was already found. Here, we gather all these cases.
  1815. Returns 1 if instruction pointer was adjusted, otherwise 0. */
  1816. static int
  1817. adjust_if_needed (ins *insn ATTRIBUTE_UNUSED)
  1818. {
  1819. int ret_value = 0;
  1820. if ((IS_INSN_TYPE (CSTBIT_INS)) || (IS_INSN_TYPE (LD_STOR_INS)))
  1821. {
  1822. if ((instruction->operands[0].op_type == abs24)
  1823. && ((insn->arg[0].constant) > 0xF00000))
  1824. {
  1825. insn->arg[0].constant &= 0xFFFFF;
  1826. instruction--;
  1827. ret_value = 1;
  1828. }
  1829. }
  1830. return ret_value;
  1831. }
  1832. /* Assemble a single instruction:
  1833. INSN is already parsed (that is, all operand values and types are set).
  1834. For instruction to be assembled, we need to find an appropriate template in
  1835. the instruction table, meeting the following conditions:
  1836. 1: Has the same number of operands.
  1837. 2: Has the same operand types.
  1838. 3: Each operand size is sufficient to represent the instruction's values.
  1839. Returns 1 upon success, 0 upon failure. */
  1840. static int
  1841. assemble_insn (const char *mnemonic, ins *insn)
  1842. {
  1843. /* Type of each operand in the current template. */
  1844. argtype cur_type[MAX_OPERANDS];
  1845. /* Size (in bits) of each operand in the current template. */
  1846. unsigned int cur_size[MAX_OPERANDS];
  1847. /* Flags of each operand in the current template. */
  1848. unsigned int cur_flags[MAX_OPERANDS];
  1849. /* Instruction type to match. */
  1850. unsigned int ins_type;
  1851. /* Boolean flag to mark whether a match was found. */
  1852. int match = 0;
  1853. int i;
  1854. /* Nonzero if an instruction with same number of operands was found. */
  1855. int found_same_number_of_operands = 0;
  1856. /* Nonzero if an instruction with same argument types was found. */
  1857. int found_same_argument_types = 0;
  1858. /* Nonzero if a constant was found within the required range. */
  1859. int found_const_within_range = 0;
  1860. /* Argument number of an operand with invalid type. */
  1861. int invalid_optype = -1;
  1862. /* Argument number of an operand with invalid constant value. */
  1863. int invalid_const = -1;
  1864. /* Operand error (used for issuing various constant error messages). */
  1865. op_err op_error, const_err = OP_LEGAL;
  1866. /* Retrieve data (based on FUNC) for each operand of a given instruction. */
  1867. #define GET_CURRENT_DATA(FUNC, ARRAY) \
  1868. for (i = 0; i < insn->nargs; i++) \
  1869. ARRAY[i] = FUNC (instruction->operands[i].op_type)
  1870. #define GET_CURRENT_TYPE GET_CURRENT_DATA (get_optype, cur_type)
  1871. #define GET_CURRENT_SIZE GET_CURRENT_DATA (get_opbits, cur_size)
  1872. #define GET_CURRENT_FLAGS GET_CURRENT_DATA (get_opflags, cur_flags)
  1873. /* Instruction has no operands -> only copy the constant opcode. */
  1874. if (insn->nargs == 0)
  1875. {
  1876. output_opcode[0] = BIN (instruction->match, instruction->match_bits);
  1877. return 1;
  1878. }
  1879. /* In some case, same mnemonic can appear with different instruction types.
  1880. For example, 'storb' is supported with 3 different types :
  1881. LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
  1882. We assume that when reaching this point, the instruction type was
  1883. pre-determined. We need to make sure that the type stays the same
  1884. during a search for matching instruction. */
  1885. ins_type = CR16_INS_TYPE (instruction->flags);
  1886. while (/* Check that match is still not found. */
  1887. match != 1
  1888. /* Check we didn't get to end of table. */
  1889. && instruction->mnemonic != NULL
  1890. /* Check that the actual mnemonic is still available. */
  1891. && IS_INSN_MNEMONIC (mnemonic)
  1892. /* Check that the instruction type wasn't changed. */
  1893. && IS_INSN_TYPE (ins_type))
  1894. {
  1895. /* Check whether number of arguments is legal. */
  1896. if (get_number_of_operands () != insn->nargs)
  1897. goto next_insn;
  1898. found_same_number_of_operands = 1;
  1899. /* Initialize arrays with data of each operand in current template. */
  1900. GET_CURRENT_TYPE;
  1901. GET_CURRENT_SIZE;
  1902. GET_CURRENT_FLAGS;
  1903. /* Check for type compatibility. */
  1904. for (i = 0; i < insn->nargs; i++)
  1905. {
  1906. if (cur_type[i] != insn->arg[i].type)
  1907. {
  1908. if (invalid_optype == -1)
  1909. invalid_optype = i + 1;
  1910. goto next_insn;
  1911. }
  1912. }
  1913. found_same_argument_types = 1;
  1914. for (i = 0; i < insn->nargs; i++)
  1915. {
  1916. /* If 'bal' instruction size is '2' and reg operand is not 'ra'
  1917. then goto next instruction. */
  1918. if (IS_INSN_MNEMONIC ("bal") && (i == 0)
  1919. && (instruction->size == 2) && (insn->arg[i].rp != 14))
  1920. goto next_insn;
  1921. /* If 'storb' instruction with 'sp' reg and 16-bit disp of
  1922. * reg-pair, leads to undefined trap, so this should use
  1923. * 20-bit disp of reg-pair. */
  1924. if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2)
  1925. && (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp))
  1926. goto next_insn;
  1927. /* Only check range - don't update the constant's value, since the
  1928. current instruction may not be the last we try to match.
  1929. The constant's value will be updated later, right before printing
  1930. it to the object file. */
  1931. if ((insn->arg[i].X_op == O_constant)
  1932. && (op_error = check_range (&insn->arg[i].constant, cur_size[i],
  1933. cur_flags[i], 0)))
  1934. {
  1935. if (invalid_const == -1)
  1936. {
  1937. invalid_const = i + 1;
  1938. const_err = op_error;
  1939. }
  1940. goto next_insn;
  1941. }
  1942. /* For symbols, we make sure the relocation size (which was already
  1943. determined) is sufficient. */
  1944. else if ((insn->arg[i].X_op == O_symbol)
  1945. && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
  1946. > cur_size[i]))
  1947. goto next_insn;
  1948. }
  1949. found_const_within_range = 1;
  1950. /* If we got till here -> Full match is found. */
  1951. match = 1;
  1952. break;
  1953. /* Try again with next instruction. */
  1954. next_insn:
  1955. instruction++;
  1956. }
  1957. if (!match)
  1958. {
  1959. /* We haven't found a match - instruction can't be assembled. */
  1960. if (!found_same_number_of_operands)
  1961. as_bad (_("Incorrect number of operands"));
  1962. else if (!found_same_argument_types)
  1963. as_bad (_("Illegal type of operand (arg %d)"), invalid_optype);
  1964. else if (!found_const_within_range)
  1965. {
  1966. switch (const_err)
  1967. {
  1968. case OP_OUT_OF_RANGE:
  1969. as_bad (_("Operand out of range (arg %d)"), invalid_const);
  1970. break;
  1971. case OP_NOT_EVEN:
  1972. as_bad (_("Operand has odd displacement (arg %d)"), invalid_const);
  1973. break;
  1974. default:
  1975. as_bad (_("Illegal operand (arg %d)"), invalid_const);
  1976. break;
  1977. }
  1978. }
  1979. return 0;
  1980. }
  1981. else
  1982. /* Full match - print the encoding to output file. */
  1983. {
  1984. /* Make further checking (such that couldn't be made earlier).
  1985. Warn the user if necessary. */
  1986. warn_if_needed (insn);
  1987. /* Check whether we need to adjust the instruction pointer. */
  1988. if (adjust_if_needed (insn))
  1989. /* If instruction pointer was adjusted, we need to update
  1990. the size of the current template operands. */
  1991. GET_CURRENT_SIZE;
  1992. for (i = 0; i < insn->nargs; i++)
  1993. {
  1994. int j = instruction->flags & REVERSE_MATCH ?
  1995. i == 0 ? 1 :
  1996. i == 1 ? 0 : i :
  1997. i;
  1998. /* This time, update constant value before printing it. */
  1999. if ((insn->arg[j].X_op == O_constant)
  2000. && (check_range (&insn->arg[j].constant, cur_size[j],
  2001. cur_flags[j], 1) != OP_LEGAL))
  2002. as_fatal (_("Illegal operand (arg %d)"), j+1);
  2003. }
  2004. /* First, copy the instruction's opcode. */
  2005. output_opcode[0] = BIN (instruction->match, instruction->match_bits);
  2006. for (i = 0; i < insn->nargs; i++)
  2007. {
  2008. /* For BAL (ra),disp17 instruction only. And also set the
  2009. DISP24a relocation type. */
  2010. if (IS_INSN_MNEMONIC ("bal") && (instruction->size == 2) && i == 0)
  2011. {
  2012. insn->rtype = BFD_RELOC_CR16_DISP24a;
  2013. continue;
  2014. }
  2015. cur_arg_num = i;
  2016. print_operand (cur_size[i], instruction->operands[i].shift,
  2017. &insn->arg[i]);
  2018. }
  2019. }
  2020. return 1;
  2021. }
  2022. /* Print the instruction.
  2023. Handle also cases where the instruction is relaxable/relocatable. */
  2024. static void
  2025. print_insn (ins *insn)
  2026. {
  2027. unsigned int i, j, insn_size;
  2028. char *this_frag;
  2029. unsigned short words[4];
  2030. int addr_mod;
  2031. /* Arrange the insn encodings in a WORD size array. */
  2032. for (i = 0, j = 0; i < 2; i++)
  2033. {
  2034. words[j++] = (output_opcode[i] >> 16) & 0xFFFF;
  2035. words[j++] = output_opcode[i] & 0xFFFF;
  2036. }
  2037. /* Handle relocation. */
  2038. if ((instruction->flags & RELAXABLE) && relocatable)
  2039. {
  2040. int relax_subtype;
  2041. /* Write the maximal instruction size supported. */
  2042. insn_size = INSN_MAX_SIZE;
  2043. if (IS_INSN_TYPE (BRANCH_INS))
  2044. {
  2045. switch (insn->rtype)
  2046. {
  2047. case BFD_RELOC_CR16_DISP24:
  2048. relax_subtype = 2;
  2049. break;
  2050. case BFD_RELOC_CR16_DISP16:
  2051. relax_subtype = 1;
  2052. break;
  2053. default:
  2054. relax_subtype = 0;
  2055. break;
  2056. }
  2057. }
  2058. else
  2059. abort ();
  2060. this_frag = frag_var (rs_machine_dependent, insn_size *2,
  2061. 4, relax_subtype,
  2062. insn->exp.X_add_symbol,
  2063. 0,
  2064. 0);
  2065. }
  2066. else
  2067. {
  2068. insn_size = instruction->size;
  2069. this_frag = frag_more (insn_size * 2);
  2070. if ((relocatable) && (insn->rtype != BFD_RELOC_NONE))
  2071. {
  2072. reloc_howto_type *reloc_howto;
  2073. int size;
  2074. reloc_howto = bfd_reloc_type_lookup (stdoutput, insn->rtype);
  2075. if (!reloc_howto)
  2076. abort ();
  2077. size = bfd_get_reloc_size (reloc_howto);
  2078. if (size < 1 || size > 4)
  2079. abort ();
  2080. fix_new_exp (frag_now, this_frag - frag_now->fr_literal,
  2081. size, &insn->exp, reloc_howto->pc_relative,
  2082. insn->rtype);
  2083. }
  2084. }
  2085. /* Verify a 2-byte code alignment. */
  2086. addr_mod = frag_now_fix () & 1;
  2087. if (frag_now->has_code && frag_now->insn_addr != addr_mod)
  2088. as_bad (_("instruction address is not a multiple of 2"));
  2089. frag_now->insn_addr = addr_mod;
  2090. frag_now->has_code = 1;
  2091. /* Write the instruction encoding to frag. */
  2092. for (i = 0; i < insn_size; i++)
  2093. {
  2094. md_number_to_chars (this_frag, (valueT) words[i], 2);
  2095. this_frag += 2;
  2096. }
  2097. }
  2098. /* Actually assemble an instruction. */
  2099. static void
  2100. cr16_assemble (const char *op, char *param)
  2101. {
  2102. ins cr16_ins;
  2103. /* Find the instruction. */
  2104. instruction = (const inst *) str_hash_find (cr16_inst_hash, op);
  2105. if (instruction == NULL)
  2106. {
  2107. as_bad (_("Unknown opcode: `%s'"), op);
  2108. return;
  2109. }
  2110. /* Tie dwarf2 debug info to the address at the start of the insn. */
  2111. dwarf2_emit_insn (0);
  2112. /* Parse the instruction's operands. */
  2113. parse_insn (&cr16_ins, param);
  2114. /* Assemble the instruction - return upon failure. */
  2115. if (assemble_insn (op, &cr16_ins) == 0)
  2116. return;
  2117. /* Print the instruction. */
  2118. print_insn (&cr16_ins);
  2119. }
  2120. /* This is the guts of the machine-dependent assembler. OP points to a
  2121. machine dependent instruction. This function is supposed to emit
  2122. the frags/bytes it assembles to. */
  2123. void
  2124. md_assemble (char *op)
  2125. {
  2126. ins cr16_ins;
  2127. char *param, param1[32];
  2128. /* Reset global variables for a new instruction. */
  2129. reset_vars (op);
  2130. /* Strip the mnemonic. */
  2131. for (param = op; *param != 0 && !ISSPACE (*param); param++)
  2132. ;
  2133. *param++ = '\0';
  2134. /* bCC instructions and adjust the mnemonic by adding extra white spaces. */
  2135. if (is_bcc_insn (op))
  2136. {
  2137. strcpy (param1, get_b_cc (op));
  2138. strcat (param1,",");
  2139. strcat (param1, param);
  2140. param = (char *) &param1;
  2141. cr16_assemble ("b", param);
  2142. return;
  2143. }
  2144. /* Checking the cinv options and adjust the mnemonic by removing the
  2145. extra white spaces. */
  2146. if (streq ("cinv", op))
  2147. {
  2148. /* Validate the cinv options. */
  2149. unsigned int op_len, param_len;
  2150. check_cinv_options (param);
  2151. op_len = strlen (op);
  2152. param_len = strlen (param) + 1;
  2153. memmove (op + op_len, param, param_len);
  2154. }
  2155. /* MAPPING - SHIFT INSN, if imm4/imm16 positive values
  2156. lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
  2157. as CR16 core doesn't support lsh[b/w] right shift operations. */
  2158. if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op))
  2159. && (param [0] == '$'))
  2160. {
  2161. strcpy (param1, param);
  2162. /* Find the instruction. */
  2163. instruction = (const inst *) str_hash_find (cr16_inst_hash, op);
  2164. parse_operands (&cr16_ins, param1);
  2165. if (((&cr16_ins)->arg[0].type == arg_ic)
  2166. && ((&cr16_ins)->arg[0].constant >= 0))
  2167. {
  2168. if (streq ("lshb", op))
  2169. cr16_assemble ("ashub", param);
  2170. else if (streq ("lshd", op))
  2171. cr16_assemble ("ashud", param);
  2172. else
  2173. cr16_assemble ("ashuw", param);
  2174. return;
  2175. }
  2176. }
  2177. cr16_assemble (op, param);
  2178. }