itbl-parse.y 11 KB

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  1. /* itbl-parse.y
  2. Copyright (C) 1997-2022 Free Software Foundation, Inc.
  3. This file is part of GAS, the GNU Assembler.
  4. GAS is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 3, or (at your option)
  7. any later version.
  8. GAS is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with GAS; see the file COPYING. If not, write to the Free
  14. Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  15. 02110-1301, USA. */
  16. %{
  17. /*
  18. Yacc grammar for instruction table entries.
  19. =======================================================================
  20. Original Instruction table specification document:
  21. MIPS Coprocessor Table Specification
  22. ====================================
  23. This document describes the format of the MIPS coprocessor table. The
  24. table specifies a list of valid functions, data registers and control
  25. registers that can be used in coprocessor instructions. This list,
  26. together with the coprocessor instruction classes listed below,
  27. specifies the complete list of coprocessor instructions that will
  28. be recognized and assembled by the GNU assembler. In effect,
  29. this makes the GNU assembler table-driven, where the table is
  30. specified by the programmer.
  31. The table is an ordinary text file that the GNU assembler reads when
  32. it starts. Using the information in the table, the assembler
  33. generates an internal list of valid coprocessor registers and
  34. functions. The assembler uses this internal list in addition to the
  35. standard MIPS registers and instructions which are built-in to the
  36. assembler during code generation.
  37. To specify the coprocessor table when invoking the GNU assembler, use
  38. the command line option "--itbl file", where file is the
  39. complete name of the table, including path and extension.
  40. Examples:
  41. gas -t cop.tbl test.s -o test.o
  42. gas -t /usr/local/lib/cop.tbl test.s -o test.o
  43. gas --itbl d:\gnu\data\cop.tbl test.s -o test.o
  44. Only one table may be supplied during a single invocation of
  45. the assembler.
  46. Instruction classes
  47. ===================
  48. Below is a list of the valid coprocessor instruction classes for
  49. any given coprocessor "z". These instructions are already recognized
  50. by the assembler, and are listed here only for reference.
  51. Class format instructions
  52. -------------------------------------------------
  53. Class1:
  54. op base rt offset
  55. LWCz rt,offset (base)
  56. SWCz rt,offset (base)
  57. Class2:
  58. COPz sub rt rd 0
  59. MTCz rt,rd
  60. MFCz rt,rd
  61. CTCz rt,rd
  62. CFCz rt,rd
  63. Class3:
  64. COPz CO cofun
  65. COPz cofun
  66. Class4:
  67. COPz BC br offset
  68. BCzT offset
  69. BCzF offset
  70. Class5:
  71. COPz sub rt rd 0
  72. DMFCz rt,rd
  73. DMTCz rt,rd
  74. Class6:
  75. op base rt offset
  76. LDCz rt,offset (base)
  77. SDCz rt,offset (base)
  78. Class7:
  79. COPz BC br offset
  80. BCzTL offset
  81. BCzFL offset
  82. The coprocessor table defines coprocessor-specific registers that can
  83. be used with all of the above classes of instructions, where
  84. appropriate. It also defines additional coprocessor-specific
  85. functions for Class3 (COPz cofun) instructions, Thus, the table allows
  86. the programmer to use convenient mnemonics and operands for these
  87. functions, instead of the COPz mmenmonic and cofun operand.
  88. The names of the MIPS general registers and their aliases are defined
  89. by the assembler and will be recognized as valid register names by the
  90. assembler when used (where allowed) in coprocessor instructions.
  91. However, the names and values of all coprocessor data and control
  92. register mnemonics must be specified in the coprocessor table.
  93. Table Grammar
  94. =============
  95. Here is the grammar for the coprocessor table:
  96. table -> entry*
  97. entry -> [z entrydef] [comment] '\n'
  98. entrydef -> type name val
  99. entrydef -> 'insn' name val funcdef ; type of entry (instruction)
  100. z -> 'p'['0'..'3'] ; processor number
  101. type -> ['dreg' | 'creg' | 'greg' ] ; type of entry (register)
  102. ; 'dreg', 'creg' or 'greg' specifies a data, control, or general
  103. ; register mnemonic, respectively
  104. name -> [ltr|dec]* ; mnemonic of register/function
  105. val -> [dec|hex] ; register/function number (integer constant)
  106. funcdef -> frange flags fields
  107. ; bitfield range for opcode
  108. ; list of fields' formats
  109. fields -> field*
  110. field -> [','] ftype frange flags
  111. flags -> ['*' flagexpr]
  112. flagexpr -> '[' flagexpr ']'
  113. flagexpr -> val '|' flagexpr
  114. ftype -> [ type | 'immed' | 'addr' ]
  115. ; 'immed' specifies an immediate value; see grammar for "val" above
  116. ; 'addr' specifies a C identifier; name of symbol to be resolved at
  117. ; link time
  118. frange -> ':' val '-' val ; starting to ending bit positions, where
  119. ; where 0 is least significant bit
  120. frange -> (null) ; default range of 31-0 will be assumed
  121. comment -> [';'|'#'] [char]*
  122. char -> any printable character
  123. ltr -> ['a'..'z'|'A'..'Z']
  124. dec -> ['0'..'9']* ; value in decimal
  125. hex -> '0x'['0'..'9' | 'a'..'f' | 'A'..'F']* ; value in hexadecimal
  126. Examples
  127. ========
  128. Example 1:
  129. The table:
  130. p1 dreg d1 1 ; data register "d1" for COP1 has value 1
  131. p1 creg c3 3 ; ctrl register "c3" for COP1 has value 3
  132. p3 func fill 0x1f:24-20 ; function "fill" for COP3 has value 31 and
  133. ; no fields
  134. will allow the assembler to accept the following coprocessor instructions:
  135. LWC1 d1,0x100 ($2)
  136. fill
  137. Here, the general purpose register "$2", and instruction "LWC1", are standard
  138. mnemonics built-in to the MIPS assembler.
  139. Example 2:
  140. The table:
  141. p3 dreg d3 3 ; data register "d3" for COP3 has value 3
  142. p3 creg c2 22 ; control register "c2" for COP3 has value 22
  143. p3 func fee 0x1f:24-20 dreg:17-13 creg:12-8 immed:7-0
  144. ; function "fee" for COP3 has value 31, and 3 fields
  145. ; consisting of a data register, a control register,
  146. ; and an immediate value.
  147. will allow the assembler to accept the following coprocessor instruction:
  148. fee d3,c2,0x1
  149. and will emit the object code:
  150. 31-26 25 24-20 19-18 17-13 12-8 7-0
  151. COPz CO fun dreg creg immed
  152. 010011 1 11111 00 00011 10110 00000001
  153. 0x4ff07601
  154. Example 3:
  155. The table:
  156. p3 dreg d3 3 ; data register "d3" for COP3 has value 3
  157. p3 creg c2 22 ; control register "c2" for COP3 has value 22
  158. p3 func fuu 0x01f00001 dreg:17-13 creg:12-8
  159. will allow the assembler to accept the following coprocessor
  160. instruction:
  161. fuu d3,c2
  162. and will emit the object code:
  163. 31-26 25 24-20 19-18 17-13 12-8 7-0
  164. COPz CO fun dreg creg
  165. 010011 1 11111 00 00011 10110 00000001
  166. 0x4ff07601
  167. In this way, the programmer can force arbitrary bits of an instruction
  168. to have predefined values.
  169. =======================================================================
  170. Additional notes:
  171. Encoding of ranges:
  172. To handle more than one bit position range within an instruction,
  173. use 0s to mask out the ranges which don't apply.
  174. May decide to modify the syntax to allow commas separate multiple
  175. ranges within an instruction (range','range).
  176. Changes in grammar:
  177. The number of parms argument to the function entry
  178. was deleted from the original format such that we now count the fields.
  179. ----
  180. FIXME! should really change lexical analyzer
  181. to recognize 'dreg' etc. in context sensitive way.
  182. Currently function names or mnemonics may be incorrectly parsed as keywords
  183. FIXME! hex is ambiguous with any digit
  184. */
  185. #include "as.h"
  186. #include "itbl-lex.h"
  187. #include "itbl-ops.h"
  188. /* #define DEBUG */
  189. #ifdef DEBUG
  190. #ifndef DBG_LVL
  191. #define DBG_LVL 1
  192. #endif
  193. #else
  194. #define DBG_LVL 0
  195. #endif
  196. #if DBG_LVL >= 1
  197. #define DBG(x) printf x
  198. #else
  199. #define DBG(x)
  200. #endif
  201. #if DBG_LVL >= 2
  202. #define DBGL2(x) printf x
  203. #else
  204. #define DBGL2(x)
  205. #endif
  206. static int sbit, ebit;
  207. static struct itbl_entry *insn=0;
  208. static void yyerror (const char *);
  209. %}
  210. %union
  211. {
  212. char *str;
  213. int num;
  214. int processor;
  215. unsigned long val;
  216. }
  217. %token DREG CREG GREG IMMED ADDR INSN NUM ID NL PNUM
  218. %type <val> value flags flagexpr
  219. %type <num> number NUM ftype regtype pnum PNUM
  220. %type <str> ID name
  221. %start insntbl
  222. %%
  223. insntbl:
  224. entrys
  225. ;
  226. entrys:
  227. entry entrys
  228. |
  229. ;
  230. entry:
  231. pnum regtype name value NL
  232. {
  233. DBG (("line %d: entry pnum=%d type=%d name=%s value=x%x\n",
  234. insntbl_line, $1, $2, $3, $4));
  235. itbl_add_reg ($1, $2, $3, $4);
  236. }
  237. | pnum INSN name value range flags
  238. {
  239. DBG (("line %d: entry pnum=%d type=INSN name=%s value=x%x",
  240. insntbl_line, $1, $3, $4));
  241. DBG ((" sbit=%d ebit=%d flags=0x%x\n", sbit, ebit, $6));
  242. insn=itbl_add_insn ($1, $3, $4, sbit, ebit, $6);
  243. }
  244. fieldspecs NL
  245. {}
  246. | NL
  247. | error NL
  248. ;
  249. fieldspecs:
  250. ',' fieldspec fieldspecs
  251. | fieldspec fieldspecs
  252. |
  253. ;
  254. ftype:
  255. regtype
  256. {
  257. DBGL2 (("ftype\n"));
  258. $$ = $1;
  259. }
  260. | ADDR
  261. {
  262. DBGL2 (("addr\n"));
  263. $$ = ADDR;
  264. }
  265. | IMMED
  266. {
  267. DBGL2 (("immed\n"));
  268. $$ = IMMED;
  269. }
  270. ;
  271. fieldspec:
  272. ftype range flags
  273. {
  274. DBG (("line %d: field type=%d sbit=%d ebit=%d, flags=0x%x\n",
  275. insntbl_line, $1, sbit, ebit, $3));
  276. itbl_add_operand (insn, $1, sbit, ebit, $3);
  277. }
  278. ;
  279. flagexpr:
  280. NUM '|' flagexpr
  281. {
  282. $$ = $1 | $3;
  283. }
  284. | '[' flagexpr ']'
  285. {
  286. $$ = $2;
  287. }
  288. | NUM
  289. {
  290. $$ = $1;
  291. }
  292. ;
  293. flags:
  294. '*' flagexpr
  295. {
  296. DBGL2 (("flags=%d\n", $2));
  297. $$ = $2;
  298. }
  299. |
  300. {
  301. $$ = 0;
  302. }
  303. ;
  304. range:
  305. ':' NUM '-' NUM
  306. {
  307. DBGL2 (("range %d %d\n", $2, $4));
  308. sbit = $2;
  309. ebit = $4;
  310. }
  311. |
  312. {
  313. sbit = 31;
  314. ebit = 0;
  315. }
  316. ;
  317. pnum:
  318. PNUM
  319. {
  320. DBGL2 (("pnum=%d\n",$1));
  321. $$ = $1;
  322. }
  323. ;
  324. regtype:
  325. DREG
  326. {
  327. DBGL2 (("dreg\n"));
  328. $$ = DREG;
  329. }
  330. | CREG
  331. {
  332. DBGL2 (("creg\n"));
  333. $$ = CREG;
  334. }
  335. | GREG
  336. {
  337. DBGL2 (("greg\n"));
  338. $$ = GREG;
  339. }
  340. ;
  341. name:
  342. ID
  343. {
  344. DBGL2 (("name=%s\n",$1));
  345. $$ = $1;
  346. }
  347. ;
  348. number:
  349. NUM
  350. {
  351. DBGL2 (("num=%d\n",$1));
  352. $$ = $1;
  353. }
  354. ;
  355. value:
  356. NUM
  357. {
  358. DBGL2 (("val=x%x\n",$1));
  359. $$ = $1;
  360. }
  361. ;
  362. %%
  363. static void
  364. yyerror (const char *msg)
  365. {
  366. printf ("line %d: %s\n", insntbl_line, msg);
  367. }