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c_dagmodim_lnz_imltbl.s

c_dagmodim_lnz_imltbl.s 1.7 KB
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  1. //Original:/testcases/core/c_dagmodim_lnz_imltbl/c_dagmodim_lnz_imltbl.dsp
    2. 

  2. // Spec Reference: dagmodim l not zero & i+m < b
    3. 

  3. # mach: bfin
    4. 

  4. 

  5. .include "testutils.inc"
    6. 

  6. 	start
    7. 

  7. 

  8. 

  9. INIT_R_REGS 0;
    10. 

  10. 

  11. imm32 i0, 0x00001000;
    12. 

  12. imm32 i1, 0x00001100;
    13. 

  13. imm32 i2, 0x00001010;
    14. 

  14. imm32 i3, 0x00001001;
    15. 

  15. 

  16. imm32 b0, 0x0000110e;
    17. 

  17. imm32 b1, 0x0000110c;
    18. 

  18. imm32 b2, 0x0000110a;
    19. 

  19. imm32 b3, 0x00001108;
    20. 

  20. 

  21. imm32 l0, 0x000000a1;
    22. 

  22. imm32 l1, 0x000000b2;
    23. 

  23. imm32 l2, 0x000000c3;
    24. 

  24. imm32 l3, 0x000000d4;
    25. 

  25. 

  26. imm32 m0, 0x00000005;
    27. 

  27. imm32 m1, 0x00000004;
    28. 

  28. imm32 m2, 0x00000003;
    29. 

  29. imm32 m3, 0x00000002;
    30. 

  30. 

  31.  I0 += M0;
    32. 

  32.  I1 += M1;
    33. 

  33.  I2 += M2;
    34. 

  34.  I3 += M3;
    35. 

  35. R0 = I0;
    36. 

  36. R1 = I1;
    37. 

  37. R2 = I2;
    38. 

  38. R3 = I3;
    39. 

  39.  I0 += M1;
    40. 

  40.  I1 += M2;
    41. 

  41.  I2 += M3;
    42. 

  42.  I3 += M0;
    43. 

  43. R4 = I0;
    44. 

  44. R5 = I1;
    45. 

  45. R6 = I2;
    46. 

  46. R7 = I3;
    47. 

  47. CHECKREG r0, 0x00001005;
    48. 

  48. CHECKREG r1, 0x00001104;
    49. 

  49. CHECKREG r2, 0x00001013;
    50. 

  50. CHECKREG r3, 0x00001003;
    51. 

  51. CHECKREG r4, 0x00001009;
    52. 

  52. CHECKREG r5, 0x00001107;
    53. 

  53. CHECKREG r6, 0x00001015;
    54. 

  54. CHECKREG r7, 0x00001008;
    55. 

  55. 

  56. 

  57.  I0 -= M2;
    58. 

  58.  I1 -= M3;
    59. 

  59.  I2 -= M0;
    60. 

  60.  I3 -= M1;
    61. 

  61. R0 = I0;
    62. 

  62. R1 = I1;
    63. 

  63. R2 = I2;
    64. 

  64. R3 = I3;
    65. 

  65.  I0 -= M3;
    66. 

  66.  I1 -= M2;
    67. 

  67.  I2 -= M1;
    68. 

  68.  I3 -= M0;
    69. 

  69. R4 = I0;
    70. 

  70. R5 = I1;
    71. 

  71. R6 = I2;
    72. 

  72. R7 = I3;
    73. 

  73. CHECKREG r0, 0x000010A7;
    74. 

  74. CHECKREG r1, 0x000011B7;
    75. 

  75. CHECKREG r2, 0x000010D3;
    76. 

  76. CHECKREG r3, 0x000010D8;
    77. 

  77. CHECKREG r4, 0x00001146;
    78. 

  78. CHECKREG r5, 0x000011B4;
    79. 

  79. CHECKREG r6, 0x00001192;
    80. 

  80. CHECKREG r7, 0x000011A7;
    81. 

  81. 

  82.  I0 += M3 (BREV);
    83. 

  83.  I1 += M0 (BREV);
    84. 

  84.  I2 += M1 (BREV);
    85. 

  85.  I3 += M2 (BREV);
    86. 

  86. R0 = I0;
    87. 

  87. R1 = I1;
    88. 

  88. R2 = I2;
    89. 

  89. R3 = I3;
    90. 

  90.  I0 += M2 (BREV);
    91. 

  91.  I1 += M3 (BREV);
    92. 

  92.  I2 += M0 (BREV);
    93. 

  93.  I3 += M1 (BREV);
    94. 

  94. R4 = I0;
    95. 

  95. R5 = I1;
    96. 

  96. R6 = I2;
    97. 

  97. R7 = I3;
    98. 

  98. CHECKREG r0, 0x00001145;
    99. 

  99. CHECKREG r1, 0x000011B3;
    100. 

  100. CHECKREG r2, 0x00001196;
    101. 

  101. CHECKREG r3, 0x000011A5;
    102. 

  102. CHECKREG r4, 0x00001146;
    103. 

  103. CHECKREG r5, 0x000011B0;
    104. 

  104. CHECKREG r6, 0x00001190;
    105. 

  105. CHECKREG r7, 0x000011A3;
    106. 

  106. 

  107. 

  108. 

  109. pass
    110.