c_dsp32alu_rrppmm_sft.s 7.1 KB

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  1. //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrppmm_sft/c_dsp32alu_rrppmm_sft.dsp
  2. // Spec Reference: dsp32alu (dreg, dreg) = +/+, -/- (dreg, dreg) >>, <<
  3. # mach: bfin
  4. .include "testutils.inc"
  5. start
  6. R0 = 0;
  7. ASTAT = R0;
  8. imm32 r0, 0x95679911;
  9. imm32 r1, 0x2789ab1d;
  10. imm32 r2, 0x34945515;
  11. imm32 r3, 0x46967717;
  12. imm32 r4, 0x5597891b;
  13. imm32 r5, 0x6989ab1d;
  14. imm32 r6, 0x94445515;
  15. imm32 r7, 0x96667777;
  16. R0 = R0 +|+ R0, R7 = R0 -|- R0 (ASR);
  17. R1 = R0 +|+ R1, R6 = R0 -|- R1 (ASL);
  18. R2 = R0 +|+ R2, R5 = R0 -|- R2 (ASR);
  19. R3 = R0 +|+ R3, R4 = R0 -|- R3 (ASR);
  20. R4 = R0 +|+ R4, R3 = R0 -|- R4 (ASL);
  21. R5 = R0 +|+ R5, R2 = R0 -|- R5 (ASR);
  22. R6 = R0 +|+ R6, R1 = R0 -|- R6 (ASL);
  23. R7 = R0 +|+ R7, R0 = R0 -|- R7 (ASR);
  24. CHECKREG r0, 0xcAB3cC88;
  25. CHECKREG r1, 0x73567A52;
  26. CHECKREG r2, 0xf27FfB89;
  27. CHECKREG r3, 0xdBFE1028;
  28. CHECKREG r4, 0x799E541C;
  29. CHECKREG r5, 0xa2E89D87;
  30. CHECKREG r6, 0xE246e9F2;
  31. CHECKREG r7, 0xcAB3cC88;
  32. imm32 r0, 0x11678911;
  33. imm32 r1, 0xa719ab1d;
  34. imm32 r2, 0x3a415515;
  35. imm32 r3, 0x46a67717;
  36. imm32 r4, 0x556a891b;
  37. imm32 r5, 0x6789ab1d;
  38. imm32 r6, 0x74445a15;
  39. imm32 r7, 0x866677a7;
  40. R0 = R1 +|+ R0, R7 = R1 -|- R0 (ASR);
  41. R1 = R1 +|+ R1, R6 = R1 -|- R1 (ASR);
  42. R2 = R1 +|+ R2, R5 = R1 -|- R2 (ASL);
  43. R3 = R1 +|+ R3, R4 = R1 -|- R3 (ASR);
  44. R4 = R1 +|+ R4, R3 = R1 -|- R4 (ASR);
  45. R5 = R1 +|+ R5, R2 = R1 -|- R5 (ASR);
  46. R6 = R1 +|+ R6, R1 = R1 -|- R6 (ASL);
  47. R7 = R1 +|+ R7, R0 = R1 -|- R7 (ASR);
  48. CHECKREG r0, 0x41AC229A;
  49. CHECKREG r1, 0x4E32563A;
  50. CHECKREG r2, 0xe6B4fF86;
  51. CHECKREG r3, 0xfB70088D;
  52. CHECKREG r4, 0xaBA9a290;
  53. CHECKREG r5, 0xc064aB96;
  54. CHECKREG r6, 0x4E32563A;
  55. CHECKREG r7, 0x0C8533A0;
  56. imm32 r0, 0xb567891b;
  57. imm32 r1, 0x2b89abbd;
  58. imm32 r2, 0x34b45b15;
  59. imm32 r3, 0x466bb717;
  60. imm32 r4, 0x556bb91b;
  61. imm32 r5, 0x67b9ab1d;
  62. imm32 r6, 0x7b4455b5;
  63. imm32 r7, 0xb666777b;
  64. R0 = R2 +|+ R0, R7 = R2 -|- R0 (ASR);
  65. R1 = R2 +|+ R1, R6 = R2 -|- R1 (ASR);
  66. R2 = R2 +|+ R2, R5 = R2 -|- R2 (ASR);
  67. R3 = R2 +|+ R3, R4 = R2 -|- R3 (ASL);
  68. R4 = R2 +|+ R4, R3 = R2 -|- R4 (ASR);
  69. R5 = R2 +|+ R5, R2 = R2 -|- R5 (ASR);
  70. R6 = R2 +|+ R6, R1 = R2 -|- R6 (ASL);
  71. R7 = R2 +|+ R7, R0 = R2 -|- R7 (ASR);
  72. CHECKREG r0, 0xED5Ae246;
  73. CHECKREG r1, 0x2B8AaBBC;
  74. CHECKREG r2, 0x1A5A2D8A;
  75. CHECKREG r3, 0x2C11098C;
  76. CHECKREG r4, 0x08A35188;
  77. CHECKREG r5, 0x1A5A2D8A;
  78. CHECKREG r6, 0x3DDE0A6C;
  79. CHECKREG r7, 0x2D004B43;
  80. imm32 r0, 0xbc678c11;
  81. imm32 r1, 0x27c9cb1d;
  82. imm32 r2, 0x344c5515;
  83. imm32 r3, 0x46c6c717;
  84. imm32 r4, 0x55678c1b;
  85. imm32 r5, 0x6c89abcd;
  86. imm32 r6, 0x7444551c;
  87. imm32 r7, 0x8c667777;
  88. R0 = R3 +|+ R0, R7 = R3 -|- R0 (ASL);
  89. R1 = R3 +|+ R1, R6 = R3 -|- R1 (ASR);
  90. R2 = R3 +|+ R2, R5 = R3 -|- R2 (ASR);
  91. R3 = R3 +|+ R3, R4 = R3 -|- R3 (ASR);
  92. R4 = R3 +|+ R4, R3 = R3 -|- R4 (ASL);
  93. R5 = R3 +|+ R5, R2 = R3 -|- R5 (ASR);
  94. R6 = R3 +|+ R6, R1 = R3 -|- R6 (ASR);
  95. R7 = R3 +|+ R7, R0 = R3 -|- R7 (ASL);
  96. CHECKREG r0, 0xF19C3044;
  97. CHECKREG r1, 0xbF07C818;
  98. CHECKREG r2, 0xC227eA96;
  99. CHECKREG r3, 0x8D8C8E2E;
  100. CHECKREG r4, 0x8D8C8E2E;
  101. CHECKREG r5, 0xCB64a397;
  102. CHECKREG r6, 0xCE85C615;
  103. CHECKREG r7, 0x44940874;
  104. imm32 r0, 0xd56789d1;
  105. imm32 r1, 0x2d89abdd;
  106. imm32 r2, 0x34d455d5;
  107. imm32 r3, 0x4d667717;
  108. imm32 r4, 0x5dd7891b;
  109. imm32 r5, 0x6789ab1d;
  110. imm32 r6, 0xd44d5515;
  111. imm32 r7, 0xd666d777;
  112. R0 = R4 +|+ R0, R7 = R4 -|- R0 (ASR);
  113. R1 = R4 +|+ R1, R6 = R4 -|- R1 (ASR);
  114. R2 = R4 +|+ R2, R5 = R4 -|- R2 (ASR);
  115. R3 = R4 +|+ R3, R4 = R4 -|- R3 (ASL);
  116. R4 = R4 +|+ R4, R3 = R4 -|- R4 (ASR);
  117. R5 = R4 +|+ R5, R2 = R4 -|- R5 (ASL);
  118. R6 = R4 +|+ R6, R1 = R4 -|- R6 (ASR);
  119. R7 = R4 +|+ R7, R0 = R4 -|- R7 (ASR);
  120. CHECKREG r0, 0xeE551231;
  121. CHECKREG r1, 0x045D1AB4;
  122. CHECKREG r2, 0x18C214CA;
  123. CHECKREG r3, 0x00000000;
  124. CHECKREG r4, 0x20E22408;
  125. CHECKREG r5, 0x6AC67B56;
  126. CHECKREG r6, 0x1C840953;
  127. CHECKREG r7, 0x328D11D6;
  128. imm32 r0, 0xc567a911;
  129. imm32 r1, 0x278aab1d;
  130. imm32 r2, 0x3c445515;
  131. imm32 r3, 0x46a67717;
  132. imm32 r4, 0x55c7891b;
  133. imm32 r5, 0x6a8cab1d;
  134. imm32 r6, 0x7444c515;
  135. imm32 r7, 0xa6667c77;
  136. R0 = R5 +|+ R0, R7 = R5 -|- R0 (ASR);
  137. R1 = R5 +|+ R1, R6 = R5 -|- R1 (ASL);
  138. R2 = R5 +|+ R2, R5 = R5 -|- R2 (ASR);
  139. R3 = R5 +|+ R3, R4 = R5 -|- R3 (ASR);
  140. R4 = R5 +|+ R4, R3 = R5 -|- R4 (ASR);
  141. R5 = R5 +|+ R5, R2 = R5 -|- R5 (ASL);
  142. R6 = R5 +|+ R6, R1 = R5 -|- R6 (ASR);
  143. R7 = R5 +|+ R7, R0 = R5 -|- R7 (ASR);
  144. CHECKREG r0, 0x04FFD585;
  145. CHECKREG r1, 0x6B46D608;
  146. CHECKREG r2, 0x00000000;
  147. CHECKREG r3, 0x17720887;
  148. CHECKREG r4, 0xFFB1a27D;
  149. CHECKREG r5, 0x5C90AC10;
  150. CHECKREG r6, 0xF14AD608;
  151. CHECKREG r7, 0x5791D68B;
  152. imm32 r0, 0xd5678911;
  153. imm32 r1, 0x2ddddd1d;
  154. imm32 r2, 0x34ddd515;
  155. imm32 r3, 0x46d67717;
  156. imm32 r4, 0x5d6d891b;
  157. imm32 r5, 0x6789db1d;
  158. imm32 r6, 0x74445d15;
  159. imm32 r7, 0xd66677d7;
  160. R0 = R6 +|+ R0, R7 = R6 -|- R0 (ASR);
  161. R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASR);
  162. R2 = R6 +|+ R2, R5 = R6 -|- R2 (ASR);
  163. R3 = R6 +|+ R3, R4 = R6 -|- R3 (ASL);
  164. R4 = R6 +|+ R4, R3 = R6 -|- R4 (ASR);
  165. R5 = R6 +|+ R5, R2 = R6 -|- R5 (ASR);
  166. R6 = R6 +|+ R6, R1 = R6 -|- R6 (ASL);
  167. R7 = R6 +|+ R7, R0 = R6 -|- R7 (ASR);
  168. CHECKREG r0, 0x9EAFcAF7;
  169. CHECKREG r1, 0x00000000;
  170. CHECKREG r2, 0x16040544;
  171. CHECKREG r3, 0x353C5719;
  172. CHECKREG r4, 0xEDF6E8E3;
  173. CHECKREG r5, 0x0D2F3AB7;
  174. CHECKREG r6, 0x8CCCFFF0;
  175. CHECKREG r7, 0xeE1D34F9;
  176. imm32 r0, 0xf567a911;
  177. imm32 r1, 0x2f8aab1d;
  178. imm32 r2, 0x34a45515;
  179. imm32 r3, 0x4a6f7717;
  180. imm32 r4, 0x5567f91b;
  181. imm32 r5, 0xa789af1d;
  182. imm32 r6, 0x74445515;
  183. imm32 r7, 0x866677f7;
  184. R0 = R7 +|+ R0, R7 = R7 -|- R0 (ASR);
  185. R1 = R7 +|+ R1, R6 = R7 -|- R1 (ASL);
  186. R2 = R7 +|+ R2, R5 = R7 -|- R2 (ASR);
  187. R3 = R7 +|+ R3, R4 = R7 -|- R3 (ASR);
  188. R4 = R7 +|+ R4, R3 = R7 -|- R4 (ASL);
  189. R5 = R7 +|+ R5, R2 = R7 -|- R5 (ASL);
  190. R6 = R7 +|+ R6, R1 = R7 -|- R6 (ASR);
  191. R7 = R7 +|+ R7, R0 = R7 -|- R7 (ASL);
  192. CHECKREG r0, 0x00000000;
  193. CHECKREG r1, 0xCB4Af763;
  194. CHECKREG r2, 0xFD24bC88;
  195. CHECKREG r3, 0x12EEdE8A;
  196. CHECKREG r4, 0x0F0EbF42;
  197. CHECKREG r5, 0x24D8e144;
  198. CHECKREG r6, 0xFD34700F;
  199. CHECKREG r7, 0x21FC9DCC;
  200. imm32 r0, 0xe5678911;
  201. imm32 r1, 0x2e89ab1d;
  202. imm32 r2, 0x34e45515;
  203. imm32 r3, 0x46667717;
  204. imm32 r4, 0x556e891b;
  205. imm32 r5, 0x6789ab1d;
  206. imm32 r6, 0x7444e515;
  207. imm32 r7, 0x86667e77;
  208. R4 = R2 +|+ R5, R3 = R2 -|- R5 (ASR);
  209. R0 = R5 +|+ R3, R5 = R5 -|- R3 (ASL);
  210. R2 = R6 +|+ R2, R0 = R6 -|- R2 (ASL);
  211. R3 = R4 +|+ R0, R2 = R4 -|- R0 (ASR);
  212. R7 = R7 +|+ R6, R6 = R7 -|- R6 (ASL);
  213. R6 = R1 +|+ R7, R1 = R1 -|- R7 (ASL);
  214. R5 = R0 +|+ R4, R7 = R0 -|- R4 (ASR);
  215. R1 = R3 +|+ R1, R4 = R3 -|- R1 (ASR);
  216. CHECKREG r0, 0x7EC02000;
  217. CHECKREG r1, 0x6C72EC0B;
  218. CHECKREG r2, 0xe7BBF00C;
  219. CHECKREG r3, 0x667B100C;
  220. CHECKREG r4, 0xfA082401;
  221. CHECKREG r5, 0x667B100C;
  222. CHECKREG r6, 0x47BAE46A;
  223. CHECKREG r7, 0x18450FF3;
  224. imm32 r0, 0xd5678911;
  225. imm32 r1, 0xff89ab1d;
  226. imm32 r2, 0x34f45515;
  227. imm32 r3, 0x46667717;
  228. imm32 r4, 0x556f891b;
  229. imm32 r5, 0x6789fb1d;
  230. imm32 r6, 0x74445f15;
  231. imm32 r7, 0x866677f7;
  232. R4 = R3 +|+ R3, R5 = R3 -|- R3 (ASR);
  233. R1 = R6 +|+ R1, R6 = R6 -|- R1 (ASL);
  234. R6 = R1 +|+ R4, R4 = R1 -|- R4 (ASL);
  235. R7 = R4 +|+ R2, R0 = R4 -|- R2 (ASR);
  236. R2 = R2 +|+ R6, R1 = R2 -|- R6 (ASR);
  237. R3 = R5 +|+ R5, R7 = R5 -|- R5 (ASL);
  238. R5 = R7 +|+ R7, R3 = R7 -|- R7 (ASL);
  239. R0 = R0 +|+ R0, R2 = R0 -|- R0 (ASR);
  240. CHECKREG r0, 0x06BAF2C2;
  241. CHECKREG r1, 0xEC7A1F0F;
  242. CHECKREG r2, 0x00000000;
  243. CHECKREG r3, 0x00000000;
  244. CHECKREG r4, 0x42683A9A;
  245. CHECKREG r5, 0x00000000;
  246. CHECKREG r6, 0x5C0016F6;
  247. CHECKREG r7, 0x00000000;
  248. pass