binutils-gdb/sim/testsuite/bfin/c_dsp32mac_pair_a1_i.s

//Original:/proj/frio/dv/testcases/core/c_dsp32mac_pair_a1_i/c_dsp32mac_pair_a1_i.dsp
// Spec Reference: dsp32mac pair a1 I
# mach: bfin

.include "testutils.inc"
	start

	A1 = A0 = 0;

// The result accumulated in A1      , and stored to a reg half
	imm32 r0, 0x93545abd;
	imm32 r1, 0x89bcfec7;
	imm32 r2, 0xa8945679;
	imm32 r3, 0x00890007;
	imm32 r4, 0xefb89569;
	imm32 r5, 0x1235890b;
	imm32 r6, 0x000c089d;
	imm32 r7, 0x678e0089;
	R7 = ( A1 += R1.L * R0.L ), A0 = R1.L * R0.L (IS);
	P1 = A1.w;
	R1 = ( A1 = R2.L * R3.L ), A0 -= R2.H * R3.L (IS);
	P2 = A1.w;
	R3 = ( A1 = R7.L * R4.L ), A0 += R7.H * R4.H (IS);
	P3 = A1.w;
	R5 = ( A1 += R6.L * R5.L ), A0 += R6.L * R5.H (IS);
	P4 = A1.w;
	CHECKREG r0, 0x93545ABD;
	CHECKREG r1, 0x00025D4F;
	CHECKREG r2, 0xA8945679;
	CHECKREG r3, 0xF9C9E563;
	CHECKREG r4, 0xEFB89569;
	CHECKREG r5, 0xF5C94922;
	CHECKREG r6, 0x000C089D;
	CHECKREG r7, 0xFF910EEB;
	CHECKREG p1, 0xFF910EEB;
	CHECKREG p2, 0x00025D4F;
	CHECKREG p3, 0xF9C9E563;
	CHECKREG p4, 0xF5C94922;

	imm32 r0, 0x98464abd;
	imm32 r1, 0xa1b5f4c7;
	imm32 r2, 0xa1146649;
	imm32 r3, 0x00010805;
	imm32 r4, 0xefbc1599;
	imm32 r5, 0x12350100;
	imm32 r6, 0x200c001d;
	imm32 r7, 0x628e0001;
	R5 = ( A1 += R1.L * R0.H ), A0 = R1.L * R0.L (IS);
	P1 = A1.w;
	R1 = ( A1 = R2.L * R3.H ), A0 = R2.H * R3.L (IS);
	P2 = A1.w;
	R3 = ( A1 = R4.L * R5.H ), A0 -= R4.H * R5.H (IS);
	P3 = A1.w;
	R1 = ( A1 += R6.L * R7.H ), A0 += R6.L * R7.H (IS);
	P4 = A1.w;
	CHECKREG r0, 0x98464ABD;
	CHECKREG r1, 0xFF90BFE3;
	CHECKREG r2, 0xA1146649;
	CHECKREG r3, 0xFF8595CD;
	CHECKREG r4, 0xEFBC1599;
	CHECKREG r5, 0xFA555F8C;
	CHECKREG r6, 0x200C001D;
	CHECKREG r7, 0x628E0001;
	CHECKREG p1, 0xFA555F8C;
	CHECKREG p2, 0x00006649;
	CHECKREG p3, 0xFF8595CD;
	CHECKREG p4, 0xFF90BFE3;

	imm32 r0, 0x713a459d;
	imm32 r1, 0xabd6aec7;
	imm32 r2, 0x7a145a79;
	imm32 r3, 0x08a100a7;
	imm32 r4, 0xef9a156a;
	imm32 r5, 0x1225a10b;
	imm32 r6, 0x0003401d;
	imm32 r7, 0x678e0a61;
	R5 = ( A1 += R1.H * R0.L ), A0 -= R1.L * R0.L (IS);
	P1 = A1.w;
	R7 = ( A1 -= R2.H * R3.L ), A0 = R2.H * R3.L (IS);
	P2 = A1.w;
	R1 = ( A1 -= R4.H * R5.L ), A0 += R4.H * R5.H (IS);
	P3 = A1.w;
	R5 = ( A1 += R6.H * R7.L ), A0 += R6.L * R7.H (IS);
	P4 = A1.w;
	CHECKREG r0, 0x713A459D;
	CHECKREG r1, 0xE54D2A3B;
	CHECKREG r2, 0x7A145A79;
	CHECKREG r3, 0x08A100A7;
	CHECKREG r4, 0xEF9A156A;
	CHECKREG r5, 0xE54DB17A;
	CHECKREG r6, 0x0003401D;
	CHECKREG r7, 0xE85E2D15;
	CHECKREG p1, 0xE8ADD021;
	CHECKREG p2, 0xE85E2D15;
	CHECKREG p3, 0xE54D2A3B;
	CHECKREG p4, 0xE54DB17A;

	imm32 r0, 0x773489bd;
	imm32 r1, 0x917cfec7;
	imm32 r2, 0xa9177679;
	imm32 r3, 0xd0910777;
	imm32 r4, 0xedb91579;
	imm32 r5, 0xd235910b;
	imm32 r6, 0x0d077999;
	imm32 r7, 0x677e0709;
	R1 = ( A1 += R5.H * R3.H ), A0 = R5.L * R3.L (IS);
	P1 = A1.w;
	R3 = ( A1 -= R2.H * R1.H ), A0 = R2.H * R1.L (IS);
	P2 = A1.w;
	R5 = ( A1 -= R7.H * R0.H ), A0 += R7.H * R0.H (IS);
	P3 = A1.w;
	R7 = ( A1 += R4.H * R6.H ), A0 -= R4.L * R6.H (IS);
	P4 = A1.w;
	CHECKREG r0, 0x773489BD;
	CHECKREG r1, 0xEDC9D17F;
	CHECKREG r2, 0xA9177679;
	CHECKREG r3, 0xE79AC370;
	CHECKREG r4, 0xEDB91579;
	CHECKREG r5, 0xB76A2BD8;
	CHECKREG r6, 0x0D077999;
	CHECKREG r7, 0xB67C10E7;
	CHECKREG p1, 0xEDC9D17F;
	CHECKREG p2, 0xE79AC370;
	CHECKREG p3, 0xB76A2BD8;
	CHECKREG p4, 0xB67C10E7;

	imm32 r0, 0x83547abd;
	imm32 r1, 0x88bc8ec7;
	imm32 r2, 0xa8895679;
	imm32 r3, 0x00080007;
	imm32 r4, 0xe6b86569;
	imm32 r5, 0x1A35860b;
	imm32 r6, 0x000c896d;
	imm32 r7, 0x67Be0096;
	R7 = ( A1 += R1.L * R0.L ) (IS);
	P1 = A1.w;
	R1 = ( A1 = R2.H * R3.L ) (IS);
	P2 = A1.w;
	R3 = ( A1 = R7.L * R4.H ) (IS);
	P3 = A1.w;
	R5 = ( A1 += R6.H * R5.H ) (IS);
	P4 = A1.w;
	CHECKREG r0, 0x83547ABD;
	CHECKREG r1, 0xFFFD9BBF;
	CHECKREG r2, 0xA8895679;
	CHECKREG r3, 0xF81E0AF0;
	CHECKREG r4, 0xE6B86569;
	CHECKREG r5, 0xF81F456C;
	CHECKREG r6, 0x000C896D;
	CHECKREG r7, 0x80334FD2;
	CHECKREG p1, 0x80334FD2;
	CHECKREG p2, 0xFFFD9BBF;
	CHECKREG p3, 0xF81E0AF0;
	CHECKREG p4, 0xF81F456C;

	imm32 r0, 0x9aa64abd;
	imm32 r1, 0xa1baf4c7;
	imm32 r2, 0xb114a649;
	imm32 r3, 0x0b010005;
	imm32 r4, 0xefbcdb69;
	imm32 r5, 0x123501bb;
	imm32 r6, 0x000c0d1b;
	imm32 r7, 0x678e0d01;
	R5 = ( A1 += R1.L * R0.H ) (M), A0 = R1.L * R0.L (IS);
	P1 = A1.w;
	R1 = ( A1 = R2.L * R3.H ) (M), A0 -= R2.H * R3.L (IS);
	P2 = A1.w;
	R3 = ( A1 -= R4.L * R5.H ) (M), A0 += R4.H * R5.H (IS);
	P3 = A1.w;
	R1 = ( A1 += R6.L * R7.H ) (M), A0 += R6.L * R7.H (IS);
	P4 = A1.w;
	CHECKREG r0, 0x9AA64ABD;
	CHECKREG r1, 0x23F08194;
	CHECKREG r2, 0xB114A649;
	CHECKREG r3, 0x1EA35F9A;
	CHECKREG r4, 0xEFBCDB69;
	CHECKREG r5, 0xF157B476;
	CHECKREG r6, 0x000C0D1B;
	CHECKREG r7, 0x678E0D01;
	CHECKREG p1, 0xF157B476;
	CHECKREG p2, 0xFC24C949;
	CHECKREG p3, 0x1EA35F9A;
	CHECKREG p4, 0x23F08194;

	imm32 r0, 0xd136459d;
	imm32 r1, 0xabd69ec7;
	imm32 r2, 0x71145679;
	imm32 r3, 0xdd010007;
	imm32 r4, 0xeddc1569;
	imm32 r5, 0x122d010b;
	imm32 r6, 0x00e3d01d;
	imm32 r7, 0x678e0d61;
	R5 = A1 , A0 -= R1.L * R0.L (IS);
	P1 = A1.w;
	R7 = A1 , A0 = R2.H * R3.L (IS);
	P2 = A1.w;
	R1 = A1 , A0 += R4.H * R5.H (IS);
	P3 = A1.w;
	R5 = A1 , A0 += R6.L * R7.H (IS);
	P4 = A1.w;
	CHECKREG r0, 0xD136459D;
	CHECKREG r1, 0x23F08194;
	CHECKREG r2, 0x71145679;
	CHECKREG r3, 0xDD010007;
	CHECKREG r4, 0xEDDC1569;
	CHECKREG r5, 0x23F08194;
	CHECKREG r6, 0x00E3D01D;
	CHECKREG r7, 0x23F08194;
	CHECKREG p1, 0x23F08194;
	CHECKREG p2, 0x23F08194;
	CHECKREG p3, 0x23F08194;
	CHECKREG p4, 0x23F08194;

	imm32 r0, 0x125489bd;
	imm32 r1, 0x91b5fec7;
	imm32 r2, 0xa9145679;
	imm32 r3, 0xd0910507;
	imm32 r4, 0x34567859;
	imm32 r5, 0xd2359105;
	imm32 r6, 0x0d0c0999;
	imm32 r7, 0x67de0009;
	R1 = ( A1 += R5.H * R3.H ) (M,IS);
	P1 = A1.w;
	R3 = ( A1 = R2.H * R1.H ) (M,IS);
	P2 = A1.w;
	R5 = ( A1 -= R7.H * R0.H ) (M,IS);
	P3 = A1.w;
	R7 = ( A1 += R4.H * R6.H ) (M,IS);
	P4 = A1.w;
	CHECKREG r0, 0x125489BD;
	CHECKREG r1, 0xFEA1A199;
	CHECKREG r2, 0xA9145679;
	CHECKREG r3, 0xA98B2D94;
	CHECKREG r4, 0x34567859;
	CHECKREG r5, 0xA21B7CBC;
	CHECKREG r6, 0x0D0C0999;
	CHECKREG r7, 0xA4C64EC4;
	CHECKREG p1, 0xFEA1A199;
	CHECKREG p2, 0xA98B2D94;
	CHECKREG p3, 0xA21B7CBC;
	CHECKREG p4, 0xA4C64EC4;

	pass