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c_dsp32mult_dr_is.s

c_dsp32mult_dr_is.s 6.1 KB
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  1. //Original:/testcases/core/c_dsp32mult_dr_is/c_dsp32mult_dr_is.dsp
    2. 

  2. // Spec Reference: dsp32mult single dr is
    3. 

  3. # mach: bfin
    4. 

  4. 

  5. .include "testutils.inc"
    6. 

  6. 	start
    7. 

  7. 

  8. imm32 r0, 0x8b235625;
    9. 

  9. imm32 r1, 0x98ba5127;
    10. 

  10. imm32 r2, 0xa3846725;
    11. 

  11. imm32 r3, 0x00080027;
    12. 

  12. imm32 r4, 0xb0ab8d29;
    13. 

  13. imm32 r5, 0x10ace82b;
    14. 

  14. imm32 r6, 0xc00c008d;
    15. 

  15. imm32 r7, 0xd2467028;
    16. 

  16. R4.H = R0.L * R0.L, R4.L = R0.L * R0.L (ISS2);
    17. 

  17. R5.H = R0.L * R1.L, R5.L = R0.L * R1.H (ISS2);
    18. 

  18. R6.H = R1.L * R0.L, R6.L = R1.H * R0.L (ISS2);
    19. 

  19. R7.H = R1.L * R1.L, R7.L = R1.H * R1.H (ISS2);
    20. 

  20. R0.H = R0.L * R0.L, R0.L = R0.L * R0.L (ISS2);
    21. 

  21. R1.H = R0.L * R1.L, R1.L = R0.L * R1.H (ISS2);
    22. 

  22. R2.H = R1.L * R0.L, R2.L = R1.H * R0.L (ISS2);
    23. 

  23. R3.H = R1.L * R1.L, R3.L = R1.H * R1.H (ISS2);
    24. 

  24. CHECKREG r0, 0x7FFF7FFF;
    25. 

  25. CHECKREG r1, 0x7FFF8000;
    26. 

  26. CHECKREG r2, 0x80007FFF;
    27. 

  27. CHECKREG r3, 0x7FFF7FFF;
    28. 

  28. CHECKREG r4, 0x7FFF7FFF;
    29. 

  29. CHECKREG r5, 0x7FFF8000;
    30. 

  30. CHECKREG r6, 0x7FFF8000;
    31. 

  31. CHECKREG r7, 0x7FFF7FFF;
    32. 

  32. 

  33. imm32 r0, 0x9923a635;
    34. 

  34. imm32 r1, 0x6f995137;
    35. 

  35. imm32 r2, 0x1324b735;
    36. 

  36. imm32 r3, 0x99060037;
    37. 

  37. imm32 r4, 0x809bcd39;
    38. 

  38. imm32 r5, 0xb0a99f3b;
    39. 

  39. imm32 r6, 0xa00c093d;
    40. 

  40. imm32 r7, 0x12467093;
    41. 

  41. R4.H = R2.L * R2.H, R4.L = R2.H * R2.L (ISS2);
    42. 

  42. R5.H = R2.L * R3.H, R5.L = R2.H * R3.H (ISS2);
    43. 

  43. R6.H = R3.L * R2.L, R6.L = R3.L * R2.H (ISS2);
    44. 

  44. R7.H = R3.L * R3.H, R7.L = R3.L * R3.H (ISS2);
    45. 

  45. R2.H = R2.L * R2.H, R2.L = R2.H * R2.L (ISS2);
    46. 

  46. R3.H = R2.L * R3.H, R3.L = R2.H * R3.H (ISS2);
    47. 

  47. R0.H = R3.L * R2.H, R0.L = R3.L * R2.L (ISS2);
    48. 

  48. R1.H = R3.L * R3.H, R1.L = R3.L * R3.H (ISS2);
    49. 

  49. CHECKREG r0, 0x80008000;
    50. 

  50. CHECKREG r1, 0x7FFF7FFF;
    51. 

  51. CHECKREG r2, 0x80008000;
    52. 

  52. CHECKREG r3, 0x7FFF7FFF;
    53. 

  53. CHECKREG r4, 0x80008000;
    54. 

  54. CHECKREG r5, 0x7FFF8000;
    55. 

  55. CHECKREG r6, 0x80007FFF;
    56. 

  56. CHECKREG r7, 0x80008000;
    57. 

  57. 

  58. imm32 r0, 0x19235655;
    59. 

  59. imm32 r1, 0xc9ba5157;
    60. 

  60. imm32 r2, 0x63246755;
    61. 

  61. imm32 r3, 0x0a060055;
    62. 

  62. imm32 r4, 0x90abc509;
    63. 

  63. imm32 r5, 0x10acef5b;
    64. 

  64. imm32 r6, 0xb00a005d;
    65. 

  65. imm32 r7, 0x1246a05f;
    66. 

  66. R0.H = R4.H * R4.L, R0.L = R4.L * R4.L (ISS2);
    67. 

  67. R1.H = R4.H * R5.L, R1.L = R4.L * R5.H (ISS2);
    68. 

  68. R2.H = R5.H * R4.L, R2.L = R5.H * R4.L (ISS2);
    69. 

  69. R3.H = R5.L * R5.L, R3.L = R5.H * R5.H (ISS2);
    70. 

  70. R4.H = R4.H * R4.L, R4.L = R4.L * R4.L (ISS2);
    71. 

  71. R5.H = R4.H * R5.L, R5.L = R4.L * R5.L (ISS2);
    72. 

  72. R6.H = R5.L * R4.L, R6.L = R5.H * R4.L (ISS2);
    73. 

  73. R7.H = R5.H * R5.L, R7.L = R5.H * R5.H (ISS2);
    74. 

  74. CHECKREG r0, 0x7FFF7FFF;
    75. 

  75. CHECKREG r1, 0x7FFF8000;
    76. 

  76. CHECKREG r2, 0x80008000;
    77. 

  77. CHECKREG r3, 0x7FFF7FFF;
    78. 

  78. CHECKREG r4, 0x7FFF7FFF;
    79. 

  79. CHECKREG r5, 0x80008000;
    80. 

  80. CHECKREG r6, 0x80008000;
    81. 

  81. CHECKREG r7, 0x7FFF7FFF;
    82. 

  82. 

  83. imm32 r0, 0xbb235666;
    84. 

  84. imm32 r1, 0xefba5166;
    85. 

  85. imm32 r2, 0x13248766;
    86. 

  86. imm32 r3, 0xe0060066;
    87. 

  87. imm32 r4, 0x9eab9d69;
    88. 

  88. imm32 r5, 0x10ecef6b;
    89. 

  89. imm32 r6, 0x800ee06d;
    90. 

  90. imm32 r7, 0x12467e6f;
    91. 

  91. // test the unsigned U=1
    92. 

  92. R0.H = R6.H * R6.H, R0.L = R6.L * R6.L (ISS2);
    93. 

  93. R1.H = R6.H * R7.H, R1.L = R6.L * R7.H (ISS2);
    94. 

  94. R2.H = R7.H * R6.H, R2.L = R7.H * R6.L (ISS2);
    95. 

  95. R3.H = R7.H * R7.H, R3.L = R7.H * R7.H (ISS2);
    96. 

  96. R6.H = R6.H * R6.H, R6.L = R6.L * R6.L (ISS2);
    97. 

  97. R7.H = R6.H * R7.H, R7.L = R6.L * R7.H (ISS2);
    98. 

  98. R4.H = R7.H * R6.H, R4.L = R7.H * R6.L (ISS2);
    99. 

  99. R5.H = R7.H * R7.H, R5.L = R7.H * R7.H (ISS2);
    100. 

  100. CHECKREG r0, 0x7FFF7FFF;
    101. 

  101. CHECKREG r1, 0x80008000;
    102. 

  102. CHECKREG r2, 0x80008000;
    103. 

  103. CHECKREG r3, 0x7FFF7FFF;
    104. 

  104. CHECKREG r4, 0x7FFF7FFF;
    105. 

  105. CHECKREG r5, 0x7FFF7FFF;
    106. 

  106. CHECKREG r6, 0x7FFF7FFF;
    107. 

  107. CHECKREG r7, 0x7FFF7FFF;
    108. 

  108. 

  109. // mix order
    110. 

  110. imm32 r0, 0xac23a675;
    111. 

  111. imm32 r1, 0xcfba5127;
    112. 

  112. imm32 r2, 0x13c46705;
    113. 

  113. imm32 r3, 0x00060007;
    114. 

  114. imm32 r4, 0x90accd09;
    115. 

  115. imm32 r5, 0x10acdfdb;
    116. 

  116. imm32 r6, 0x000cc00d;
    117. 

  117. imm32 r7, 0x1246fc0f;
    118. 

  118. R0.H = R0.L * R7.L, R0.L = R0.H * R7.H (ISS2);
    119. 

  119. R1.H = R1.L * R6.L, R1.L = R1.L * R6.H (ISS2);
    120. 

  120. R2.H = R2.H * R5.L, R2.L = R2.H * R5.L (ISS2);
    121. 

  121. R3.H = R3.L * R4.L, R3.L = R3.L * R4.L (ISS2);
    122. 

  122. R4.H = R4.L * R3.L, R4.L = R4.L * R3.L (ISS2);
    123. 

  123. R5.H = R5.H * R2.L, R5.L = R5.H * R2.L (ISS2);
    124. 

  124. R6.H = R6.L * R1.L, R6.L = R6.L * R1.L (ISS2);
    125. 

  125. R7.H = R7.H * R0.L, R7.L = R7.H * R0.H (ISS2);
    126. 

  126. CHECKREG r0, 0x7FFF8000;
    127. 

  127. CHECKREG r1, 0x80007FFF;
    128. 

  128. CHECKREG r2, 0x80008000;
    129. 

  129. CHECKREG r3, 0x80008000;
    130. 

  130. CHECKREG r4, 0x7FFF7FFF;
    131. 

  131. CHECKREG r5, 0x80008000;
    132. 

  132. CHECKREG r6, 0x80008000;
    133. 

  133. CHECKREG r7, 0x80007FFF;
    134. 

  134. 

  135. imm32 r0, 0xab235a75;
    136. 

  136. imm32 r1, 0xcfba5127;
    137. 

  137. imm32 r2, 0xdd246905;
    138. 

  138. imm32 r3, 0x00d6d007;
    139. 

  139. imm32 r4, 0x90abcd09;
    140. 

  140. imm32 r5, 0x10aceddb;
    141. 

  141. imm32 r6, 0x000c0d0d;
    142. 

  142. imm32 r7, 0x1246700f;
    143. 

  143. R0.H = R7.H * R0.H, R0.L = R7.H * R0.L (ISS2);
    144. 

  144. R1.H = R6.H * R1.H, R1.L = R6.L * R1.L (ISS2);
    145. 

  145. R2.H = R5.H * R2.H, R2.L = R5.H * R2.L (ISS2);
    146. 

  146. R3.H = R4.H * R3.H, R3.L = R4.H * R3.L (ISS2);
    147. 

  147. R4.H = R3.H * R4.H, R4.L = R3.H * R4.L (ISS2);
    148. 

  148. R5.H = R2.H * R5.H, R5.L = R2.H * R5.L (ISS2);
    149. 

  149. R6.H = R1.H * R6.H, R6.L = R1.H * R6.L (ISS2);
    150. 

  150. R7.H = R0.L * R7.H, R7.L = R0.H * R7.H (ISS2);
    151. 

  151. CHECKREG r0, 0x80007FFF;
    152. 

  152. CHECKREG r1, 0x80007FFF;
    153. 

  153. CHECKREG r2, 0x80007FFF;
    154. 

  154. CHECKREG r3, 0x80007FFF;
    155. 

  155. CHECKREG r4, 0x7FFF7FFF;
    156. 

  156. CHECKREG r5, 0x80007FFF;
    157. 

  157. CHECKREG r6, 0x80008000;
    158. 

  158. CHECKREG r7, 0x7FFF8000;
    159. 

  159. 

  160. imm32 r0, 0xfb235675;
    161. 

  161. imm32 r1, 0xcfba5127;
    162. 

  162. imm32 r2, 0x13f46705;
    163. 

  163. imm32 r3, 0x000f0007;
    164. 

  164. imm32 r4, 0x90abfd09;
    165. 

  165. imm32 r5, 0x10acefdb;
    166. 

  166. imm32 r6, 0x000c00fd;
    167. 

  167. imm32 r7, 0x1246700f;
    168. 

  168. R2.H = R0.L * R6.L, R2.L = R0.L * R6.H (ISS2);
    169. 

  169. R3.H = R1.H * R7.H, R3.L = R1.H * R7.L (ISS2);
    170. 

  170. R0.H = R2.L * R0.L, R0.L = R2.H * R0.H (ISS2);
    171. 

  171. R1.H = R3.L * R1.L, R1.L = R3.H * R1.H (ISS2);
    172. 

  172. R4.H = R4.L * R2.L, R4.L = R4.H * R2.H (ISS2);
    173. 

  173. R5.H = R5.L * R3.H, R5.L = R5.H * R3.L (ISS2);
    174. 

  174. R6.H = R6.H * R4.L, R6.L = R6.L * R4.H (ISS2);
    175. 

  175. R7.H = R7.L * R5.L, R7.L = R7.H * R5.H (ISS2);
    176. 

  176. CHECKREG r0, 0x7FFF8000;
    177. 

  177. CHECKREG r1, 0x80007FFF;
    178. 

  178. CHECKREG r2, 0x7FFF7FFF;
    179. 

  179. CHECKREG r3, 0x80008000;
    180. 

  180. CHECKREG r4, 0x80008000;
    181. 

  181. CHECKREG r5, 0x7FFF8000;
    182. 

  182. CHECKREG r6, 0x80008000;
    183. 

  183. CHECKREG r7, 0x80007FFF;
    184. 

  184. 

  185. imm32 r0, 0xab2d5675;
    186. 

  186. imm32 r1, 0xcfbad127;
    187. 

  187. imm32 r2, 0x13246d05;
    188. 

  188. imm32 r3, 0x000600d7;
    189. 

  189. imm32 r4, 0x908bcd09;
    190. 

  190. imm32 r5, 0x10a9efdb;
    191. 

  191. imm32 r6, 0x000c500d;
    192. 

  192. imm32 r7, 0x1246760f;
    193. 

  193. R4.H = R5.L * R2.L, R4.L = R5.L * R2.H (ISS2);
    194. 

  194. R6.H = R6.H * R3.L, R6.L = R6.L * R3.H (ISS2);
    195. 

  195. R0.H = R7.L * R4.L, R0.L = R7.L * R4.H (ISS2);
    196. 

  196. R1.H = R0.L * R5.H, R1.L = R0.L * R5.L (ISS2);
    197. 

  197. R2.H = R1.L * R6.L, R2.L = R1.L * R6.H (ISS2);
    198. 

  198. R5.H = R2.L * R7.H, R5.L = R2.H * R7.L (ISS2);
    199. 

  199. R3.H = R3.L * R0.L, R3.L = R3.L * R0.H (ISS2);
    200. 

  200. R7.H = R4.H * R1.L, R7.L = R4.L * R1.H (ISS2);
    201. 

  201. CHECKREG r0, 0x80008000;
    202. 

  202. CHECKREG r1, 0x80007FFF;
    203. 

  203. CHECKREG r2, 0x7FFF7FFF;
    204. 

  204. CHECKREG r3, 0x80008000;
    205. 

  205. CHECKREG r4, 0x80008000;
    206. 

  206. CHECKREG r5, 0x7FFF7FFF;
    207. 

  207. CHECKREG r6, 0x14287FFF;
    208. 

  208. CHECKREG r7, 0x80007FFF;
    209. 

  209. 

  210. 

  211. 

  212. pass
    213.