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c_dsp32shift_signbits_rh.s

c_dsp32shift_signbits_rh.s 4.5 KB
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  1. //Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp
    2. 

  2. // Spec Reference: dsp32shift signbits dregs_hi
    3. 

  3. # mach: bfin
    4. 

  4. 

  5. .include "testutils.inc"
    6. 

  6. 	start
    7. 

  7. 

  8. 

  9. 

  10. 

  11. imm32 r0, 0xd1000000;
    12. 

  12. imm32 r1, 0xd2000001;
    13. 

  13. imm32 r2, 0xd3000002;
    14. 

  14. imm32 r3, 0xd4000003;
    15. 

  15. imm32 r4, 0xd5000004;
    16. 

  16. imm32 r5, 0xd6000005;
    17. 

  17. imm32 r6, 0xd7000006;
    18. 

  18. imm32 r7, 0xd8000007;
    19. 

  19. R0.L = SIGNBITS R0.H;
    20. 

  20. R1.L = SIGNBITS R0.H;
    21. 

  21. R2.L = SIGNBITS R0.H;
    22. 

  22. R3.L = SIGNBITS R0.H;
    23. 

  23. R4.L = SIGNBITS R0.H;
    24. 

  24. R5.L = SIGNBITS R0.H;
    25. 

  25. R6.L = SIGNBITS R0.H;
    26. 

  26. R7.L = SIGNBITS R0.H;
    27. 

  27. CHECKREG r0, 0xD1000001;
    28. 

  28. CHECKREG r1, 0xD2000001;
    29. 

  29. CHECKREG r2, 0xD3000001;
    30. 

  30. CHECKREG r3, 0xD4000001;
    31. 

  31. CHECKREG r4, 0xD5000001;
    32. 

  32. CHECKREG r5, 0xD6000001;
    33. 

  33. CHECKREG r6, 0xD7000001;
    34. 

  34. CHECKREG r7, 0xD8000001;
    35. 

  35. 

  36. imm32 r0, 0xe200d001;
    37. 

  37. imm32 r1, 0xe2000001;
    38. 

  38. imm32 r2, 0xe200d002;
    39. 

  39. imm32 r3, 0xe200d003;
    40. 

  40. imm32 r4, 0xe200d004;
    41. 

  41. imm32 r5, 0xe200d005;
    42. 

  42. imm32 r6, 0xe200d006;
    43. 

  43. imm32 r7, 0xe200d007;
    44. 

  44. R0.L = SIGNBITS R1.H;
    45. 

  45. R1.L = SIGNBITS R1.H;
    46. 

  46. R2.L = SIGNBITS R1.H;
    47. 

  47. R3.L = SIGNBITS R1.H;
    48. 

  48. R4.L = SIGNBITS R1.H;
    49. 

  49. R5.L = SIGNBITS R1.H;
    50. 

  50. R6.L = SIGNBITS R1.H;
    51. 

  51. R7.L = SIGNBITS R1.H;
    52. 

  52. CHECKREG r0, 0xE2000002;
    53. 

  53. CHECKREG r1, 0xE2000002;
    54. 

  54. CHECKREG r2, 0xE2000002;
    55. 

  55. CHECKREG r3, 0xE2000002;
    56. 

  56. CHECKREG r4, 0xE2000002;
    57. 

  57. CHECKREG r5, 0xE2000002;
    58. 

  58. CHECKREG r6, 0xE2000002;
    59. 

  59. CHECKREG r7, 0xE2000002;
    60. 

  60. 

  61. 

  62. imm32 r0, 0x0000e001;
    63. 

  63. imm32 r1, 0x0000e001;
    64. 

  64. imm32 r2, 0xf000000f;
    65. 

  65. imm32 r3, 0x0000e003;
    66. 

  66. imm32 r4, 0x0000e004;
    67. 

  67. imm32 r5, 0x0000e005;
    68. 

  68. imm32 r6, 0x0000e006;
    69. 

  69. imm32 r7, 0x0000e007;
    70. 

  70. R0.L = SIGNBITS R2.H;
    71. 

  71. R1.L = SIGNBITS R2.H;
    72. 

  72. R2.L = SIGNBITS R2.H;
    73. 

  73. R3.L = SIGNBITS R2.H;
    74. 

  74. R4.L = SIGNBITS R2.H;
    75. 

  75. R5.L = SIGNBITS R2.H;
    76. 

  76. R6.L = SIGNBITS R2.H;
    77. 

  77. R7.L = SIGNBITS R2.H;
    78. 

  78. CHECKREG r0, 0x00000003;
    79. 

  79. CHECKREG r1, 0x00000003;
    80. 

  80. CHECKREG r2, 0xF0000003;
    81. 

  81. CHECKREG r3, 0x00000003;
    82. 

  82. CHECKREG r4, 0x00000003;
    83. 

  83. CHECKREG r5, 0x00000003;
    84. 

  84. CHECKREG r6, 0x00000003;
    85. 

  85. CHECKREG r7, 0x00000003;
    86. 

  86. 

  87. imm32 r0, 0x0100f001;
    88. 

  88. imm32 r1, 0x0100f001;
    89. 

  89. imm32 r2, 0x0100f002;
    90. 

  90. imm32 r3, 0x01000010;
    91. 

  91. imm32 r4, 0x0100f004;
    92. 

  92. imm32 r5, 0x0100f005;
    93. 

  93. imm32 r6, 0x0100f006;
    94. 

  94. imm32 r7, 0x0100f007;
    95. 

  95. R0.L = SIGNBITS R3.H;
    96. 

  96. R1.L = SIGNBITS R3.H;
    97. 

  97. R2.L = SIGNBITS R3.H;
    98. 

  98. R3.L = SIGNBITS R3.H;
    99. 

  99. R4.L = SIGNBITS R3.H;
    100. 

  100. R5.L = SIGNBITS R3.H;
    101. 

  101. R6.L = SIGNBITS R3.H;
    102. 

  102. R7.L = SIGNBITS R3.H;
    103. 

  103. CHECKREG r0, 0x01000006;
    104. 

  104. CHECKREG r1, 0x01000006;
    105. 

  105. CHECKREG r2, 0x01000006;
    106. 

  106. CHECKREG r3, 0x01000006;
    107. 

  107. CHECKREG r4, 0x01000006;
    108. 

  108. CHECKREG r5, 0x01000006;
    109. 

  109. CHECKREG r6, 0x01000006;
    110. 

  110. CHECKREG r7, 0x01000006;
    111. 

  111. 

  112. imm32 r0, 0x04000000;
    113. 

  113. imm32 r1, 0x04010000;
    114. 

  114. imm32 r2, 0x04020000;
    115. 

  115. imm32 r3, 0x04030000;
    116. 

  116. imm32 r4, 0x04040000;
    117. 

  117. imm32 r5, 0x04050000;
    118. 

  118. imm32 r6, 0x04060000;
    119. 

  119. imm32 r7, 0x04070000;
    120. 

  120. R0.L = SIGNBITS R4.H;
    121. 

  121. R1.L = SIGNBITS R4.H;
    122. 

  122. R2.L = SIGNBITS R4.H;
    123. 

  123. R3.L = SIGNBITS R4.H;
    124. 

  124. R4.L = SIGNBITS R4.H;
    125. 

  125. R5.L = SIGNBITS R4.H;
    126. 

  126. R6.L = SIGNBITS R4.H;
    127. 

  127. R7.L = SIGNBITS R4.H;
    128. 

  128. CHECKREG r0, 0x04000004;
    129. 

  129. CHECKREG r1, 0x04010004;
    130. 

  130. CHECKREG r2, 0x04020004;
    131. 

  131. CHECKREG r3, 0x04030004;
    132. 

  132. CHECKREG r4, 0x04040004;
    133. 

  133. CHECKREG r5, 0x04050004;
    134. 

  134. CHECKREG r6, 0x04060004;
    135. 

  135. CHECKREG r7, 0x04070004;
    136. 

  136. 

  137. imm32 r0, 0xa5010000;
    138. 

  138. imm32 r1, 0xa5010001;
    139. 

  139. imm32 r2, 0xa5020000;
    140. 

  140. imm32 r3, 0xa5030000;
    141. 

  141. imm32 r4, 0xa5540000;
    142. 

  142. imm32 r5, 0xa5550000;
    143. 

  143. imm32 r6, 0xa5060000;
    144. 

  144. imm32 r7, 0xa5070000;
    145. 

  145. R0.L = SIGNBITS R5.H;
    146. 

  146. R1.L = SIGNBITS R5.H;
    147. 

  147. R2.L = SIGNBITS R5.H;
    148. 

  148. R3.L = SIGNBITS R5.H;
    149. 

  149. R4.L = SIGNBITS R5.H;
    150. 

  150. R5.L = SIGNBITS R5.H;
    151. 

  151. R6.L = SIGNBITS R5.H;
    152. 

  152. R7.L = SIGNBITS R5.H;
    153. 

  153. CHECKREG r0, 0xA5010000;
    154. 

  154. CHECKREG r1, 0xA5010000;
    155. 

  155. CHECKREG r2, 0xA5020000;
    156. 

  156. CHECKREG r3, 0xA5030000;
    157. 

  157. CHECKREG r4, 0xA5540000;
    158. 

  158. CHECKREG r5, 0xA5550000;
    159. 

  159. CHECKREG r6, 0xA5060000;
    160. 

  160. CHECKREG r7, 0xA5070000;
    161. 

  161. 

  162. 

  163. imm32 r0, 0xb6010000;
    164. 

  164. imm32 r1, 0xb6010000;
    165. 

  165. imm32 r2, 0xb602000f;
    166. 

  166. imm32 r3, 0xb6030000;
    167. 

  167. imm32 r4, 0xb6040000;
    168. 

  168. imm32 r5, 0xb6050000;
    169. 

  169. imm32 r6, 0xb6060000;
    170. 

  170. imm32 r7, 0xb6670000;
    171. 

  171. R0.L = SIGNBITS R6.H;
    172. 

  172. R1.L = SIGNBITS R6.H;
    173. 

  173. R2.L = SIGNBITS R6.H;
    174. 

  174. R3.L = SIGNBITS R6.H;
    175. 

  175. R4.L = SIGNBITS R6.H;
    176. 

  176. R5.L = SIGNBITS R6.H;
    177. 

  177. R6.L = SIGNBITS R6.H;
    178. 

  178. R7.L = SIGNBITS R6.H;
    179. 

  179. CHECKREG r0, 0xB6010000;
    180. 

  180. CHECKREG r1, 0xB6010000;
    181. 

  181. CHECKREG r2, 0xB6020000;
    182. 

  182. CHECKREG r3, 0xB6030000;
    183. 

  183. CHECKREG r4, 0xB6040000;
    184. 

  184. CHECKREG r5, 0xB6050000;
    185. 

  185. CHECKREG r6, 0xB6060000;
    186. 

  186. CHECKREG r7, 0xB6670000;
    187. 

  187. 

  188. imm32 r0, 0xd7010000;
    189. 

  189. imm32 r1, 0xd7010000;
    190. 

  190. imm32 r2, 0xd7020000;
    191. 

  191. imm32 r3, 0xd7030010;
    192. 

  192. imm32 r4, 0xd7040000;
    193. 

  193. imm32 r5, 0xd7050000;
    194. 

  194. imm32 r6, 0xd7060000;
    195. 

  195. imm32 r7, 0xd7070000;
    196. 

  196. R0.L = SIGNBITS R7.H;
    197. 

  197. R1.L = SIGNBITS R7.H;
    198. 

  198. R2.L = SIGNBITS R7.H;
    199. 

  199. R3.L = SIGNBITS R7.H;
    200. 

  200. R4.L = SIGNBITS R7.H;
    201. 

  201. R5.L = SIGNBITS R7.H;
    202. 

  202. R6.L = SIGNBITS R7.H;
    203. 

  203. R7.L = SIGNBITS R7.H;
    204. 

  204. CHECKREG r0, 0xD7010001;
    205. 

  205. CHECKREG r1, 0xD7010001;
    206. 

  206. CHECKREG r2, 0xD7020001;
    207. 

  207. CHECKREG r3, 0xD7030001;
    208. 

  208. CHECKREG r4, 0xD7040001;
    209. 

  209. CHECKREG r5, 0xD7050001;
    210. 

  210. CHECKREG r6, 0xD7060001;
    211. 

  211. CHECKREG r7, 0xD7070001;
    212. 

  212. 

  213. 

  214. pass
    215.