c_dsp32shiftim_rot.s 1.3 KB

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  1. //Original:/proj/frio/dv/testcases/core/c_dsp32shiftim_rot/c_dsp32shiftim_rot.dsp
  2. // Spec Reference: dsp32shiftimm rot:
  3. # mach: bfin
  4. .include "testutils.inc"
  5. start
  6. R0 = 0;
  7. ASTAT = R0;
  8. imm32 r0, 0xa1230001;
  9. imm32 r1, 0x1b345678;
  10. imm32 r2, 0x23c56789;
  11. imm32 r3, 0x34d6789a;
  12. imm32 r4, 0x85a789ab;
  13. imm32 r5, 0x967c9abc;
  14. imm32 r6, 0xa789abcd;
  15. imm32 r7, 0xb8912cde;
  16. R0 = ROT R0 BY 1;
  17. R1 = ROT R1 BY 5;
  18. R2 = ROT R2 BY 9;
  19. R3 = ROT R3 BY 8;
  20. R4 = ROT R4 BY 24;
  21. R5 = ROT R5 BY 31;
  22. R6 = ROT R6 BY 14;
  23. R7 = ROT R7 BY 25;
  24. CHECKREG r0, 0x42460002;
  25. CHECKREG r1, 0x668ACF11;
  26. CHECKREG r2, 0x8ACF1323;
  27. CHECKREG r3, 0xD6789A9A;
  28. CHECKREG r4, 0xAB42D3C4;
  29. CHECKREG r5, 0x659F26AF;
  30. CHECKREG r6, 0x6AF354F1;
  31. CHECKREG r7, 0xBCB8912C;
  32. imm32 r0, 0xa1230001;
  33. imm32 r1, 0x1b345678;
  34. imm32 r2, 0x23c56789;
  35. imm32 r3, 0x34d6789a;
  36. imm32 r4, 0x85a789ab;
  37. imm32 r5, 0x967c9abc;
  38. imm32 r6, 0xa789abcd;
  39. imm32 r7, 0xb8912cde;
  40. R6 = ROT R0 BY -3;
  41. R7 = ROT R1 BY -9;
  42. R0 = ROT R2 BY -8;
  43. R1 = ROT R3 BY -7;
  44. R2 = ROT R4 BY -15;
  45. R3 = ROT R5 BY -24;
  46. R4 = ROT R6 BY -31;
  47. R5 = ROT R7 BY -22;
  48. CHECKREG r0, 0x1223C567;
  49. CHECKREG r1, 0x6A69ACF1;
  50. CHECKREG r2, 0x26AD0B4F;
  51. CHECKREG r3, 0xF9357896;
  52. CHECKREG r4, 0xD0918000;
  53. CHECKREG r5, 0x6CD15DE0;
  54. CHECKREG r6, 0x74246000;
  55. CHECKREG r7, 0x780D9A2B;
  56. pass