binutils-gdb/sim/testsuite/bfin/c_logi2op_log_l_shft.s

//Original:/testcases/core/c_logi2op_log_l_shft/c_logi2op_log_l_shft.dsp
// Spec Reference: Logi2op <<=
# mach: bfin

.include "testutils.inc"
	start




// Logical <<= : negative data
// bit 0-7
imm32 r0, 0x81111111;
imm32 r1, 0x81111111;
imm32 r2, 0x81111111;
imm32 r3, 0x81111111;
imm32 r4, 0x81111111;
imm32 r5, 0x81111111;
imm32 r6, 0x81111111;
imm32 r7, 0x81111111;
R0 <<= 0; /* r0 = 0x81111111 */
R1 <<= 1; /* r1 = 0x40888888 */
R2 <<= 2; /* r2 = 0x20444444 */
R3 <<= 3; /* r3 = 0x10222222 */
R4 <<= 4; /* r4 = 0x08111111 */
R5 <<= 5; /* r5 = 0x04088888 */
R6 <<= 6; /* r6 = 0x02044444 */
R7 <<= 7; /* r7 = 0x01022222 */
CHECKREG r0, 0x81111111;
CHECKREG r1, 0x02222222;
CHECKREG r2, 0x04444444;
CHECKREG r3, 0x08888888;
CHECKREG r4, 0x11111110;
CHECKREG r5, 0x22222220;
CHECKREG r6, 0x44444440;
CHECKREG r7, 0x88888880;

// bit 8-15
imm32 r0, 0x82222222;
imm32 r1, 0x82222222;
imm32 r2, 0x82222222;
imm32 r3, 0x82222222;
imm32 r4, 0x82222222;
imm32 r5, 0x82222222;
imm32 r6, 0x82222222;
imm32 r7, 0x82222222;
R0 <<= 8;
R1 <<= 9;
R2 <<= 10;
R3 <<= 11;
R4 <<= 12;
R5 <<= 13;
R6 <<= 14;
R7 <<= 15;
CHECKREG r0, 0x22222200;
CHECKREG r1, 0x44444400;
CHECKREG r2, 0x88888800;
CHECKREG r3, 0x11111000;
CHECKREG r4, 0x22222000;
CHECKREG r5, 0x44444000;
CHECKREG r6, 0x88888000;
CHECKREG r7, 0x11110000;

// bit 16-23
imm32 r0, 0x83333333;
imm32 r1, 0x83333333;
imm32 r2, 0x83333333;
imm32 r3, 0x83333333;
imm32 r4, 0x83333333;
imm32 r5, 0x83333333;
imm32 r6, 0x83333333;
imm32 r7, 0x83333333;
R0 <<= 16;
R1 <<= 17;
R2 <<= 18;
R3 <<= 19;
R4 <<= 20;
R5 <<= 21;
R6 <<= 22;
R7 <<= 23;
CHECKREG r0, 0x33330000;
CHECKREG r1, 0x66660000;
CHECKREG r2, 0xCCCC0000;
CHECKREG r3, 0x99980000;
CHECKREG r4, 0x33300000;
CHECKREG r5, 0x66600000;
CHECKREG r6, 0xCCC00000;
CHECKREG r7, 0x99800000;

// bit 24-31
imm32 r0, 0x84444444;
imm32 r1, 0x84444444;
imm32 r2, 0x84444444;
imm32 r3, 0x84444444;
imm32 r4, 0x84444444;
imm32 r5, 0x84444444;
imm32 r6, 0x84444444;
imm32 r7, 0x84444444;
R0 <<= 24;
R1 <<= 25;
R2 <<= 26;
R3 <<= 27;
R4 <<= 28;
R5 <<= 29;
R6 <<= 30;
R7 <<= 31;
CHECKREG r0, 0x44000000;
CHECKREG r1, 0x88000000;
CHECKREG r2, 0x10000000;
CHECKREG r3, 0x20000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;

// Arithmetic <<= : positive data
// bit 0-7
imm32 r0, 0x41111111;
imm32 r1, 0x41111111;
imm32 r2, 0x41111111;
imm32 r3, 0x41111111;
imm32 r4, 0x41111111;
imm32 r5, 0x41111111;
imm32 r6, 0x41111111;
imm32 r7, 0x41111111;
R0 <<= 0;
R1 <<= 1;
R2 <<= 2;
R3 <<= 3;
R4 <<= 4;
R5 <<= 5;
R6 <<= 6;
R7 <<= 7;
CHECKREG r0, 0x41111111;
CHECKREG r1, 0x82222222;
CHECKREG r2, 0x04444444;
CHECKREG r3, 0x08888888;
CHECKREG r4, 0x11111110;
CHECKREG r5, 0x22222220;
CHECKREG r6, 0x44444440;
CHECKREG r7, 0x88888880;

// bit 8-15
imm32 r0, 0x42222222;
imm32 r1, 0x42222222;
imm32 r2, 0x42222222;
imm32 r3, 0x42222222;
imm32 r4, 0x42222222;
imm32 r5, 0x42222222;
imm32 r6, 0x42222222;
imm32 r7, 0x42222222;
R0 <<= 8;
R1 <<= 9;
R2 <<= 10;
R3 <<= 11;
R4 <<= 12;
R5 <<= 13;
R6 <<= 14;
R7 <<= 15;
CHECKREG r0, 0x22222200;
CHECKREG r1, 0x44444400;
CHECKREG r2, 0x88888800;
CHECKREG r3, 0x11111000;
CHECKREG r4, 0x22222000;
CHECKREG r5, 0x44444000;
CHECKREG r6, 0x88888000;
CHECKREG r7, 0x11110000;

// bit 16-23
imm32 r0, 0x43333333;
imm32 r1, 0x43333333;
imm32 r2, 0x43333333;
imm32 r3, 0x43333333;
imm32 r4, 0x43333333;
imm32 r5, 0x43333333;
imm32 r6, 0x43333333;
imm32 r7, 0x43333333;
R0 <<= 16;
R1 <<= 17;
R2 <<= 18;
R3 <<= 19;
R4 <<= 20;
R5 <<= 21;
R6 <<= 22;
R7 <<= 23;
CHECKREG r0, 0x33330000;
CHECKREG r1, 0x66660000;
CHECKREG r2, 0xCCCC0000;
CHECKREG r3, 0x99980000;
CHECKREG r4, 0x33300000;
CHECKREG r5, 0x66600000;
CHECKREG r6, 0xCCC00000;
CHECKREG r7, 0x99800000;

// bit 24-31
imm32 r0, 0x44444444;
imm32 r1, 0x44444444;
imm32 r2, 0x44444444;
imm32 r3, 0x44444444;
imm32 r4, 0x44444444;
imm32 r5, 0x44444444;
imm32 r6, 0x44444444;
imm32 r7, 0x44444444;
R0 <<= 24;
R1 <<= 25;
R2 <<= 26;
R3 <<= 27;
R4 <<= 28;
R5 <<= 29;
R6 <<= 30;
R7 <<= 31;
CHECKREG r0, 0x44000000;
CHECKREG r1, 0x88000000;
CHECKREG r2, 0x10000000;
CHECKREG r3, 0x20000000;
CHECKREG r4, 0x40000000;
CHECKREG r5, 0x80000000;
CHECKREG r6, 0x00000000;
CHECKREG r7, 0x00000000;


pass