c_seq_ex1_brcc_mv_pop.S 7.1 KB

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  1. //Original:/proj/frio/dv/testcases/core/c_seq_ex1_brcc_mv_pop/c_seq_ex1_brcc_mv_pop.dsp
  2. // Spec Reference: sequencer stage ex1 ( brcc + regmv + pushpopmultiple)
  3. # mach: bfin
  4. # sim: --environment operating
  5. #include "test.h"
  6. .include "testutils.inc"
  7. start
  8. include(std.inc)
  9. include(selfcheck.inc)
  10. include(gen_int.inc)
  11. INIT_R_REGS(0);
  12. INIT_P_REGS(0);
  13. INIT_I_REGS(0); // initialize the dsp address regs
  14. INIT_M_REGS(0);
  15. INIT_L_REGS(0);
  16. INIT_B_REGS(0);
  17. //CHECK_INIT(p5, 0xe0000000);
  18. include(symtable.inc)
  19. CHECK_INIT_DEF(p5);
  20. #ifndef STACKSIZE
  21. #define STACKSIZE 0x10
  22. #endif
  23. #ifndef EVT
  24. #define EVT 0xFFE02000
  25. #endif
  26. #ifndef EVT15
  27. #define EVT15 0xFFE0203C
  28. #endif
  29. #ifndef EVT_OVERRIDE
  30. #define EVT_OVERRIDE 0xFFE02100
  31. #endif
  32. #ifndef ITABLE
  33. #define ITABLE DATA_ADDR_1
  34. #endif
  35. GEN_INT_INIT(ITABLE) // set location for interrupt table
  36. //
  37. // Reset/Bootstrap Code
  38. // (Here we should set the processor operating modes, initialize registers,
  39. //
  40. BOOT:
  41. // in reset mode now
  42. LD32_LABEL(sp, KSTACK); // setup the stack pointer
  43. FP = SP; // and frame pointer
  44. LD32(p0, EVT); // Setup Event Vectors and Handlers
  45. LD32_LABEL(r0, EHANDLE); // Emulation Handler (Int0)
  46. [ P0 ++ ] = R0;
  47. LD32_LABEL(r0, RHANDLE); // Reset Handler (Int1)
  48. [ P0 ++ ] = R0;
  49. LD32_LABEL(r0, NHANDLE); // NMI Handler (Int2)
  50. [ P0 ++ ] = R0;
  51. LD32_LABEL(r0, XHANDLE); // Exception Handler (Int3)
  52. [ P0 ++ ] = R0;
  53. [ P0 ++ ] = R0; // IVT4 not used
  54. LD32_LABEL(r0, HWHANDLE); // HW Error Handler (Int5)
  55. [ P0 ++ ] = R0;
  56. LD32_LABEL(r0, THANDLE); // Timer Handler (Int6)
  57. [ P0 ++ ] = R0;
  58. LD32_LABEL(r0, I7HANDLE); // IVG7 Handler
  59. [ P0 ++ ] = R0;
  60. LD32_LABEL(r0, I8HANDLE); // IVG8 Handler
  61. [ P0 ++ ] = R0;
  62. LD32_LABEL(r0, I9HANDLE); // IVG9 Handler
  63. [ P0 ++ ] = R0;
  64. LD32_LABEL(r0, I10HANDLE);// IVG10 Handler
  65. [ P0 ++ ] = R0;
  66. LD32_LABEL(r0, I11HANDLE);// IVG11 Handler
  67. [ P0 ++ ] = R0;
  68. LD32_LABEL(r0, I12HANDLE);// IVG12 Handler
  69. [ P0 ++ ] = R0;
  70. LD32_LABEL(r0, I13HANDLE);// IVG13 Handler
  71. [ P0 ++ ] = R0;
  72. LD32_LABEL(r0, I14HANDLE);// IVG14 Handler
  73. [ P0 ++ ] = R0;
  74. LD32_LABEL(r0, I15HANDLE);// IVG15 Handler
  75. [ P0 ++ ] = R0;
  76. LD32(p0, EVT_OVERRIDE);
  77. R0 = 0;
  78. [ P0 ++ ] = R0;
  79. R0 = -1; // Change this to mask interrupts (*)
  80. [ P0 ] = R0; // IMASK
  81. CSYNC;
  82. DUMMY:
  83. R0 = 0 (Z);
  84. LT0 = r0; // set loop counters to something deterministic
  85. LB0 = r0;
  86. LC0 = r0;
  87. LT1 = r0;
  88. LB1 = r0;
  89. LC1 = r0;
  90. ASTAT = r0; // reset other internal regs
  91. // The following code sets up the test for running in USER mode
  92. LD32_LABEL(r0, STARTUSER);// One gets to user mode by doing a
  93. // ReturnFromInterrupt (RTI)
  94. RETI = r0; // We need to load the return address
  95. // Comment the following line for a USER Mode test
  96. JUMP STARTSUP; // jump to code start for SUPERVISOR mode
  97. RTI;
  98. STARTSUP:
  99. LD32_LABEL(p1, BEGIN);
  100. LD32(p0, EVT15);
  101. [ P0 ] = P1; // IVG15 (General) handler (Int 15) load with start
  102. RAISE 15; // after we RTI, INT 15 should be taken,& return to BEGIN in
  103. // SUPERVISOR MODE & go to different RAISE in supervisor mode
  104. // until the end of the test.
  105. NOP; // Workaround for Bug 217
  106. RTI;
  107. //
  108. // The Main Program
  109. //
  110. STARTUSER:
  111. LD32_LABEL(sp, USTACK); // setup the stack pointer
  112. FP = SP; // set frame pointer
  113. JUMP BEGIN;
  114. //*********************************************************************
  115. BEGIN:
  116. // COMMENT the following line for USER MODE tests
  117. [ -- SP ] = RETI; // enable interrupts in supervisor mode
  118. // **** YOUR CODE GOES HERE ****
  119. // PUT YOUR TEST HERE!
  120. R0 = 0;
  121. ASTAT = R0;
  122. R0 = 0x01;
  123. R1 = 0x02;
  124. R2 = 0x03;
  125. R3 = 0x04;
  126. R4 = 0x05;
  127. R5 = 0x06;
  128. R6 = 0x07;
  129. R7 = 0x08;
  130. LD32(p1, 0x12345678);
  131. LD32(p2, 0x05612496);
  132. LD32(p3, 0xab5fd490);
  133. LD32(p4, 0xa581bd94);
  134. [ -- SP ] = ( R7:0 );
  135. // RAISE 2; // RTN
  136. IF !CC JUMP LABEL1 (BP);
  137. P1 = R1;
  138. R2 = P1;
  139. [ -- SP ] = ( R7:0 );
  140. R1 = 0x12;
  141. R2 = 0x13;
  142. R3 = 0x14;
  143. R4 = 0x15;
  144. R5 = 0x16;
  145. R6 = 0x17;
  146. R7 = 0x18;
  147. LABEL1:
  148. // RAISE 5; // RTI
  149. P2 = R2;
  150. R3 = P2;
  151. [ -- SP ] = ( R7:0 );
  152. R2 = 0x23;
  153. R3 = 0x24;
  154. R4 = 0x25;
  155. R5 = 0x26;
  156. R6 = 0x27;
  157. R7 = 0x28;
  158. // RAISE 6; // RTI
  159. IF !CC JUMP LABEL2 (BP);
  160. P3 = R3;
  161. R4 = P3;
  162. [ -- SP ] = ( R7:0 );
  163. // POP
  164. R0 = 0x00;
  165. R1 = 0x00;
  166. R2 = 0x00;
  167. R3 = 0x00;
  168. R4 = 0x00;
  169. R5 = 0x00;
  170. R6 = 0x00;
  171. R7 = 0x00;
  172. LABEL2:
  173. // RAISE 7; // RTI
  174. IF CC JUMP LABEL4; // SHOULD NOT EXECUTE
  175. P4 = R4;
  176. R5 = P4;
  177. ( R7:0 ) = [ SP ++ ];
  178. LABEL4:
  179. CHECKREG(r0, 0x00000001);
  180. CHECKREG(r1, 0x00000002);
  181. CHECKREG(r2, 0x00000003);
  182. CHECKREG(r3, 0x00000003);
  183. CHECKREG(r4, 0x00000005);
  184. CHECKREG(r5, 0x00000006);
  185. CHECKREG(r6, 0x00000007);
  186. CHECKREG(r7, 0x00000008);
  187. // RAISE 8; // RTI
  188. IF !CC JUMP LABEL3 (BP);
  189. P1 = R5;
  190. R6 = P1;
  191. ( R7:0 ) = [ SP ++ ];
  192. //CHECKREG(r0, 0x000000a1); // CHECKREG can not be skipped
  193. //CHECKREG(r1, 0x000000b2); // so they cannot appear here
  194. //CHECKREG(r2, 0x000000c3);
  195. //CHECKREG(r3, 0x000000d4);
  196. //CHECKREG(r4, 0x000000e5);
  197. //CHECKREG(r5, 0x000000f6);
  198. //CHECKREG(r6, 0x00000017);
  199. //CHECKREG(r7, 0x00000028);
  200. R0 = 12;
  201. R1 = 13;
  202. R2 = 14;
  203. R3 = 15;
  204. R4 = 16;
  205. R5 = 17;
  206. R6 = 18;
  207. R7 = 19;
  208. LABEL3:
  209. // RAISE 9; // RTI
  210. P2 = R6;
  211. R7 = P2;
  212. ( R7:0 ) = [ SP ++ ];
  213. CHECKREG(r0, 0x00000001);
  214. CHECKREG(r1, 0x00000002);
  215. CHECKREG(r2, 0x00000003);
  216. CHECKREG(r3, 0x00000004);
  217. CHECKREG(r4, 0x00000005);
  218. CHECKREG(r5, 0x00000006);
  219. CHECKREG(r6, 0x00000007);
  220. CHECKREG(r7, 0x00000008);
  221. R0 = I0;
  222. R1 = I1;
  223. R2 = I2;
  224. R3 = I3;
  225. CHECKREG(r0, 0x00000000);
  226. CHECKREG(r1, 0x00000000);
  227. CHECKREG(r2, 0x00000000);
  228. CHECKREG(r3, 0x00000000);
  229. END:
  230. dbg_pass; // End the test
  231. //*********************************************************************
  232. //
  233. // Handlers for Events
  234. //
  235. EHANDLE: // Emulation Handler 0
  236. RTE;
  237. RHANDLE: // Reset Handler 1
  238. RTI;
  239. NHANDLE: // NMI Handler 2
  240. I0 += 2;
  241. RTN;
  242. XHANDLE: // Exception Handler 3
  243. R1 = 3;
  244. RTX;
  245. HWHANDLE: // HW Error Handler 5
  246. I1 += 2;
  247. RTI;
  248. THANDLE: // Timer Handler 6
  249. I2 += 2;
  250. RTI;
  251. I7HANDLE: // IVG 7 Handler
  252. I3 += 2;
  253. RTI;
  254. I8HANDLE: // IVG 8 Handler
  255. I0 += 2;
  256. RTI;
  257. I9HANDLE: // IVG 9 Handler
  258. I0 += 2;
  259. RTI;
  260. I10HANDLE: // IVG 10 Handler
  261. R7 = 10;
  262. RTI;
  263. I11HANDLE: // IVG 11 Handler
  264. I0 = R0;
  265. I1 = R1;
  266. I2 = R2;
  267. I3 = R3;
  268. M0 = R4;
  269. R0 = 11;
  270. RTI;
  271. I12HANDLE: // IVG 12 Handler
  272. R1 = 12;
  273. RTI;
  274. I13HANDLE: // IVG 13 Handler
  275. R2 = 13;
  276. RTI;
  277. I14HANDLE: // IVG 14 Handler
  278. R3 = 14;
  279. RTI;
  280. I15HANDLE: // IVG 15 Handler
  281. R4 = 15;
  282. RTI;
  283. NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
  284. //
  285. // Data Segment
  286. //
  287. .data
  288. DATA:
  289. .space (0x10);
  290. // Stack Segments (Both Kernel and User)
  291. .space (STACKSIZE);
  292. KSTACK:
  293. .space (STACKSIZE);
  294. USTACK: