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cfcku.cgs

cfcku.cgs 9.0 KB
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  1. # frv testcase for cfcku $FCCi,$CCj_float,$CCi,$cond
    2. 

  2. # mach: all
    3. 

  3. 

  4. 	.include "testutils.inc"
    5. 

  5. 

  6. 	start
    7. 

  7. 

  8. 	.global cfcku
    9. 

  9. cfcku:
    10. 

  10. 	set_spr_immed	0x1b5b,cccr
    11. 

  11. 	set_fcc		0x0 0
    12. 

  12. 	cfcku		fcc0,cc3,cc0,1
    13. 

  13. 	test_spr_immed	0x1b9b,cccr
    14. 

  14. 

  15. 	set_spr_immed	0x1b5b,cccr
    16. 

  16. 	set_fcc		0x1 0
    17. 

  17. 	cfcku		fcc0,cc3,cc0,1
    18. 

  18. 	test_spr_immed	0x1bdb,cccr
    19. 

  19. 

  20. 	set_spr_immed	0x1b5b,cccr
    21. 

  21. 	set_fcc		0x2 0
    22. 

  22. 	cfcku		fcc0,cc3,cc0,1
    23. 

  23. 	test_spr_immed	0x1b9b,cccr
    24. 

  24. 

  25. 	set_spr_immed	0x1b5b,cccr
    26. 

  26. 	set_fcc		0x3 0
    27. 

  27. 	cfcku		fcc0,cc3,cc0,1
    28. 

  28. 	test_spr_immed	0x1bdb,cccr
    29. 

  29. 

  30. 	set_spr_immed	0x1b5b,cccr
    31. 

  31. 	set_fcc		0x4 0
    32. 

  32. 	cfcku		fcc0,cc3,cc0,1
    33. 

  33. 	test_spr_immed	0x1b9b,cccr
    34. 

  34. 

  35. 	set_spr_immed	0x1b5b,cccr
    36. 

  36. 	set_fcc		0x5 0
    37. 

  37. 	cfcku		fcc0,cc3,cc0,1
    38. 

  38. 	test_spr_immed	0x1bdb,cccr
    39. 

  39. 

  40. 	set_spr_immed	0x1b5b,cccr
    41. 

  41. 	set_fcc		0x6 0
    42. 

  42. 	cfcku		fcc0,cc3,cc0,1
    43. 

  43. 	test_spr_immed	0x1b9b,cccr
    44. 

  44. 

  45. 	set_spr_immed	0x1b5b,cccr
    46. 

  46. 	set_fcc		0x7 0
    47. 

  47. 	cfcku		fcc0,cc3,cc0,1
    48. 

  48. 	test_spr_immed	0x1bdb,cccr
    49. 

  49. 

  50. 	set_spr_immed	0x1b5b,cccr
    51. 

  51. 	set_fcc		0x8 0
    52. 

  52. 	cfcku		fcc0,cc3,cc4,1
    53. 

  53. 	test_spr_immed	0x1b9b,cccr
    54. 

  54. 

  55. 	set_spr_immed	0x1b5b,cccr
    56. 

  56. 	set_fcc		0x9 0
    57. 

  57. 	cfcku		fcc0,cc3,cc4,1
    58. 

  58. 	test_spr_immed	0x1bdb,cccr
    59. 

  59. 

  60. 	set_spr_immed	0x1b5b,cccr
    61. 

  61. 	set_fcc		0xa 0
    62. 

  62. 	cfcku		fcc0,cc3,cc4,1
    63. 

  63. 	test_spr_immed	0x1b9b,cccr
    64. 

  64. 

  65. 	set_spr_immed	0x1b5b,cccr
    66. 

  66. 	set_fcc		0xb 0
    67. 

  67. 	cfcku		fcc0,cc3,cc4,1
    68. 

  68. 	test_spr_immed	0x1bdb,cccr
    69. 

  69. 

  70. 	set_spr_immed	0x1b5b,cccr
    71. 

  71. 	set_fcc		0xc 0
    72. 

  72. 	cfcku		fcc0,cc3,cc4,1
    73. 

  73. 	test_spr_immed	0x1b9b,cccr
    74. 

  74. 

  75. 	set_spr_immed	0x1b5b,cccr
    76. 

  76. 	set_fcc		0xd 0
    77. 

  77. 	cfcku		fcc0,cc3,cc4,1
    78. 

  78. 	test_spr_immed	0x1bdb,cccr
    79. 

  79. 

  80. 	set_spr_immed	0x1b5b,cccr
    81. 

  81. 	set_fcc		0xe 0
    82. 

  82. 	cfcku		fcc0,cc3,cc4,1
    83. 

  83. 	test_spr_immed	0x1b9b,cccr
    84. 

  84. 

  85. 	set_spr_immed	0x1b5b,cccr
    86. 

  86. 	set_fcc		0xf 0
    87. 

  87. 	cfcku		fcc0,cc3,cc4,1
    88. 

  88. 	test_spr_immed	0x1bdb,cccr
    89. 

  89. 

  90. 	set_spr_immed	0x1b5b,cccr
    91. 

  91. 	set_fcc		0x0 0
    92. 

  92. 	cfcku		fcc0,cc3,cc0,0
    93. 

  93. 	test_spr_immed	0x1b1b,cccr
    94. 

  94. 

  95. 	set_spr_immed	0x1b5b,cccr
    96. 

  96. 	set_fcc		0x1 0
    97. 

  97. 	cfcku		fcc0,cc3,cc0,0
    98. 

  98. 	test_spr_immed	0x1b1b,cccr
    99. 

  99. 

  100. 	set_spr_immed	0x1b5b,cccr
    101. 

  101. 	set_fcc		0x2 0
    102. 

  102. 	cfcku		fcc0,cc3,cc0,0
    103. 

  103. 	test_spr_immed	0x1b1b,cccr
    104. 

  104. 

  105. 	set_spr_immed	0x1b5b,cccr
    106. 

  106. 	set_fcc		0x3 0
    107. 

  107. 	cfcku		fcc0,cc3,cc0,0
    108. 

  108. 	test_spr_immed	0x1b1b,cccr
    109. 

  109. 

  110. 	set_spr_immed	0x1b5b,cccr
    111. 

  111. 	set_fcc		0x4 0
    112. 

  112. 	cfcku		fcc0,cc3,cc0,0
    113. 

  113. 	test_spr_immed	0x1b1b,cccr
    114. 

  114. 

  115. 	set_spr_immed	0x1b5b,cccr
    116. 

  116. 	set_fcc		0x5 0
    117. 

  117. 	cfcku		fcc0,cc3,cc0,0
    118. 

  118. 	test_spr_immed	0x1b1b,cccr
    119. 

  119. 

  120. 	set_spr_immed	0x1b5b,cccr
    121. 

  121. 	set_fcc		0x6 0
    122. 

  122. 	cfcku		fcc0,cc3,cc0,0
    123. 

  123. 	test_spr_immed	0x1b1b,cccr
    124. 

  124. 

  125. 	set_spr_immed	0x1b5b,cccr
    126. 

  126. 	set_fcc		0x7 0
    127. 

  127. 	cfcku		fcc0,cc3,cc0,0
    128. 

  128. 	test_spr_immed	0x1b1b,cccr
    129. 

  129. 

  130. 	set_spr_immed	0x1b5b,cccr
    131. 

  131. 	set_fcc		0x8 0
    132. 

  132. 	cfcku		fcc0,cc3,cc4,0
    133. 

  133. 	test_spr_immed	0x1b1b,cccr
    134. 

  134. 

  135. 	set_spr_immed	0x1b5b,cccr
    136. 

  136. 	set_fcc		0x9 0
    137. 

  137. 	cfcku		fcc0,cc3,cc4,0
    138. 

  138. 	test_spr_immed	0x1b1b,cccr
    139. 

  139. 

  140. 	set_spr_immed	0x1b5b,cccr
    141. 

  141. 	set_fcc		0xa 0
    142. 

  142. 	cfcku		fcc0,cc3,cc4,0
    143. 

  143. 	test_spr_immed	0x1b1b,cccr
    144. 

  144. 

  145. 	set_spr_immed	0x1b5b,cccr
    146. 

  146. 	set_fcc		0xb 0
    147. 

  147. 	cfcku		fcc0,cc3,cc4,0
    148. 

  148. 	test_spr_immed	0x1b1b,cccr
    149. 

  149. 

  150. 	set_spr_immed	0x1b5b,cccr
    151. 

  151. 	set_fcc		0xc 0
    152. 

  152. 	cfcku		fcc0,cc3,cc4,0
    153. 

  153. 	test_spr_immed	0x1b1b,cccr
    154. 

  154. 

  155. 	set_spr_immed	0x1b5b,cccr
    156. 

  156. 	set_fcc		0xd 0
    157. 

  157. 	cfcku		fcc0,cc3,cc4,0
    158. 

  158. 	test_spr_immed	0x1b1b,cccr
    159. 

  159. 

  160. 	set_spr_immed	0x1b5b,cccr
    161. 

  161. 	set_fcc		0xe 0
    162. 

  162. 	cfcku		fcc0,cc3,cc4,0
    163. 

  163. 	test_spr_immed	0x1b1b,cccr
    164. 

  164. 

  165. 	set_spr_immed	0x1b5b,cccr
    166. 

  166. 	set_fcc		0xf 0
    167. 

  167. 	cfcku		fcc0,cc3,cc4,0
    168. 

  168. 	test_spr_immed	0x1b1b,cccr
    169. 

  169. 

  170. 	set_spr_immed	0x1b5b,cccr
    171. 

  171. 	set_fcc		0x0 0
    172. 

  172. 	cfcku		fcc0,cc3,cc1,0
    173. 

  173. 	test_spr_immed	0x1b9b,cccr
    174. 

  174. 

  175. 	set_spr_immed	0x1b5b,cccr
    176. 

  176. 	set_fcc		0x1 0
    177. 

  177. 	cfcku		fcc0,cc3,cc1,0
    178. 

  178. 	test_spr_immed	0x1bdb,cccr
    179. 

  179. 

  180. 	set_spr_immed	0x1b5b,cccr
    181. 

  181. 	set_fcc		0x2 0
    182. 

  182. 	cfcku		fcc0,cc3,cc1,0
    183. 

  183. 	test_spr_immed	0x1b9b,cccr
    184. 

  184. 

  185. 	set_spr_immed	0x1b5b,cccr
    186. 

  186. 	set_fcc		0x3 0
    187. 

  187. 	cfcku		fcc0,cc3,cc1,0
    188. 

  188. 	test_spr_immed	0x1bdb,cccr
    189. 

  189. 

  190. 	set_spr_immed	0x1b5b,cccr
    191. 

  191. 	set_fcc		0x4 0
    192. 

  192. 	cfcku		fcc0,cc3,cc1,0
    193. 

  193. 	test_spr_immed	0x1b9b,cccr
    194. 

  194. 

  195. 	set_spr_immed	0x1b5b,cccr
    196. 

  196. 	set_fcc		0x5 0
    197. 

  197. 	cfcku		fcc0,cc3,cc1,0
    198. 

  198. 	test_spr_immed	0x1bdb,cccr
    199. 

  199. 

  200. 	set_spr_immed	0x1b5b,cccr
    201. 

  201. 	set_fcc		0x6 0
    202. 

  202. 	cfcku		fcc0,cc3,cc1,0
    203. 

  203. 	test_spr_immed	0x1b9b,cccr
    204. 

  204. 

  205. 	set_spr_immed	0x1b5b,cccr
    206. 

  206. 	set_fcc		0x7 0
    207. 

  207. 	cfcku		fcc0,cc3,cc1,0
    208. 

  208. 	test_spr_immed	0x1bdb,cccr
    209. 

  209. 

  210. 	set_spr_immed	0x1b5b,cccr
    211. 

  211. 	set_fcc		0x8 0
    212. 

  212. 	cfcku		fcc0,cc3,cc5,0
    213. 

  213. 	test_spr_immed	0x1b9b,cccr
    214. 

  214. 

  215. 	set_spr_immed	0x1b5b,cccr
    216. 

  216. 	set_fcc		0x9 0
    217. 

  217. 	cfcku		fcc0,cc3,cc5,0
    218. 

  218. 	test_spr_immed	0x1bdb,cccr
    219. 

  219. 

  220. 	set_spr_immed	0x1b5b,cccr
    221. 

  221. 	set_fcc		0xa 0
    222. 

  222. 	cfcku		fcc0,cc3,cc5,0
    223. 

  223. 	test_spr_immed	0x1b9b,cccr
    224. 

  224. 

  225. 	set_spr_immed	0x1b5b,cccr
    226. 

  226. 	set_fcc		0xb 0
    227. 

  227. 	cfcku		fcc0,cc3,cc5,0
    228. 

  228. 	test_spr_immed	0x1bdb,cccr
    229. 

  229. 

  230. 	set_spr_immed	0x1b5b,cccr
    231. 

  231. 	set_fcc		0xc 0
    232. 

  232. 	cfcku		fcc0,cc3,cc5,0
    233. 

  233. 	test_spr_immed	0x1b9b,cccr
    234. 

  234. 

  235. 	set_spr_immed	0x1b5b,cccr
    236. 

  236. 	set_fcc		0xd 0
    237. 

  237. 	cfcku		fcc0,cc3,cc5,0
    238. 

  238. 	test_spr_immed	0x1bdb,cccr
    239. 

  239. 

  240. 	set_spr_immed	0x1b5b,cccr
    241. 

  241. 	set_fcc		0xe 0
    242. 

  242. 	cfcku		fcc0,cc3,cc5,0
    243. 

  243. 	test_spr_immed	0x1b9b,cccr
    244. 

  244. 

  245. 	set_spr_immed	0x1b5b,cccr
    246. 

  246. 	set_fcc		0xf 0
    247. 

  247. 	cfcku		fcc0,cc3,cc5,0
    248. 

  248. 	test_spr_immed	0x1bdb,cccr
    249. 

  249. 

  250. 	set_spr_immed	0x1b5b,cccr
    251. 

  251. 	set_fcc		0x0 0
    252. 

  252. 	cfcku		fcc0,cc3,cc1,1
    253. 

  253. 	test_spr_immed	0x1b1b,cccr
    254. 

  254. 

  255. 	set_spr_immed	0x1b5b,cccr
    256. 

  256. 	set_fcc		0x1 0
    257. 

  257. 	cfcku		fcc0,cc3,cc1,1
    258. 

  258. 	test_spr_immed	0x1b1b,cccr
    259. 

  259. 

  260. 	set_spr_immed	0x1b5b,cccr
    261. 

  261. 	set_fcc		0x2 0
    262. 

  262. 	cfcku		fcc0,cc3,cc1,1
    263. 

  263. 	test_spr_immed	0x1b1b,cccr
    264. 

  264. 

  265. 	set_spr_immed	0x1b5b,cccr
    266. 

  266. 	set_fcc		0x3 0
    267. 

  267. 	cfcku		fcc0,cc3,cc1,1
    268. 

  268. 	test_spr_immed	0x1b1b,cccr
    269. 

  269. 

  270. 	set_spr_immed	0x1b5b,cccr
    271. 

  271. 	set_fcc		0x4 0
    272. 

  272. 	cfcku		fcc0,cc3,cc1,1
    273. 

  273. 	test_spr_immed	0x1b1b,cccr
    274. 

  274. 

  275. 	set_spr_immed	0x1b5b,cccr
    276. 

  276. 	set_fcc		0x5 0
    277. 

  277. 	cfcku		fcc0,cc3,cc1,1
    278. 

  278. 	test_spr_immed	0x1b1b,cccr
    279. 

  279. 

  280. 	set_spr_immed	0x1b5b,cccr
    281. 

  281. 	set_fcc		0x6 0
    282. 

  282. 	cfcku		fcc0,cc3,cc1,1
    283. 

  283. 	test_spr_immed	0x1b1b,cccr
    284. 

  284. 

  285. 	set_spr_immed	0x1b5b,cccr
    286. 

  286. 	set_fcc		0x7 0
    287. 

  287. 	cfcku		fcc0,cc3,cc1,1
    288. 

  288. 	test_spr_immed	0x1b1b,cccr
    289. 

  289. 

  290. 	set_spr_immed	0x1b5b,cccr
    291. 

  291. 	set_fcc		0x8 0
    292. 

  292. 	cfcku		fcc0,cc3,cc5,1
    293. 

  293. 	test_spr_immed	0x1b1b,cccr
    294. 

  294. 

  295. 	set_spr_immed	0x1b5b,cccr
    296. 

  296. 	set_fcc		0x9 0
    297. 

  297. 	cfcku		fcc0,cc3,cc5,1
    298. 

  298. 	test_spr_immed	0x1b1b,cccr
    299. 

  299. 

  300. 	set_spr_immed	0x1b5b,cccr
    301. 

  301. 	set_fcc		0xa 0
    302. 

  302. 	cfcku		fcc0,cc3,cc5,1
    303. 

  303. 	test_spr_immed	0x1b1b,cccr
    304. 

  304. 

  305. 	set_spr_immed	0x1b5b,cccr
    306. 

  306. 	set_fcc		0xb 0
    307. 

  307. 	cfcku		fcc0,cc3,cc5,1
    308. 

  308. 	test_spr_immed	0x1b1b,cccr
    309. 

  309. 

  310. 	set_spr_immed	0x1b5b,cccr
    311. 

  311. 	set_fcc		0xc 0
    312. 

  312. 	cfcku		fcc0,cc3,cc5,1
    313. 

  313. 	test_spr_immed	0x1b1b,cccr
    314. 

  314. 

  315. 	set_spr_immed	0x1b5b,cccr
    316. 

  316. 	set_fcc		0xd 0
    317. 

  317. 	cfcku		fcc0,cc3,cc5,1
    318. 

  318. 	test_spr_immed	0x1b1b,cccr
    319. 

  319. 

  320. 	set_spr_immed	0x1b5b,cccr
    321. 

  321. 	set_fcc		0xe 0
    322. 

  322. 	cfcku		fcc0,cc3,cc5,1
    323. 

  323. 	test_spr_immed	0x1b1b,cccr
    324. 

  324. 

  325. 	set_spr_immed	0x1b5b,cccr
    326. 

  326. 	set_fcc		0xf 0
    327. 

  327. 	cfcku		fcc0,cc3,cc5,1
    328. 

  328. 	test_spr_immed	0x1b1b,cccr
    329. 

  329. 

  330. 	set_spr_immed	0x1b5b,cccr
    331. 

  331. 	set_fcc		0x0 0
    332. 

  332. 	cfcku		fcc0,cc3,cc2,0
    333. 

  333. 	test_spr_immed	0x1b1b,cccr
    334. 

  334. 

  335. 	set_spr_immed	0x1b5b,cccr
    336. 

  336. 	set_fcc		0x1 0
    337. 

  337. 	cfcku		fcc0,cc3,cc2,1
    338. 

  338. 	test_spr_immed	0x1b1b,cccr
    339. 

  339. 

  340. 	set_spr_immed	0x1b5b,cccr
    341. 

  341. 	set_fcc		0x2 0
    342. 

  342. 	cfcku		fcc0,cc3,cc2,0
    343. 

  343. 	test_spr_immed	0x1b1b,cccr
    344. 

  344. 

  345. 	set_spr_immed	0x1b5b,cccr
    346. 

  346. 	set_fcc		0x3 0
    347. 

  347. 	cfcku		fcc0,cc3,cc2,1
    348. 

  348. 	test_spr_immed	0x1b1b,cccr
    349. 

  349. 

  350. 	set_spr_immed	0x1b5b,cccr
    351. 

  351. 	set_fcc		0x4 0
    352. 

  352. 	cfcku		fcc0,cc3,cc2,0
    353. 

  353. 	test_spr_immed	0x1b1b,cccr
    354. 

  354. 

  355. 	set_spr_immed	0x1b5b,cccr
    356. 

  356. 	set_fcc		0x5 0
    357. 

  357. 	cfcku		fcc0,cc3,cc2,1
    358. 

  358. 	test_spr_immed	0x1b1b,cccr
    359. 

  359. 

  360. 	set_spr_immed	0x1b5b,cccr
    361. 

  361. 	set_fcc		0x6 0
    362. 

  362. 	cfcku		fcc0,cc3,cc2,0
    363. 

  363. 	test_spr_immed	0x1b1b,cccr
    364. 

  364. 

  365. 	set_spr_immed	0x1b5b,cccr
    366. 

  366. 	set_fcc		0x7 0
    367. 

  367. 	cfcku		fcc0,cc3,cc2,1
    368. 

  368. 	test_spr_immed	0x1b1b,cccr
    369. 

  369. 

  370. 	set_spr_immed	0x1b5b,cccr
    371. 

  371. 	set_fcc		0x8 0
    372. 

  372. 	cfcku		fcc0,cc3,cc6,0
    373. 

  373. 	test_spr_immed	0x1b1b,cccr
    374. 

  374. 

  375. 	set_spr_immed	0x1b5b,cccr
    376. 

  376. 	set_fcc		0x9 0
    377. 

  377. 	cfcku		fcc0,cc3,cc6,1
    378. 

  378. 	test_spr_immed	0x1b1b,cccr
    379. 

  379. 

  380. 	set_spr_immed	0x1b5b,cccr
    381. 

  381. 	set_fcc		0xa 0
    382. 

  382. 	cfcku		fcc0,cc3,cc6,0
    383. 

  383. 	test_spr_immed	0x1b1b,cccr
    384. 

  384. 

  385. 	set_spr_immed	0x1b5b,cccr
    386. 

  386. 	set_fcc		0xb 0
    387. 

  387. 	cfcku		fcc0,cc3,cc6,1
    388. 

  388. 	test_spr_immed	0x1b1b,cccr
    389. 

  389. 

  390. 	set_spr_immed	0x1b5b,cccr
    391. 

  391. 	set_fcc		0xc 0
    392. 

  392. 	cfcku		fcc0,cc3,cc6,0
    393. 

  393. 	test_spr_immed	0x1b1b,cccr
    394. 

  394. 

  395. 	set_spr_immed	0x1b5b,cccr
    396. 

  396. 	set_fcc		0xd 0
    397. 

  397. 	cfcku		fcc0,cc3,cc6,1
    398. 

  398. 	test_spr_immed	0x1b1b,cccr
    399. 

  399. 

  400. 	set_spr_immed	0x1b5b,cccr
    401. 

  401. 	set_fcc		0xe 0
    402. 

  402. 	cfcku		fcc0,cc3,cc6,0
    403. 

  403. 	test_spr_immed	0x1b1b,cccr
    404. 

  404. 

  405. 	set_spr_immed	0x1b5b,cccr
    406. 

  406. 	set_fcc		0xf 0
    407. 

  407. 	cfcku		fcc0,cc3,cc6,1
    408. 

  408. 	test_spr_immed	0x1b1b,cccr
    409. 

  409. 

  410. 	set_spr_immed	0x1b5b,cccr
    411. 

  411. 	set_fcc		0x0 0
    412. 

  412. 	cfcku		fcc0,cc3,cc3,0
    413. 

  413. 	test_spr_immed	0x1b1b,cccr
    414. 

  414. 

  415. 	set_spr_immed	0x1b5b,cccr
    416. 

  416. 	set_fcc		0x1 0
    417. 

  417. 	cfcku		fcc0,cc3,cc3,1
    418. 

  418. 	test_spr_immed	0x1b1b,cccr
    419. 

  419. 

  420. 	set_spr_immed	0x1b5b,cccr
    421. 

  421. 	set_fcc		0x2 0
    422. 

  422. 	cfcku		fcc0,cc3,cc3,0
    423. 

  423. 	test_spr_immed	0x1b1b,cccr
    424. 

  424. 

  425. 	set_spr_immed	0x1b5b,cccr
    426. 

  426. 	set_fcc		0x3 0
    427. 

  427. 	cfcku		fcc0,cc3,cc3,1
    428. 

  428. 	test_spr_immed	0x1b1b,cccr
    429. 

  429. 

  430. 	set_spr_immed	0x1b5b,cccr
    431. 

  431. 	set_fcc		0x4 0
    432. 

  432. 	cfcku		fcc0,cc3,cc3,0
    433. 

  433. 	test_spr_immed	0x1b1b,cccr
    434. 

  434. 

  435. 	set_spr_immed	0x1b5b,cccr
    436. 

  436. 	set_fcc		0x5 0
    437. 

  437. 	cfcku		fcc0,cc3,cc3,1
    438. 

  438. 	test_spr_immed	0x1b1b,cccr
    439. 

  439. 

  440. 	set_spr_immed	0x1b5b,cccr
    441. 

  441. 	set_fcc		0x6 0
    442. 

  442. 	cfcku		fcc0,cc3,cc3,0
    443. 

  443. 	test_spr_immed	0x1b1b,cccr
    444. 

  444. 

  445. 	set_spr_immed	0x1b5b,cccr
    446. 

  446. 	set_fcc		0x7 0
    447. 

  447. 	cfcku		fcc0,cc3,cc3,1
    448. 

  448. 	test_spr_immed	0x1b1b,cccr
    449. 

  449. 

  450. 	set_spr_immed	0x1b5b,cccr
    451. 

  451. 	set_fcc		0x8 0
    452. 

  452. 	cfcku		fcc0,cc3,cc7,0
    453. 

  453. 	test_spr_immed	0x1b1b,cccr
    454. 

  454. 

  455. 	set_spr_immed	0x1b5b,cccr
    456. 

  456. 	set_fcc		0x9 0
    457. 

  457. 	cfcku		fcc0,cc3,cc7,1
    458. 

  458. 	test_spr_immed	0x1b1b,cccr
    459. 

  459. 

  460. 	set_spr_immed	0x1b5b,cccr
    461. 

  461. 	set_fcc		0xa 0
    462. 

  462. 	cfcku		fcc0,cc3,cc7,0
    463. 

  463. 	test_spr_immed	0x1b1b,cccr
    464. 

  464. 

  465. 	set_spr_immed	0x1b5b,cccr
    466. 

  466. 	set_fcc		0xb 0
    467. 

  467. 	cfcku		fcc0,cc3,cc7,1
    468. 

  468. 	test_spr_immed	0x1b1b,cccr
    469. 

  469. 

  470. 	set_spr_immed	0x1b5b,cccr
    471. 

  471. 	set_fcc		0xc 0
    472. 

  472. 	cfcku		fcc0,cc3,cc7,0
    473. 

  473. 	test_spr_immed	0x1b1b,cccr
    474. 

  474. 

  475. 	set_spr_immed	0x1b5b,cccr
    476. 

  476. 	set_fcc		0xd 0
    477. 

  477. 	cfcku		fcc0,cc3,cc7,1
    478. 

  478. 	test_spr_immed	0x1b1b,cccr
    479. 

  479. 

  480. 	set_spr_immed	0x1b5b,cccr
    481. 

  481. 	set_fcc		0xe 0
    482. 

  482. 	cfcku		fcc0,cc3,cc7,0
    483. 

  483. 	test_spr_immed	0x1b1b,cccr
    484. 

  484. 

  485. 	set_spr_immed	0x1b5b,cccr
    486. 

  486. 	set_fcc		0xf 0
    487. 

  487. 	cfcku		fcc0,cc3,cc7,1
    488. 

  488. 	test_spr_immed	0x1b1b,cccr
    489. 

  489. 

  490. 	pass
    491.