Home Explore Help
Register Sign In
akucxy
/
binutils-gdb
1
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Branch: master
Branches Tags
binutils-gdb
/
sim
/
testsuite
/
frv
/
cmsubhss.cgs

cmsubhss.cgs 19 KB
Permalink History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562 
  1. # frv testcase for cmsubhss $FRi,$FRj,$FRj,$CCi,$cond
    2. 

  2. # mach: frv fr500 fr400
    3. 

  3. 

  4. 	.include "testutils.inc"
    5. 

  5. 

  6. 	start
    7. 

  7. 

  8. 	.global cmsubhss
    9. 

  9. cmsubhss:
    10. 

  10. 	set_spr_immed	0x1b1b,cccr
    11. 

  11. 

  12. 	set_fr_iimmed	0x0000,0x0000,fr10
    13. 

  13. 	set_fr_iimmed	0x0000,0x0000,fr11
    14. 

  14. 	cmsubhss	fr10,fr11,fr12,cc0,1
    15. 

  15. 	test_fr_limmed	0x0000,0x0000,fr12
    16. 

  16. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    17. 

  17. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    18. 

  18. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    19. 

  19. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    20. 

  20. 

  21. 	set_fr_iimmed	0xdead,0x0000,fr10
    22. 

  22. 	set_fr_iimmed	0x0000,0xbeef,fr11
    23. 

  23. 	cmsubhss	fr10,fr11,fr12,cc0,1
    24. 

  24. 	test_fr_limmed	0xdead,0x4111,fr12
    25. 

  25. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    26. 

  26. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    27. 

  27. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    28. 

  28. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    29. 

  29. 

  30. 	set_fr_iimmed	0x0000,0xdead,fr10
    31. 

  31. 	set_fr_iimmed	0xbeef,0x0000,fr11
    32. 

  32. 	cmsubhss	fr10,fr11,fr12,cc0,1
    33. 

  33. 	test_fr_limmed	0x4111,0xdead,fr12
    34. 

  34. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    35. 

  35. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    36. 

  36. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    37. 

  37. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    38. 

  38. 

  39. 	set_fr_iimmed	0x1234,0x5678,fr10
    40. 

  40. 	set_fr_iimmed	0x1111,0x1111,fr11
    41. 

  41. 	cmsubhss	fr10,fr11,fr12,cc0,1
    42. 

  42. 	test_fr_limmed	0x0123,0x4567,fr12
    43. 

  43. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    44. 

  44. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    45. 

  45. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    46. 

  46. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    47. 

  47. 

  48. 	set_fr_iimmed	0x1234,0x5678,fr10
    49. 

  49. 	set_fr_iimmed	0xffff,0xffff,fr11
    50. 

  50. 	cmsubhss	fr10,fr11,fr12,cc0,1
    51. 

  51. 	test_fr_limmed	0x1235,0x5679,fr12
    52. 

  52. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    53. 

  53. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    54. 

  54. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    55. 

  55. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    56. 

  56. 

  57. 	set_spr_immed	0,msr0
    58. 

  58. 	set_fr_iimmed	0x7ffe,0x7ffe,fr10
    59. 

  59. 	set_fr_iimmed	0xfffe,0xffff,fr11
    60. 

  60. 	cmsubhss	fr10,fr11,fr12,cc4,1
    61. 

  61. 	test_fr_limmed	0x7fff,0x7fff,fr12
    62. 

  62. 	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
    63. 

  63. 	test_spr_bits	2,1,1,msr0		; msr0.ovf set
    64. 

  64. 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
    65. 

  65. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
    66. 

  66. 

  67. 	set_spr_immed	0,msr0
    68. 

  68. 	set_fr_iimmed	0x8001,0x8001,fr10
    69. 

  69. 	set_fr_iimmed	0x0001,0x0002,fr11
    70. 

  70. 	cmsubhss	fr10,fr11,fr12,cc4,1
    71. 

  71. 	test_fr_limmed	0x8000,0x8000,fr12
    72. 

  72. 	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
    73. 

  73. 	test_spr_bits	2,1,1,msr0		; msr0.ovf set
    74. 

  74. 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
    75. 

  75. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
    76. 

  76. 

  77. 	set_spr_immed	0,msr0
    78. 

  78. 	set_fr_iimmed	0x8001,0x8001,fr10
    79. 

  79. 	set_fr_iimmed	0x0002,0x0001,fr11
    80. 

  80. 	cmsubhss	fr10,fr11,fr12,cc4,1
    81. 

  81. 	test_fr_limmed	0x8000,0x8000,fr12
    82. 

  82. 	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
    83. 

  83. 	test_spr_bits	2,1,1,msr0		; msr0.ovf set
    84. 

  84. 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
    85. 

  85. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
    86. 

  86. 

  87. 	set_spr_immed	0,msr0
    88. 

  88. 	set_spr_immed	0,msr1
    89. 

  89. 	set_fr_iimmed	0x0001,0x0001,fr10
    90. 

  90. 	set_fr_iimmed	0x8000,0x8000,fr11
    91. 

  91. 	cmsubhss.p	fr10,fr10,fr12,cc4,1
    92. 

  92. 	cmsubhss	fr11,fr10,fr13,cc4,1
    93. 

  93. 	test_fr_limmed	0x0000,0x0000,fr12
    94. 

  94. 	test_fr_limmed	0x8000,0x8000,fr13
    95. 

  95. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    96. 

  96. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    97. 

  97. 	test_spr_bits	0x3c,2,0xc,msr1		; msr0.sie is set
    98. 

  98. 	test_spr_bits	2,1,1,msr1		; msr1.ovf set
    99. 

  99. 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
    100. 

  100. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
    101. 

  101. 

  102. 	set_spr_immed	0,msr0
    103. 

  103. 	set_spr_immed	0,msr1
    104. 

  104. 	set_fr_iimmed	0x0000,0x0000,fr10
    105. 

  105. 	set_fr_iimmed	0x0000,0x0000,fr11
    106. 

  106. 	cmsubhss	fr10,fr11,fr12,cc1,0
    107. 

  107. 	test_fr_limmed	0x0000,0x0000,fr12
    108. 

  108. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    109. 

  109. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    110. 

  110. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    111. 

  111. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    112. 

  112. 

  113. 	set_fr_iimmed	0xdead,0x0000,fr10
    114. 

  114. 	set_fr_iimmed	0x0000,0xbeef,fr11
    115. 

  115. 	cmsubhss	fr10,fr11,fr12,cc1,0
    116. 

  116. 	test_fr_limmed	0xdead,0x4111,fr12
    117. 

  117. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    118. 

  118. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    119. 

  119. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    120. 

  120. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    121. 

  121. 

  122. 	set_fr_iimmed	0x0000,0xdead,fr10
    123. 

  123. 	set_fr_iimmed	0xbeef,0x0000,fr11
    124. 

  124. 	cmsubhss	fr10,fr11,fr12,cc1,0
    125. 

  125. 	test_fr_limmed	0x4111,0xdead,fr12
    126. 

  126. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    127. 

  127. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    128. 

  128. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    129. 

  129. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    130. 

  130. 

  131. 	set_fr_iimmed	0x1234,0x5678,fr10
    132. 

  132. 	set_fr_iimmed	0x1111,0x1111,fr11
    133. 

  133. 	cmsubhss	fr10,fr11,fr12,cc1,0
    134. 

  134. 	test_fr_limmed	0x0123,0x4567,fr12
    135. 

  135. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    136. 

  136. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    137. 

  137. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    138. 

  138. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    139. 

  139. 

  140. 	set_fr_iimmed	0x1234,0x5678,fr10
    141. 

  141. 	set_fr_iimmed	0xffff,0xffff,fr11
    142. 

  142. 	cmsubhss	fr10,fr11,fr12,cc1,0
    143. 

  143. 	test_fr_limmed	0x1235,0x5679,fr12
    144. 

  144. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    145. 

  145. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    146. 

  146. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    147. 

  147. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    148. 

  148. 

  149. 	set_spr_immed	0,msr0
    150. 

  150. 	set_fr_iimmed	0x7ffe,0x7ffe,fr10
    151. 

  151. 	set_fr_iimmed	0xfffe,0xffff,fr11
    152. 

  152. 	cmsubhss	fr10,fr11,fr12,cc5,0
    153. 

  153. 	test_fr_limmed	0x7fff,0x7fff,fr12
    154. 

  154. 	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
    155. 

  155. 	test_spr_bits	2,1,1,msr0		; msr0.ovf set
    156. 

  156. 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
    157. 

  157. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
    158. 

  158. 

  159. 	set_spr_immed	0,msr0
    160. 

  160. 	set_fr_iimmed	0x8001,0x8001,fr10
    161. 

  161. 	set_fr_iimmed	0x0001,0x0002,fr11
    162. 

  162. 	cmsubhss	fr10,fr11,fr12,cc5,0
    163. 

  163. 	test_fr_limmed	0x8000,0x8000,fr12
    164. 

  164. 	test_spr_bits	0x3c,2,0x4,msr0		; msr0.sie is set
    165. 

  165. 	test_spr_bits	2,1,1,msr0		; msr0.ovf set
    166. 

  166. 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
    167. 

  167. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
    168. 

  168. 

  169. 	set_spr_immed	0,msr0
    170. 

  170. 	set_fr_iimmed	0x8001,0x8001,fr10
    171. 

  171. 	set_fr_iimmed	0x0002,0x0001,fr11
    172. 

  172. 	cmsubhss	fr10,fr11,fr12,cc5,0
    173. 

  173. 	test_fr_limmed	0x8000,0x8000,fr12
    174. 

  174. 	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
    175. 

  175. 	test_spr_bits	2,1,1,msr0		; msr0.ovf set
    176. 

  176. 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
    177. 

  177. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
    178. 

  178. 

  179. 	set_spr_immed	0,msr0
    180. 

  180. 	set_spr_immed	0,msr1
    181. 

  181. 	set_fr_iimmed	0x0001,0x0001,fr10
    182. 

  182. 	set_fr_iimmed	0x8000,0x8000,fr11
    183. 

  183. 	cmsubhss.p	fr10,fr10,fr12,cc5,0
    184. 

  184. 	cmsubhss	fr11,fr10,fr13,cc5,0
    185. 

  185. 	test_fr_limmed	0x0000,0x0000,fr12
    186. 

  186. 	test_fr_limmed	0x8000,0x8000,fr13
    187. 

  187. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    188. 

  188. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    189. 

  189. 	test_spr_bits	0x3c,2,0xc,msr1		; msr0.sie is set
    190. 

  190. 	test_spr_bits	2,1,1,msr1		; msr1.ovf set
    191. 

  191. 	test_spr_bits	1,0,1,msr0		; msr0.aovf set
    192. 

  192. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt set
    193. 

  193. 

  194. 	set_fr_iimmed	0xdead,0xbeef,fr12
    195. 

  195. 	set_spr_immed	0,msr0
    196. 

  196. 	set_spr_immed	0,msr1
    197. 

  197. 	set_fr_iimmed	0x0000,0x0000,fr10
    198. 

  198. 	set_fr_iimmed	0x0000,0x0000,fr11
    199. 

  199. 	cmsubhss	fr10,fr11,fr12,cc0,0
    200. 

  200. 	test_fr_limmed	0xdead,0xbeef,fr12
    201. 

  201. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    202. 

  202. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    203. 

  203. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    204. 

  204. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    205. 

  205. 

  206. 	set_fr_iimmed	0xdead,0x0000,fr10
    207. 

  207. 	set_fr_iimmed	0x0000,0xbeef,fr11
    208. 

  208. 	cmsubhss	fr10,fr11,fr12,cc0,0
    209. 

  209. 	test_fr_limmed	0xdead,0xbeef,fr12
    210. 

  210. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    211. 

  211. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    212. 

  212. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    213. 

  213. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    214. 

  214. 

  215. 	set_fr_iimmed	0x0000,0xdead,fr10
    216. 

  216. 	set_fr_iimmed	0xbeef,0x0000,fr11
    217. 

  217. 	cmsubhss	fr10,fr11,fr12,cc0,0
    218. 

  218. 	test_fr_limmed	0xdead,0xbeef,fr12
    219. 

  219. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    220. 

  220. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    221. 

  221. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    222. 

  222. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    223. 

  223. 

  224. 	set_fr_iimmed	0x1234,0x5678,fr10
    225. 

  225. 	set_fr_iimmed	0x1111,0x1111,fr11
    226. 

  226. 	cmsubhss	fr10,fr11,fr12,cc0,0
    227. 

  227. 	test_fr_limmed	0xdead,0xbeef,fr12
    228. 

  228. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    229. 

  229. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    230. 

  230. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    231. 

  231. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    232. 

  232. 

  233. 	set_fr_iimmed	0x1234,0x5678,fr10
    234. 

  234. 	set_fr_iimmed	0xffff,0xffff,fr11
    235. 

  235. 	cmsubhss	fr10,fr11,fr12,cc0,0
    236. 

  236. 	test_fr_limmed	0xdead,0xbeef,fr12
    237. 

  237. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    238. 

  238. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    239. 

  239. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    240. 

  240. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    241. 

  241. 

  242. 	set_spr_immed	0,msr0
    243. 

  243. 	set_fr_iimmed	0x7ffe,0x7ffe,fr10
    244. 

  244. 	set_fr_iimmed	0xfffe,0xffff,fr11
    245. 

  245. 	cmsubhss	fr10,fr11,fr12,cc4,0
    246. 

  246. 	test_fr_limmed	0xdead,0xbeef,fr12
    247. 

  247. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    248. 

  248. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    249. 

  249. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    250. 

  250. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    251. 

  251. 

  252. 	set_spr_immed	0,msr0
    253. 

  253. 	set_fr_iimmed	0x8001,0x8001,fr10
    254. 

  254. 	set_fr_iimmed	0x0001,0x0002,fr11
    255. 

  255. 	cmsubhss	fr10,fr11,fr12,cc4,0
    256. 

  256. 	test_fr_limmed	0xdead,0xbeef,fr12
    257. 

  257. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    258. 

  258. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    259. 

  259. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    260. 

  260. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    261. 

  261. 

  262. 	set_spr_immed	0,msr0
    263. 

  263. 	set_fr_iimmed	0x8001,0x8001,fr10
    264. 

  264. 	set_fr_iimmed	0x0002,0x0001,fr11
    265. 

  265. 	cmsubhss	fr10,fr11,fr12,cc4,0
    266. 

  266. 	test_fr_limmed	0xdead,0xbeef,fr12
    267. 

  267. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    268. 

  268. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    269. 

  269. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    270. 

  270. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    271. 

  271. 

  272. 	set_fr_iimmed	0xbeef,0xdead,fr13
    273. 

  273. 	set_spr_immed	0,msr0
    274. 

  274. 	set_spr_immed	0,msr1
    275. 

  275. 	set_fr_iimmed	0x0001,0x0001,fr10
    276. 

  276. 	set_fr_iimmed	0x8000,0x8000,fr11
    277. 

  277. 	cmsubhss.p	fr10,fr10,fr12,cc4,0
    278. 

  278. 	cmsubhss	fr11,fr10,fr13,cc4,0
    279. 

  279. 	test_fr_limmed	0xdead,0xbeef,fr12
    280. 

  280. 	test_fr_limmed	0xbeef,0xdead,fr13
    281. 

  281. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    282. 

  282. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    283. 

  283. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    284. 

  284. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    285. 

  285. 

  286. 	set_fr_iimmed	0xdead,0xbeef,fr12
    287. 

  287. 	set_spr_immed	0,msr0
    288. 

  288. 	set_spr_immed	0,msr1
    289. 

  289. 	set_fr_iimmed	0x0000,0x0000,fr10
    290. 

  290. 	set_fr_iimmed	0x0000,0x0000,fr11
    291. 

  291. 	cmsubhss	fr10,fr11,fr12,cc1,1
    292. 

  292. 	test_fr_limmed	0xdead,0xbeef,fr12
    293. 

  293. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    294. 

  294. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    295. 

  295. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    296. 

  296. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    297. 

  297. 

  298. 	set_fr_iimmed	0xdead,0x0000,fr10
    299. 

  299. 	set_fr_iimmed	0x0000,0xbeef,fr11
    300. 

  300. 	cmsubhss	fr10,fr11,fr12,cc1,1
    301. 

  301. 	test_fr_limmed	0xdead,0xbeef,fr12
    302. 

  302. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    303. 

  303. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    304. 

  304. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    305. 

  305. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    306. 

  306. 

  307. 	set_fr_iimmed	0x0000,0xdead,fr10
    308. 

  308. 	set_fr_iimmed	0xbeef,0x0000,fr11
    309. 

  309. 	cmsubhss	fr10,fr11,fr12,cc1,1
    310. 

  310. 	test_fr_limmed	0xdead,0xbeef,fr12
    311. 

  311. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    312. 

  312. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    313. 

  313. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    314. 

  314. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    315. 

  315. 

  316. 	set_fr_iimmed	0x1234,0x5678,fr10
    317. 

  317. 	set_fr_iimmed	0x1111,0x1111,fr11
    318. 

  318. 	cmsubhss	fr10,fr11,fr12,cc1,1
    319. 

  319. 	test_fr_limmed	0xdead,0xbeef,fr12
    320. 

  320. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    321. 

  321. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    322. 

  322. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    323. 

  323. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    324. 

  324. 

  325. 	set_fr_iimmed	0x1234,0x5678,fr10
    326. 

  326. 	set_fr_iimmed	0xffff,0xffff,fr11
    327. 

  327. 	cmsubhss	fr10,fr11,fr12,cc1,1
    328. 

  328. 	test_fr_limmed	0xdead,0xbeef,fr12
    329. 

  329. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    330. 

  330. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    331. 

  331. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    332. 

  332. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    333. 

  333. 

  334. 	set_spr_immed	0,msr0
    335. 

  335. 	set_fr_iimmed	0x7ffe,0x7ffe,fr10
    336. 

  336. 	set_fr_iimmed	0xfffe,0xffff,fr11
    337. 

  337. 	cmsubhss	fr10,fr11,fr12,cc5,1
    338. 

  338. 	test_fr_limmed	0xdead,0xbeef,fr12
    339. 

  339. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    340. 

  340. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    341. 

  341. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    342. 

  342. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    343. 

  343. 

  344. 	set_spr_immed	0,msr0
    345. 

  345. 	set_fr_iimmed	0x8001,0x8001,fr10
    346. 

  346. 	set_fr_iimmed	0x0001,0x0002,fr11
    347. 

  347. 	cmsubhss	fr10,fr11,fr12,cc5,1
    348. 

  348. 	test_fr_limmed	0xdead,0xbeef,fr12
    349. 

  349. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    350. 

  350. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    351. 

  351. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    352. 

  352. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    353. 

  353. 

  354. 	set_spr_immed	0,msr0
    355. 

  355. 	set_fr_iimmed	0x8001,0x8001,fr10
    356. 

  356. 	set_fr_iimmed	0x0002,0x0001,fr11
    357. 

  357. 	cmsubhss	fr10,fr11,fr12,cc5,1
    358. 

  358. 	test_fr_limmed	0xdead,0xbeef,fr12
    359. 

  359. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    360. 

  360. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    361. 

  361. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    362. 

  362. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    363. 

  363. 

  364. 	set_fr_iimmed	0xbeef,0xdead,fr13
    365. 

  365. 	set_spr_immed	0,msr0
    366. 

  366. 	set_spr_immed	0,msr1
    367. 

  367. 	set_fr_iimmed	0x0001,0x0001,fr10
    368. 

  368. 	set_fr_iimmed	0x8000,0x8000,fr11
    369. 

  369. 	cmsubhss.p	fr10,fr10,fr12,cc5,1
    370. 

  370. 	cmsubhss	fr11,fr10,fr13,cc5,1
    371. 

  371. 	test_fr_limmed	0xdead,0xbeef,fr12
    372. 

  372. 	test_fr_limmed	0xbeef,0xdead,fr13
    373. 

  373. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    374. 

  374. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    375. 

  375. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    376. 

  376. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    377. 

  377. 

  378. 	set_fr_iimmed	0xdead,0xbeef,fr12
    379. 

  379. 	set_spr_immed	0,msr0
    380. 

  380. 	set_spr_immed	0,msr1
    381. 

  381. 	set_fr_iimmed	0x0000,0x0000,fr10
    382. 

  382. 	set_fr_iimmed	0x0000,0x0000,fr11
    383. 

  383. 	cmsubhss	fr10,fr11,fr12,cc2,1
    384. 

  384. 	test_fr_limmed	0xdead,0xbeef,fr12
    385. 

  385. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    386. 

  386. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    387. 

  387. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    388. 

  388. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    389. 

  389. 

  390. 	set_fr_iimmed	0xdead,0x0000,fr10
    391. 

  391. 	set_fr_iimmed	0x0000,0xbeef,fr11
    392. 

  392. 	cmsubhss	fr10,fr11,fr12,cc2,0
    393. 

  393. 	test_fr_limmed	0xdead,0xbeef,fr12
    394. 

  394. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    395. 

  395. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    396. 

  396. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    397. 

  397. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    398. 

  398. 

  399. 	set_fr_iimmed	0x0000,0xdead,fr10
    400. 

  400. 	set_fr_iimmed	0xbeef,0x0000,fr11
    401. 

  401. 	cmsubhss	fr10,fr11,fr12,cc2,1
    402. 

  402. 	test_fr_limmed	0xdead,0xbeef,fr12
    403. 

  403. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    404. 

  404. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    405. 

  405. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    406. 

  406. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    407. 

  407. 

  408. 	set_fr_iimmed	0x1234,0x5678,fr10
    409. 

  409. 	set_fr_iimmed	0x1111,0x1111,fr11
    410. 

  410. 	cmsubhss	fr10,fr11,fr12,cc2,0
    411. 

  411. 	test_fr_limmed	0xdead,0xbeef,fr12
    412. 

  412. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    413. 

  413. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    414. 

  414. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    415. 

  415. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    416. 

  416. 

  417. 	set_fr_iimmed	0x1234,0x5678,fr10
    418. 

  418. 	set_fr_iimmed	0xffff,0xffff,fr11
    419. 

  419. 	cmsubhss	fr10,fr11,fr12,cc2,1
    420. 

  420. 	test_fr_limmed	0xdead,0xbeef,fr12
    421. 

  421. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    422. 

  422. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    423. 

  423. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    424. 

  424. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    425. 

  425. 

  426. 	set_spr_immed	0,msr0
    427. 

  427. 	set_fr_iimmed	0x7ffe,0x7ffe,fr10
    428. 

  428. 	set_fr_iimmed	0xfffe,0xffff,fr11
    429. 

  429. 	cmsubhss	fr10,fr11,fr12,cc6,0
    430. 

  430. 	test_fr_limmed	0xdead,0xbeef,fr12
    431. 

  431. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    432. 

  432. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    433. 

  433. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    434. 

  434. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    435. 

  435. 

  436. 	set_spr_immed	0,msr0
    437. 

  437. 	set_fr_iimmed	0x8001,0x8001,fr10
    438. 

  438. 	set_fr_iimmed	0x0001,0x0002,fr11
    439. 

  439. 	cmsubhss	fr10,fr11,fr12,cc6,1
    440. 

  440. 	test_fr_limmed	0xdead,0xbeef,fr12
    441. 

  441. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    442. 

  442. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    443. 

  443. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    444. 

  444. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    445. 

  445. 

  446. 	set_spr_immed	0,msr0
    447. 

  447. 	set_fr_iimmed	0x8001,0x8001,fr10
    448. 

  448. 	set_fr_iimmed	0x0002,0x0001,fr11
    449. 

  449. 	cmsubhss	fr10,fr11,fr12,cc6,0
    450. 

  450. 	test_fr_limmed	0xdead,0xbeef,fr12
    451. 

  451. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    452. 

  452. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    453. 

  453. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    454. 

  454. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    455. 

  455. 

  456. 	set_fr_iimmed	0xbeef,0xdead,fr13
    457. 

  457. 	set_spr_immed	0,msr0
    458. 

  458. 	set_spr_immed	0,msr1
    459. 

  459. 	set_fr_iimmed	0x0001,0x0001,fr10
    460. 

  460. 	set_fr_iimmed	0x8000,0x8000,fr11
    461. 

  461. 	cmsubhss.p	fr10,fr10,fr12,cc6,1
    462. 

  462. 	cmsubhss	fr11,fr10,fr13,cc6,0
    463. 

  463. 	test_fr_limmed	0xdead,0xbeef,fr12
    464. 

  464. 	test_fr_limmed	0xbeef,0xdead,fr13
    465. 

  465. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    466. 

  466. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    467. 

  467. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    468. 

  468. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    469. 

  469. ;
    470. 

  470. 	set_fr_iimmed	0xdead,0xbeef,fr12
    471. 

  471. 	set_spr_immed	0,msr0
    472. 

  472. 	set_spr_immed	0,msr1
    473. 

  473. 	set_fr_iimmed	0x0000,0x0000,fr10
    474. 

  474. 	set_fr_iimmed	0x0000,0x0000,fr11
    475. 

  475. 	cmsubhss	fr10,fr11,fr12,cc3,1
    476. 

  476. 	test_fr_limmed	0xdead,0xbeef,fr12
    477. 

  477. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    478. 

  478. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    479. 

  479. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    480. 

  480. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    481. 

  481. 

  482. 	set_fr_iimmed	0xdead,0x0000,fr10
    483. 

  483. 	set_fr_iimmed	0x0000,0xbeef,fr11
    484. 

  484. 	cmsubhss	fr10,fr11,fr12,cc3,0
    485. 

  485. 	test_fr_limmed	0xdead,0xbeef,fr12
    486. 

  486. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    487. 

  487. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    488. 

  488. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    489. 

  489. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    490. 

  490. 

  491. 	set_fr_iimmed	0x0000,0xdead,fr10
    492. 

  492. 	set_fr_iimmed	0xbeef,0x0000,fr11
    493. 

  493. 	cmsubhss	fr10,fr11,fr12,cc3,1
    494. 

  494. 	test_fr_limmed	0xdead,0xbeef,fr12
    495. 

  495. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    496. 

  496. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    497. 

  497. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    498. 

  498. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    499. 

  499. 

  500. 	set_fr_iimmed	0x1234,0x5678,fr10
    501. 

  501. 	set_fr_iimmed	0x1111,0x1111,fr11
    502. 

  502. 	cmsubhss	fr10,fr11,fr12,cc3,0
    503. 

  503. 	test_fr_limmed	0xdead,0xbeef,fr12
    504. 

  504. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    505. 

  505. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    506. 

  506. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    507. 

  507. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    508. 

  508. 

  509. 	set_fr_iimmed	0x1234,0x5678,fr10
    510. 

  510. 	set_fr_iimmed	0xffff,0xffff,fr11
    511. 

  511. 	cmsubhss	fr10,fr11,fr12,cc3,1
    512. 

  512. 	test_fr_limmed	0xdead,0xbeef,fr12
    513. 

  513. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    514. 

  514. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    515. 

  515. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    516. 

  516. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    517. 

  517. 

  518. 	set_spr_immed	0,msr0
    519. 

  519. 	set_fr_iimmed	0x7ffe,0x7ffe,fr10
    520. 

  520. 	set_fr_iimmed	0xfffe,0xffff,fr11
    521. 

  521. 	cmsubhss	fr10,fr11,fr12,cc7,0
    522. 

  522. 	test_fr_limmed	0xdead,0xbeef,fr12
    523. 

  523. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    524. 

  524. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    525. 

  525. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    526. 

  526. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    527. 

  527. 

  528. 	set_spr_immed	0,msr0
    529. 

  529. 	set_fr_iimmed	0x8001,0x8001,fr10
    530. 

  530. 	set_fr_iimmed	0x0001,0x0002,fr11
    531. 

  531. 	cmsubhss	fr10,fr11,fr12,cc7,1
    532. 

  532. 	test_fr_limmed	0xdead,0xbeef,fr12
    533. 

  533. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    534. 

  534. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    535. 

  535. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    536. 

  536. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    537. 

  537. 

  538. 	set_spr_immed	0,msr0
    539. 

  539. 	set_fr_iimmed	0x8001,0x8001,fr10
    540. 

  540. 	set_fr_iimmed	0x0002,0x0001,fr11
    541. 

  541. 	cmsubhss	fr10,fr11,fr12,cc7,0
    542. 

  542. 	test_fr_limmed	0xdead,0xbeef,fr12
    543. 

  543. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    544. 

  544. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    545. 

  545. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    546. 

  546. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    547. 

  547. 

  548. 	set_fr_iimmed	0xbeef,0xdead,fr13
    549. 

  549. 	set_spr_immed	0,msr0
    550. 

  550. 	set_spr_immed	0,msr1
    551. 

  551. 	set_fr_iimmed	0x0001,0x0001,fr10
    552. 

  552. 	set_fr_iimmed	0x8000,0x8000,fr11
    553. 

  553. 	cmsubhss.p	fr10,fr10,fr12,cc7,1
    554. 

  554. 	cmsubhss	fr11,fr10,fr13,cc7,0
    555. 

  555. 	test_fr_limmed	0xdead,0xbeef,fr12
    556. 

  556. 	test_fr_limmed	0xbeef,0xdead,fr13
    557. 

  557. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    558. 

  558. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    559. 

  559. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    560. 

  560. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    561. 

  561. 

  562. 	pass
    563.