| 123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138 |
- # frv testcase for cor $GRi,$GRj,$GRk,$CCi,$cond
- # mach: all
- .include "testutils.inc"
- start
- .global cor
- cor:
- set_spr_immed 0x1b1b,cccr
- set_gr_limmed 0xaaaa,0xaaaa,gr7
- set_gr_limmed 0x5555,0x5555,gr8
- set_icc 0x07,0 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc0,1
- test_icc 0 1 1 1 icc0
- test_gr_limmed 0xffff,0xffff,gr8
- set_gr_immed 0x00000000,gr7
- set_gr_immed 0x00000000,gr8
- set_icc 0x08,0 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc0,1
- test_icc 1 0 0 0 icc0
- test_gr_immed 0x00000000,gr8
- set_gr_limmed 0xdead,0x0000,gr7
- set_gr_limmed 0x0000,0xbeef,gr8
- set_icc 0x05,0 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc4,1
- test_icc 0 1 0 1 icc0
- test_gr_limmed 0xdead,0xbeef,gr8
- set_gr_limmed 0xaaaa,0xaaaa,gr7
- set_gr_limmed 0x5555,0x5555,gr8
- set_icc 0x07,0 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc0,0
- test_icc 0 1 1 1 icc0
- test_gr_limmed 0x5555,0x5555,gr8
- set_gr_immed 0x00007fff,gr7
- set_gr_immed 0x00000000,gr8
- set_icc 0x08,0 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc0,0
- test_icc 1 0 0 0 icc0
- test_gr_immed 0x00000000,gr8
- set_gr_limmed 0xdead,0x0000,gr7
- set_gr_limmed 0x0000,0xbeef,gr8
- set_icc 0x05,0 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc4,0
- test_icc 0 1 0 1 icc0
- test_gr_limmed 0x0000,0xbeef,gr8
- set_gr_limmed 0xaaaa,0xaaaa,gr7
- set_gr_limmed 0x5555,0x5555,gr8
- set_icc 0x07,1 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc1,0
- test_icc 0 1 1 1 icc1
- test_gr_limmed 0xffff,0xffff,gr8
- set_gr_immed 0x00000000,gr7
- set_gr_immed 0x00000000,gr8
- set_icc 0x08,1 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc1,0
- test_icc 1 0 0 0 icc1
- test_gr_immed 0x00000000,gr8
- set_gr_limmed 0xdead,0x0000,gr7
- set_gr_limmed 0x0000,0xbeef,gr8
- set_icc 0x05,1 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc5,0
- test_icc 0 1 0 1 icc1
- test_gr_limmed 0xdead,0xbeef,gr8
- set_gr_limmed 0xaaaa,0xaaaa,gr7
- set_gr_limmed 0x5555,0x5555,gr8
- set_icc 0x07,1 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc1,1
- test_icc 0 1 1 1 icc1
- test_gr_limmed 0x5555,0x5555,gr8
- set_gr_immed 0x00007fff,gr7
- set_gr_immed 0x00000000,gr8
- set_icc 0x08,1 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc1,1
- test_icc 1 0 0 0 icc1
- test_gr_immed 0x00000000,gr8
- set_gr_limmed 0xdead,0x0000,gr7
- set_gr_limmed 0x0000,0xbeef,gr8
- set_icc 0x05,1 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc5,1
- test_icc 0 1 0 1 icc1
- test_gr_limmed 0x0000,0xbeef,gr8
- set_gr_limmed 0xaaaa,0xaaaa,gr7
- set_gr_limmed 0x5555,0x5555,gr8
- set_icc 0x07,2 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc2,0
- test_icc 0 1 1 1 icc2
- test_gr_limmed 0x5555,0x5555,gr8
- set_gr_immed 0x00007fff,gr7
- set_gr_immed 0x00000000,gr8
- set_icc 0x08,2 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc2,0
- test_icc 1 0 0 0 icc2
- test_gr_immed 0x00000000,gr8
- set_gr_limmed 0xdead,0x0000,gr7
- set_gr_limmed 0x0000,0xbeef,gr8
- set_icc 0x05,2 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc6,1
- test_icc 0 1 0 1 icc2
- test_gr_limmed 0x0000,0xbeef,gr8
- set_gr_limmed 0xaaaa,0xaaaa,gr7
- set_gr_limmed 0x5555,0x5555,gr8
- set_icc 0x07,3 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc3,0
- test_icc 0 1 1 1 icc3
- test_gr_limmed 0x5555,0x5555,gr8
- set_gr_immed 0x00007fff,gr7
- set_gr_immed 0x00000000,gr8
- set_icc 0x08,3 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc3,0
- test_icc 1 0 0 0 icc3
- test_gr_immed 0x00000000,gr8
- set_gr_limmed 0xdead,0x0000,gr7
- set_gr_limmed 0x0000,0xbeef,gr8
- set_icc 0x05,3 ; Set mask opposite of expected
- cor gr7,gr8,gr8,cc7,1
- test_icc 0 1 0 1 icc3
- test_gr_limmed 0x0000,0xbeef,gr8
- pass
|
