ftug.cgs 2.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109
  1. # frv testcase for ftug $FCCi_2,$GRi,$GRj
  2. # mach: all
  3. .include "testutils.inc"
  4. start
  5. .global ftug
  6. ftug:
  7. and_spr_immed -4081,tbr ; clear tbr.tt
  8. set_gr_spr tbr,gr7
  9. inc_gr_immed 2112,gr7 ; address of exception handler
  10. set_bctrlr_0_0 gr7 ; bctrlr 0,0
  11. set_spr_immed 128,lcr
  12. set_gr_immed 0,gr7
  13. set_gr_immed 4,gr8
  14. set_spr_addr bad,lr
  15. set_fcc 0x0 0
  16. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  17. set_psr_et 1
  18. set_spr_addr ok1,lr
  19. set_fcc 0x1 0
  20. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  21. fail
  22. ok1:
  23. set_psr_et 1
  24. set_spr_addr ok2,lr
  25. set_fcc 0x2 0
  26. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  27. fail
  28. ok2:
  29. set_psr_et 1
  30. set_spr_addr ok3,lr
  31. set_fcc 0x3 0
  32. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  33. fail
  34. ok3:
  35. set_spr_addr bad,lr
  36. set_fcc 0x4 0
  37. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  38. set_psr_et 1
  39. set_spr_addr ok5,lr
  40. set_fcc 0x5 0
  41. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  42. fail
  43. ok5:
  44. set_psr_et 1
  45. set_spr_addr ok6,lr
  46. set_fcc 0x6 0
  47. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  48. fail
  49. ok6:
  50. set_psr_et 1
  51. set_spr_addr ok7,lr
  52. set_fcc 0x7 0
  53. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  54. fail
  55. ok7:
  56. set_spr_addr bad,lr
  57. set_fcc 0x8 0
  58. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  59. set_psr_et 1
  60. set_spr_addr ok9,lr
  61. set_fcc 0x9 0
  62. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  63. fail
  64. ok9:
  65. set_psr_et 1
  66. set_spr_addr oka,lr
  67. set_fcc 0xa 0
  68. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  69. fail
  70. oka:
  71. set_psr_et 1
  72. set_spr_addr okb,lr
  73. set_fcc 0xb 0
  74. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  75. fail
  76. okb:
  77. set_spr_addr bad,lr
  78. set_fcc 0xc 0
  79. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  80. set_psr_et 1
  81. set_spr_addr okd,lr
  82. set_fcc 0xd 0
  83. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  84. fail
  85. okd:
  86. set_psr_et 1
  87. set_spr_addr oke,lr
  88. set_fcc 0xe 0
  89. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  90. fail
  91. oke:
  92. set_psr_et 1
  93. set_spr_addr okf,lr
  94. set_fcc 0xf 0
  95. ftug fcc0,gr7,gr8 ; should branch to tbr + (128 + 4)*16
  96. fail
  97. okf:
  98. pass
  99. bad:
  100. fail