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mqmachs.cgs

mqmachs.cgs 6.7 KB
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  1. # frv testcase for mqmachs $GRi,$GRj,$ACCk
    2. 

  2. # mach: frv fr500 fr400
    3. 

  3. 

  4. 	.include "testutils.inc"
    5. 

  5. 

  6. 	start
    7. 

  7. 

  8. 	.global mqmachs
    9. 

  9. mqmachs:
    10. 

  10. 	; Positive operands
    11. 

  11. 	set_fr_iimmed  	2,3,fr8		; multiply small numbers
    12. 

  12. 	set_fr_iimmed  	3,2,fr10
    13. 

  13. 	set_fr_iimmed  	0,1,fr9		; multiply by 0
    14. 

  14. 	set_fr_iimmed  	2,0,fr11
    15. 

  15. 	mqmachs      	fr8,fr10,acc0
    16. 

  16. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    17. 

  17. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    18. 

  18. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    19. 

  19. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    20. 

  20. 	test_accg_immed 	0,accg0
    21. 

  21. 	test_acc_immed 	6,acc0
    22. 

  22. 	test_accg_immed 	0,accg1
    23. 

  23. 	test_acc_immed 	6,acc1
    24. 

  24. 	test_accg_immed 	0,accg2
    25. 

  25. 	test_acc_immed 	0,acc2
    26. 

  26. 	test_accg_immed 	0,accg3
    27. 

  27. 	test_acc_immed 	0,acc3
    28. 

  28. 

  29. 	set_fr_iimmed  	2,1,fr8		; multiply by 1
    30. 

  30. 	set_fr_iimmed  	1,2,fr10
    31. 

  31. 	set_fr_iimmed	0x3fff,2,fr9	; 15 bit result
    32. 

  32. 	set_fr_iimmed  	2,0x3fff,fr11
    33. 

  33. 	mqmachs      	fr8,fr10,acc0
    34. 

  34. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    35. 

  35. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    36. 

  36. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    37. 

  37. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    38. 

  38. 	test_accg_immed 	0,accg0
    39. 

  39. 	test_acc_immed 	8,acc0
    40. 

  40. 	test_accg_immed 	0,accg1
    41. 

  41. 	test_acc_immed 	8,acc1
    42. 

  42. 	test_accg_immed 	0,accg2
    43. 

  43. 	test_acc_limmed	0,0x7ffe,acc2
    44. 

  44. 	test_accg_immed 	0,accg3
    45. 

  45. 	test_acc_limmed	0,0x7ffe,acc3
    46. 

  46. 

  47. 	set_fr_iimmed	0x4000,2,fr8	; 16 bit result
    48. 

  48. 	set_fr_iimmed  	2,0x4000,fr10
    49. 

  49. 	set_fr_iimmed	0x7fff,0x7fff,fr9	; max positive result
    50. 

  50. 	set_fr_iimmed	0x7fff,0x7fff,fr11
    51. 

  51. 	mqmachs      	fr8,fr10,acc0
    52. 

  52. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    53. 

  53. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    54. 

  54. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    55. 

  55. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    56. 

  56. 	test_accg_immed 	0,accg0
    57. 

  57. 	test_acc_limmed	0x0000,0x8008,acc0
    58. 

  58. 	test_accg_immed 	0,accg1
    59. 

  59. 	test_acc_limmed	0x0000,0x8008,acc1
    60. 

  60. 	test_accg_immed 	0,accg2
    61. 

  61. 	test_acc_limmed 0x3fff,0x7fff,acc2
    62. 

  62. 	test_accg_immed 	0,accg3
    63. 

  63. 	test_acc_limmed 0x3fff,0x7fff,acc3
    64. 

  64. 

  65. 	; Mixed operands
    66. 

  66. 	set_fr_iimmed  	2,0xfffd,fr8		; multiply small numbers
    67. 

  67. 	set_fr_iimmed  	0xfffd,2,fr10
    68. 

  68. 	set_fr_iimmed  	0xfffe,1,fr9		; multiply by 1
    69. 

  69. 	set_fr_iimmed  	1,0xfffe,fr11
    70. 

  70. 	mqmachs      	fr8,fr10,acc0
    71. 

  71. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    72. 

  72. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    73. 

  73. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    74. 

  74. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    75. 

  75. 	test_accg_immed 	0,accg0
    76. 

  76. 	test_acc_limmed 0x0000,0x8002,acc0
    77. 

  77. 	test_accg_immed 	0,accg1
    78. 

  78. 	test_acc_limmed 0x0000,0x8002,acc1
    79. 

  79. 	test_accg_immed 	0,accg2
    80. 

  80. 	test_acc_limmed 0x3fff,0x7ffd,acc2
    81. 

  81. 	test_accg_immed 	0,accg3
    82. 

  82. 	test_acc_limmed 0x3fff,0x7ffd,acc3
    83. 

  83. 

  84. 	set_fr_iimmed  	0xfffe,0,fr8		; multiply by 0
    85. 

  85. 	set_fr_iimmed  	0,0xfffe,fr10
    86. 

  86. 	set_fr_iimmed  	0x2001,0xfffe,fr9	; 15 bit result
    87. 

  87. 	set_fr_iimmed  	0xfffe,0x2001,fr11
    88. 

  88. 	mqmachs      	fr8,fr10,acc0
    89. 

  89. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    90. 

  90. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    91. 

  91. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    92. 

  92. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    93. 

  93. 	test_accg_immed 	0,accg0
    94. 

  94. 	test_acc_limmed 0x0000,0x8002,acc0
    95. 

  95. 	test_accg_immed 	0,accg1
    96. 

  96. 	test_acc_limmed 0x0000,0x8002,acc1
    97. 

  97. 	test_accg_immed 	0,accg2
    98. 

  98. 	test_acc_limmed	0x3fff,0x3ffb,acc2
    99. 

  99. 	test_accg_immed 	0,accg3
    100. 

  100. 	test_acc_limmed	0x3fff,0x3ffb,acc3
    101. 

  101. 

  102. 	set_fr_iimmed	0x4000,0xfffe,fr8	; 16 bit result
    103. 

  103. 	set_fr_iimmed  	0xfffe,0x4000,fr10
    104. 

  104. 	set_fr_iimmed	0x7fff,0x8000,fr9	; max negative result
    105. 

  105. 	set_fr_iimmed	0x8000,0x7fff,fr11
    106. 

  106. 	mqmachs      	fr8,fr10,acc0
    107. 

  107. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    108. 

  108. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    109. 

  109. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    110. 

  110. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    111. 

  111. 	test_accg_immed 	0,accg0
    112. 

  112. 	test_acc_limmed	0x0000,0x0002,acc0
    113. 

  113. 	test_accg_immed 	0,accg1
    114. 

  114. 	test_acc_limmed	0x0000,0x0002,acc1
    115. 

  115. 	test_accg_immed 	0xff,accg2
    116. 

  116. 	test_acc_limmed	0xffff,0xbffb,acc2
    117. 

  117. 	test_accg_immed 	0xff,accg3
    118. 

  118. 	test_acc_limmed	0xffff,0xbffb,acc3
    119. 

  119. 

  120. 	; Negative operands
    121. 

  121. 	set_fr_iimmed  	0xfffe,0xfffd,fr8		; multiply small numbers
    122. 

  122. 	set_fr_iimmed  	0xfffd,0xfffe,fr10
    123. 

  123. 	set_fr_iimmed  	0xffff,0xfffe,fr9		; multiply by -1
    124. 

  124. 	set_fr_iimmed  	0xfffe,0xffff,fr11
    125. 

  125. 	mqmachs      	fr8,fr10,acc0
    126. 

  126. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    127. 

  127. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    128. 

  128. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    129. 

  129. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    130. 

  130. 	test_accg_immed 	0,accg0
    131. 

  131. 	test_acc_limmed	0x0000,0x0008,acc0
    132. 

  132. 	test_accg_immed 	0,accg1
    133. 

  133. 	test_acc_limmed	0x0000,0x0008,acc1
    134. 

  134. 	test_accg_immed 	0xff,accg2
    135. 

  135. 	test_acc_limmed	0xffff,0xbffd,acc2
    136. 

  136. 	test_accg_immed 	0xff,accg3
    137. 

  137. 	test_acc_limmed	0xffff,0xbffd,acc3
    138. 

  138. 

  139. 	set_fr_iimmed	0x8001,0x8001,fr8	; almost max positive result
    140. 

  140. 	set_fr_iimmed	0x8001,0x8001,fr10
    141. 

  141. 	set_fr_iimmed	0x8000,0x8000,fr9	; max positive result
    142. 

  142. 	set_fr_iimmed	0x8000,0x8000,fr11
    143. 

  143. 	mqmachs      	fr8,fr10,acc0
    144. 

  144. 	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
    145. 

  145. 	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
    146. 

  146. 	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
    147. 

  147. 	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
    148. 

  148. 	test_accg_immed 	0,accg0
    149. 

  149. 	test_acc_immed 	0x3fff0009,acc0
    150. 

  150. 	test_accg_immed 	0,accg1
    151. 

  151. 	test_acc_immed 	0x3fff0009,acc1
    152. 

  152. 	test_accg_immed 	0,accg2
    153. 

  153. 	test_acc_immed 	0x3fffbffd,acc2
    154. 

  154. 	test_accg_immed 	0,accg3
    155. 

  155. 	test_acc_immed 	0x3fffbffd,acc3
    156. 

  156. 

  157. 	set_accg_immed 	0x7f,accg0		; saturation
    158. 

  158. 	set_acc_immed	0xffffffff,acc0
    159. 

  159. 	set_accg_immed 	0x7f,accg1
    160. 

  160. 	set_acc_immed	0xffffffff,acc1
    161. 

  161. 	set_accg_immed 	0x7f,accg2		; saturation
    162. 

  162. 	set_acc_immed	0xffffffff,acc2
    163. 

  163. 	set_accg_immed 	0x7f,accg3
    164. 

  164. 	set_acc_immed	0xffffffff,acc3
    165. 

  165. 	set_fr_iimmed  	1,1,fr8
    166. 

  166. 	set_fr_iimmed  	1,1,fr10
    167. 

  167. 	set_fr_iimmed  	0x7fff,0x7fff,fr9	; saturation
    168. 

  168. 	set_fr_iimmed  	0x7fff,0x7fff,fr11
    169. 

  169. 	mqmachs      	fr8,fr10,acc0
    170. 

  170. 	test_spr_bits	0x3c,2,0xf,msr0		; msr0.sie is set
    171. 

  171. 	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
    172. 

  172. 	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
    173. 

  173. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
    174. 

  174. 	test_accg_immed 	0x7f,accg0
    175. 

  175. 	test_acc_limmed	0xffff,0xffff,acc0
    176. 

  176. 	test_accg_immed 	0x7f,accg1
    177. 

  177. 	test_acc_limmed	0xffff,0xffff,acc1
    178. 

  178. 	test_accg_immed 	0x7f,accg2
    179. 

  179. 	test_acc_limmed	0xffff,0xffff,acc2
    180. 

  180. 	test_accg_immed 	0x7f,accg3
    181. 

  181. 	test_acc_limmed	0xffff,0xffff,acc3
    182. 

  182. 

  183. 	set_accg_immed 	0x80,accg0		; saturation
    184. 

  184. 	set_acc_immed	0,acc0
    185. 

  185. 	set_accg_immed 	0x80,accg1
    186. 

  186. 	set_acc_immed	0,acc1
    187. 

  187. 	set_accg_immed 	0x80,accg2		; saturation
    188. 

  188. 	set_acc_immed	0,acc2
    189. 

  189. 	set_accg_immed 	0x80,accg3
    190. 

  190. 	set_acc_immed	0,acc3
    191. 

  191. 	set_fr_iimmed  	0xffff,0,fr8
    192. 

  192. 	set_fr_iimmed  	1,0xffff,fr10
    193. 

  193. 	set_fr_iimmed  	0x0000,0x8000,fr9	; saturation
    194. 

  194. 	set_fr_iimmed  	0x7fff,0x7fff,fr11
    195. 

  195. 	mqmachs      	fr8,fr10,acc0
    196. 

  196. 	test_spr_bits	0x3c,2,0x9,msr0		; msr0.sie is set
    197. 

  197. 	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
    198. 

  198. 	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
    199. 

  199. 	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
    200. 

  200. 	test_accg_immed 	0x80,accg0
    201. 

  201. 	test_acc_immed	0,acc0
    202. 

  202. 	test_accg_immed 	0x80,accg1
    203. 

  203. 	test_acc_immed	0,acc1
    204. 

  204. 	test_accg_immed 	0x80,accg2
    205. 

  205. 	test_acc_immed	0,acc2
    206. 

  206. 	test_accg_immed 	0x80,accg3
    207. 

  207. 	test_acc_immed	0,acc3
    208. 

  208. 

  209. 	pass
    210. 

  210. 

  211.