fdiv.s 1.5 KB

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  1. # sh testcase for fdiv
  2. # mach: sh
  3. # as(sh): -defsym sim_cpu=0
  4. .include "testutils.inc"
  5. start
  6. fdiv_single:
  7. # Single test
  8. set_grs_a5a5
  9. set_fprs_a5a5
  10. single_prec
  11. # 1.0 / 0.0 should be INF
  12. # (and not crash the sim).
  13. fldi0 fr0
  14. fldi1 fr1
  15. fdiv fr0, fr1
  16. assert_fpreg_x 0x7f800000, fr1
  17. # 0.0 / 1.0 == 0.0.
  18. fldi0 fr0
  19. fldi1 fr1
  20. fdiv fr1, fr0
  21. assert_fpreg_x 0, fr0
  22. # 2.0 / 1.0 == 2.0.
  23. fldi1 fr1
  24. fldi1 fr2
  25. fadd fr2, fr2
  26. fdiv fr1, fr2
  27. assert_fpreg_i 2, fr2
  28. # (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
  29. fldi1 fr1
  30. fldi1 fr2
  31. fadd fr2, fr2
  32. fdiv fr2, fr1
  33. # fr1 should contain 0.5.
  34. fadd fr1, fr1
  35. assert_fpreg_i 1, fr1
  36. test_grs_a5a5
  37. assert_fpreg_i 2, fr2
  38. test_fpr_a5a5 fr3
  39. test_fpr_a5a5 fr4
  40. test_fpr_a5a5 fr5
  41. test_fpr_a5a5 fr6
  42. test_fpr_a5a5 fr7
  43. test_fpr_a5a5 fr8
  44. test_fpr_a5a5 fr9
  45. test_fpr_a5a5 fr10
  46. test_fpr_a5a5 fr11
  47. test_fpr_a5a5 fr12
  48. test_fpr_a5a5 fr13
  49. test_fpr_a5a5 fr14
  50. test_fpr_a5a5 fr15
  51. fdiv_double:
  52. # Double test
  53. set_grs_a5a5
  54. set_fprs_a5a5
  55. # (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
  56. fldi1 fr1
  57. fldi1 fr2
  58. # This add must be in single precision. The rest must be in double.
  59. fadd fr2, fr2
  60. double_prec
  61. _s2d fr1, dr0
  62. _s2d fr2, dr2
  63. fdiv dr2, dr0
  64. # dr0 should contain 0.5.
  65. # double it, expect 1.0.
  66. fadd dr0, dr0
  67. assert_dpreg_i 1, dr0
  68. assert_dpreg_i 2, dr2
  69. test_grs_a5a5
  70. test_fpr_a5a5 fr4
  71. test_fpr_a5a5 fr5
  72. test_fpr_a5a5 fr6
  73. test_fpr_a5a5 fr7
  74. test_fpr_a5a5 fr8
  75. test_fpr_a5a5 fr9
  76. test_fpr_a5a5 fr10
  77. test_fpr_a5a5 fr11
  78. test_fpr_a5a5 fr12
  79. test_fpr_a5a5 fr13
  80. test_fpr_a5a5 fr14
  81. test_fpr_a5a5 fr15
  82. pass
  83. exit 0